1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/of_address.h> 14 #include <linux/of_graph.h> 15 #include <linux/reset.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_fb_cma_helper.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_plane_helper.h> 25 26 #include <video/videomode.h> 27 28 #include "ltdc.h" 29 30 #define NB_CRTC 1 31 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 32 33 #define MAX_IRQ 4 34 35 #define MAX_ENDPOINTS 2 36 37 #define HWVER_10200 0x010200 38 #define HWVER_10300 0x010300 39 #define HWVER_20101 0x020101 40 41 /* 42 * The address of some registers depends on the HW version: such registers have 43 * an extra offset specified with reg_ofs. 44 */ 45 #define REG_OFS_NONE 0 46 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 47 #define REG_OFS (ldev->caps.reg_ofs) 48 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 49 50 /* Global register offsets */ 51 #define LTDC_IDR 0x0000 /* IDentification */ 52 #define LTDC_LCR 0x0004 /* Layer Count */ 53 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 54 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 55 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 56 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 57 #define LTDC_GCR 0x0018 /* Global Control */ 58 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 59 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 60 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 61 #define LTDC_GACR 0x0028 /* GAmma Correction */ 62 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 63 #define LTDC_IER 0x0034 /* Interrupt Enable */ 64 #define LTDC_ISR 0x0038 /* Interrupt Status */ 65 #define LTDC_ICR 0x003C /* Interrupt Clear */ 66 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 67 #define LTDC_CPSR 0x0044 /* Current Position Status */ 68 #define LTDC_CDSR 0x0048 /* Current Display Status */ 69 70 /* Layer register offsets */ 71 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 72 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 73 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 74 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 75 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 76 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 77 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 78 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 79 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 80 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 81 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 82 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 83 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 84 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 85 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 86 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 87 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 88 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 89 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 90 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 91 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 92 93 /* Bit definitions */ 94 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 95 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 96 97 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 98 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 99 100 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 101 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 102 103 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 104 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 105 106 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 107 #define GCR_DEN BIT(16) /* Dither ENable */ 108 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 109 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 110 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 111 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 112 113 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 114 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 115 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 116 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 117 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 118 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 119 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 120 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 121 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 122 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 123 #define GC1R_TP BIT(25) /* Timing Programmable */ 124 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 125 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 126 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 127 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 128 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 129 130 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 131 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 132 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 133 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 134 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 135 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 136 137 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 138 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 139 140 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 141 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 142 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 143 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 144 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 145 146 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 147 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 148 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 149 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 150 151 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 152 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 153 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 154 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 155 156 #define LXCR_LEN BIT(0) /* Layer ENable */ 157 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 158 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 159 160 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 161 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 162 163 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 164 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 165 166 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 167 168 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 169 170 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 171 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 172 173 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 174 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 175 176 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 177 178 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 179 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 180 #define BF1_CA 0x400 /* Constant Alpha */ 181 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 182 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 183 184 #define NB_PF 8 /* Max nb of HW pixel format */ 185 186 enum ltdc_pix_fmt { 187 PF_NONE, 188 /* RGB formats */ 189 PF_ARGB8888, /* ARGB [32 bits] */ 190 PF_RGBA8888, /* RGBA [32 bits] */ 191 PF_RGB888, /* RGB [24 bits] */ 192 PF_RGB565, /* RGB [16 bits] */ 193 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 194 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 195 /* Indexed formats */ 196 PF_L8, /* Indexed 8 bits [8 bits] */ 197 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 198 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 199 }; 200 201 /* The index gives the encoding of the pixel format for an HW version */ 202 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 203 PF_ARGB8888, /* 0x00 */ 204 PF_RGB888, /* 0x01 */ 205 PF_RGB565, /* 0x02 */ 206 PF_ARGB1555, /* 0x03 */ 207 PF_ARGB4444, /* 0x04 */ 208 PF_L8, /* 0x05 */ 209 PF_AL44, /* 0x06 */ 210 PF_AL88 /* 0x07 */ 211 }; 212 213 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 214 PF_ARGB8888, /* 0x00 */ 215 PF_RGB888, /* 0x01 */ 216 PF_RGB565, /* 0x02 */ 217 PF_RGBA8888, /* 0x03 */ 218 PF_AL44, /* 0x04 */ 219 PF_L8, /* 0x05 */ 220 PF_ARGB1555, /* 0x06 */ 221 PF_ARGB4444 /* 0x07 */ 222 }; 223 224 static inline u32 reg_read(void __iomem *base, u32 reg) 225 { 226 return readl_relaxed(base + reg); 227 } 228 229 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 230 { 231 writel_relaxed(val, base + reg); 232 } 233 234 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 235 { 236 reg_write(base, reg, reg_read(base, reg) | mask); 237 } 238 239 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 240 { 241 reg_write(base, reg, reg_read(base, reg) & ~mask); 242 } 243 244 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 245 u32 val) 246 { 247 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 248 } 249 250 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 251 { 252 return (struct ltdc_device *)crtc->dev->dev_private; 253 } 254 255 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 256 { 257 return (struct ltdc_device *)plane->dev->dev_private; 258 } 259 260 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 261 { 262 return (struct ltdc_device *)enc->dev->dev_private; 263 } 264 265 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 266 { 267 enum ltdc_pix_fmt pf; 268 269 switch (drm_fmt) { 270 case DRM_FORMAT_ARGB8888: 271 case DRM_FORMAT_XRGB8888: 272 pf = PF_ARGB8888; 273 break; 274 case DRM_FORMAT_RGBA8888: 275 case DRM_FORMAT_RGBX8888: 276 pf = PF_RGBA8888; 277 break; 278 case DRM_FORMAT_RGB888: 279 pf = PF_RGB888; 280 break; 281 case DRM_FORMAT_RGB565: 282 pf = PF_RGB565; 283 break; 284 case DRM_FORMAT_ARGB1555: 285 case DRM_FORMAT_XRGB1555: 286 pf = PF_ARGB1555; 287 break; 288 case DRM_FORMAT_ARGB4444: 289 case DRM_FORMAT_XRGB4444: 290 pf = PF_ARGB4444; 291 break; 292 case DRM_FORMAT_C8: 293 pf = PF_L8; 294 break; 295 default: 296 pf = PF_NONE; 297 break; 298 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 299 } 300 301 return pf; 302 } 303 304 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 305 { 306 switch (pf) { 307 case PF_ARGB8888: 308 return DRM_FORMAT_ARGB8888; 309 case PF_RGBA8888: 310 return DRM_FORMAT_RGBA8888; 311 case PF_RGB888: 312 return DRM_FORMAT_RGB888; 313 case PF_RGB565: 314 return DRM_FORMAT_RGB565; 315 case PF_ARGB1555: 316 return DRM_FORMAT_ARGB1555; 317 case PF_ARGB4444: 318 return DRM_FORMAT_ARGB4444; 319 case PF_L8: 320 return DRM_FORMAT_C8; 321 case PF_AL44: /* No DRM support */ 322 case PF_AL88: /* No DRM support */ 323 case PF_NONE: 324 default: 325 return 0; 326 } 327 } 328 329 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 330 { 331 struct drm_device *ddev = arg; 332 struct ltdc_device *ldev = ddev->dev_private; 333 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 334 335 /* Line IRQ : trigger the vblank event */ 336 if (ldev->irq_status & ISR_LIF) 337 drm_crtc_handle_vblank(crtc); 338 339 /* Save FIFO Underrun & Transfer Error status */ 340 mutex_lock(&ldev->err_lock); 341 if (ldev->irq_status & ISR_FUIF) 342 ldev->error_status |= ISR_FUIF; 343 if (ldev->irq_status & ISR_TERRIF) 344 ldev->error_status |= ISR_TERRIF; 345 mutex_unlock(&ldev->err_lock); 346 347 return IRQ_HANDLED; 348 } 349 350 static irqreturn_t ltdc_irq(int irq, void *arg) 351 { 352 struct drm_device *ddev = arg; 353 struct ltdc_device *ldev = ddev->dev_private; 354 355 /* Read & Clear the interrupt status */ 356 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 357 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 358 359 return IRQ_WAKE_THREAD; 360 } 361 362 /* 363 * DRM_CRTC 364 */ 365 366 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 367 struct drm_crtc_state *old_state) 368 { 369 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 370 371 DRM_DEBUG_DRIVER("\n"); 372 373 /* Sets the background color value */ 374 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 375 376 /* Enable IRQ */ 377 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 378 379 /* Immediately commit the planes */ 380 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 381 382 /* Enable LTDC */ 383 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 384 385 drm_crtc_vblank_on(crtc); 386 } 387 388 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 389 struct drm_crtc_state *old_state) 390 { 391 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 392 393 DRM_DEBUG_DRIVER("\n"); 394 395 drm_crtc_vblank_off(crtc); 396 397 /* disable LTDC */ 398 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 399 400 /* disable IRQ */ 401 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 402 403 /* immediately commit disable of layers before switching off LTDC */ 404 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 405 } 406 407 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 408 { 409 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 410 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 411 struct videomode vm; 412 int rate = mode->clock * 1000; 413 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 414 u32 total_width, total_height; 415 u32 val; 416 417 drm_display_mode_to_videomode(mode, &vm); 418 419 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 420 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 421 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 422 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 423 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 424 425 /* Convert video timings to ltdc timings */ 426 hsync = vm.hsync_len - 1; 427 vsync = vm.vsync_len - 1; 428 accum_hbp = hsync + vm.hback_porch; 429 accum_vbp = vsync + vm.vback_porch; 430 accum_act_w = accum_hbp + vm.hactive; 431 accum_act_h = accum_vbp + vm.vactive; 432 total_width = accum_act_w + vm.hfront_porch; 433 total_height = accum_act_h + vm.vfront_porch; 434 435 clk_disable(ldev->pixel_clk); 436 437 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 438 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 439 return; 440 } 441 442 clk_enable(ldev->pixel_clk); 443 444 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 445 val = 0; 446 447 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 448 val |= GCR_HSPOL; 449 450 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 451 val |= GCR_VSPOL; 452 453 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 454 val |= GCR_DEPOL; 455 456 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 457 val |= GCR_PCPOL; 458 459 reg_update_bits(ldev->regs, LTDC_GCR, 460 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 461 462 /* Set Synchronization size */ 463 val = (hsync << 16) | vsync; 464 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 465 466 /* Set Accumulated Back porch */ 467 val = (accum_hbp << 16) | accum_vbp; 468 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 469 470 /* Set Accumulated Active Width */ 471 val = (accum_act_w << 16) | accum_act_h; 472 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 473 474 /* Set total width & height */ 475 val = (total_width << 16) | total_height; 476 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 477 478 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 479 } 480 481 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 482 struct drm_crtc_state *old_crtc_state) 483 { 484 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 485 struct drm_pending_vblank_event *event = crtc->state->event; 486 487 DRM_DEBUG_ATOMIC("\n"); 488 489 /* Commit shadow registers = update planes at next vblank */ 490 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 491 492 if (event) { 493 crtc->state->event = NULL; 494 495 spin_lock_irq(&crtc->dev->event_lock); 496 if (drm_crtc_vblank_get(crtc) == 0) 497 drm_crtc_arm_vblank_event(crtc, event); 498 else 499 drm_crtc_send_vblank_event(crtc, event); 500 spin_unlock_irq(&crtc->dev->event_lock); 501 } 502 } 503 504 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 505 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 506 .atomic_flush = ltdc_crtc_atomic_flush, 507 .atomic_enable = ltdc_crtc_atomic_enable, 508 .atomic_disable = ltdc_crtc_atomic_disable, 509 }; 510 511 int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe) 512 { 513 struct ltdc_device *ldev = ddev->dev_private; 514 515 DRM_DEBUG_DRIVER("\n"); 516 reg_set(ldev->regs, LTDC_IER, IER_LIE); 517 518 return 0; 519 } 520 521 void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe) 522 { 523 struct ltdc_device *ldev = ddev->dev_private; 524 525 DRM_DEBUG_DRIVER("\n"); 526 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 527 } 528 529 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 530 .destroy = drm_crtc_cleanup, 531 .set_config = drm_atomic_helper_set_config, 532 .page_flip = drm_atomic_helper_page_flip, 533 .reset = drm_atomic_helper_crtc_reset, 534 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 535 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 536 }; 537 538 /* 539 * DRM_PLANE 540 */ 541 542 static int ltdc_plane_atomic_check(struct drm_plane *plane, 543 struct drm_plane_state *state) 544 { 545 struct drm_framebuffer *fb = state->fb; 546 u32 src_x, src_y, src_w, src_h; 547 548 DRM_DEBUG_DRIVER("\n"); 549 550 if (!fb) 551 return 0; 552 553 /* convert src_ from 16:16 format */ 554 src_x = state->src_x >> 16; 555 src_y = state->src_y >> 16; 556 src_w = state->src_w >> 16; 557 src_h = state->src_h >> 16; 558 559 /* Reject scaling */ 560 if (src_w != state->crtc_w || src_h != state->crtc_h) { 561 DRM_ERROR("Scaling is not supported"); 562 return -EINVAL; 563 } 564 565 return 0; 566 } 567 568 static void ltdc_plane_atomic_update(struct drm_plane *plane, 569 struct drm_plane_state *oldstate) 570 { 571 struct ltdc_device *ldev = plane_to_ltdc(plane); 572 struct drm_plane_state *state = plane->state; 573 struct drm_framebuffer *fb = state->fb; 574 u32 lofs = plane->index * LAY_OFS; 575 u32 x0 = state->crtc_x; 576 u32 x1 = state->crtc_x + state->crtc_w - 1; 577 u32 y0 = state->crtc_y; 578 u32 y1 = state->crtc_y + state->crtc_h - 1; 579 u32 src_x, src_y, src_w, src_h; 580 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 581 enum ltdc_pix_fmt pf; 582 583 if (!state->crtc || !fb) { 584 DRM_DEBUG_DRIVER("fb or crtc NULL"); 585 return; 586 } 587 588 /* convert src_ from 16:16 format */ 589 src_x = state->src_x >> 16; 590 src_y = state->src_y >> 16; 591 src_w = state->src_w >> 16; 592 src_h = state->src_h >> 16; 593 594 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 595 plane->base.id, fb->base.id, 596 src_w, src_h, src_x, src_y, 597 state->crtc_w, state->crtc_h, 598 state->crtc_x, state->crtc_y); 599 600 bpcr = reg_read(ldev->regs, LTDC_BPCR); 601 ahbp = (bpcr & BPCR_AHBP) >> 16; 602 avbp = bpcr & BPCR_AVBP; 603 604 /* Configures the horizontal start and stop position */ 605 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 606 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 607 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 608 609 /* Configures the vertical start and stop position */ 610 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 611 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 612 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 613 614 /* Specifies the pixel format */ 615 pf = to_ltdc_pixelformat(fb->format->format); 616 for (val = 0; val < NB_PF; val++) 617 if (ldev->caps.pix_fmt_hw[val] == pf) 618 break; 619 620 if (val == NB_PF) { 621 DRM_ERROR("Pixel format %.4s not supported\n", 622 (char *)&fb->format->format); 623 val = 0; /* set by default ARGB 32 bits */ 624 } 625 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 626 627 /* Configures the color frame buffer pitch in bytes & line length */ 628 pitch_in_bytes = fb->pitches[0]; 629 line_length = drm_format_plane_cpp(fb->format->format, 0) * 630 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 631 val = ((pitch_in_bytes << 16) | line_length); 632 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 633 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 634 635 /* Specifies the constant alpha value */ 636 val = CONSTA_MAX; 637 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 638 639 /* Specifies the blending factors */ 640 val = BF1_PAXCA | BF2_1PAXCA; 641 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 642 LXBFCR_BF2 | LXBFCR_BF1, val); 643 644 /* Configures the frame buffer line number */ 645 val = y1 - y0 + 1; 646 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 647 648 /* Sets the FB address */ 649 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 650 651 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 652 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 653 654 /* Enable layer and CLUT if needed */ 655 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 656 val |= LXCR_LEN; 657 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 658 LXCR_LEN | LXCR_CLUTEN, val); 659 660 mutex_lock(&ldev->err_lock); 661 if (ldev->error_status & ISR_FUIF) { 662 DRM_DEBUG_DRIVER("Fifo underrun\n"); 663 ldev->error_status &= ~ISR_FUIF; 664 } 665 if (ldev->error_status & ISR_TERRIF) { 666 DRM_DEBUG_DRIVER("Transfer error\n"); 667 ldev->error_status &= ~ISR_TERRIF; 668 } 669 mutex_unlock(&ldev->err_lock); 670 } 671 672 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 673 struct drm_plane_state *oldstate) 674 { 675 struct ltdc_device *ldev = plane_to_ltdc(plane); 676 u32 lofs = plane->index * LAY_OFS; 677 678 /* disable layer */ 679 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 680 681 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 682 oldstate->crtc->base.id, plane->base.id); 683 } 684 685 static const struct drm_plane_funcs ltdc_plane_funcs = { 686 .update_plane = drm_atomic_helper_update_plane, 687 .disable_plane = drm_atomic_helper_disable_plane, 688 .destroy = drm_plane_cleanup, 689 .reset = drm_atomic_helper_plane_reset, 690 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 691 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 692 }; 693 694 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 695 .atomic_check = ltdc_plane_atomic_check, 696 .atomic_update = ltdc_plane_atomic_update, 697 .atomic_disable = ltdc_plane_atomic_disable, 698 }; 699 700 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 701 enum drm_plane_type type) 702 { 703 unsigned long possible_crtcs = CRTC_MASK; 704 struct ltdc_device *ldev = ddev->dev_private; 705 struct device *dev = ddev->dev; 706 struct drm_plane *plane; 707 unsigned int i, nb_fmt = 0; 708 u32 formats[NB_PF]; 709 u32 drm_fmt; 710 int ret; 711 712 /* Get supported pixel formats */ 713 for (i = 0; i < NB_PF; i++) { 714 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 715 if (!drm_fmt) 716 continue; 717 formats[nb_fmt++] = drm_fmt; 718 } 719 720 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 721 if (!plane) 722 return 0; 723 724 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 725 <dc_plane_funcs, formats, nb_fmt, 726 NULL, type, NULL); 727 if (ret < 0) 728 return 0; 729 730 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 731 732 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 733 734 return plane; 735 } 736 737 static void ltdc_plane_destroy_all(struct drm_device *ddev) 738 { 739 struct drm_plane *plane, *plane_temp; 740 741 list_for_each_entry_safe(plane, plane_temp, 742 &ddev->mode_config.plane_list, head) 743 drm_plane_cleanup(plane); 744 } 745 746 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 747 { 748 struct ltdc_device *ldev = ddev->dev_private; 749 struct drm_plane *primary, *overlay; 750 unsigned int i; 751 int ret; 752 753 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 754 if (!primary) { 755 DRM_ERROR("Can not create primary plane\n"); 756 return -EINVAL; 757 } 758 759 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 760 <dc_crtc_funcs, NULL); 761 if (ret) { 762 DRM_ERROR("Can not initialize CRTC\n"); 763 goto cleanup; 764 } 765 766 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 767 768 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 769 770 /* Add planes. Note : the first layer is used by primary plane */ 771 for (i = 1; i < ldev->caps.nb_layers; i++) { 772 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 773 if (!overlay) { 774 ret = -ENOMEM; 775 DRM_ERROR("Can not create overlay plane %d\n", i); 776 goto cleanup; 777 } 778 } 779 780 return 0; 781 782 cleanup: 783 ltdc_plane_destroy_all(ddev); 784 return ret; 785 } 786 787 /* 788 * DRM_ENCODER 789 */ 790 791 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 792 .destroy = drm_encoder_cleanup, 793 }; 794 795 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 796 { 797 struct drm_encoder *encoder; 798 int ret; 799 800 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 801 if (!encoder) 802 return -ENOMEM; 803 804 encoder->possible_crtcs = CRTC_MASK; 805 encoder->possible_clones = 0; /* No cloning support */ 806 807 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 808 DRM_MODE_ENCODER_DPI, NULL); 809 810 ret = drm_bridge_attach(encoder, bridge, NULL); 811 if (ret) { 812 drm_encoder_cleanup(encoder); 813 return -EINVAL; 814 } 815 816 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 817 818 return 0; 819 } 820 821 static int ltdc_get_caps(struct drm_device *ddev) 822 { 823 struct ltdc_device *ldev = ddev->dev_private; 824 u32 bus_width_log2, lcr, gc2r; 825 826 /* at least 1 layer must be managed */ 827 lcr = reg_read(ldev->regs, LTDC_LCR); 828 829 ldev->caps.nb_layers = max_t(int, lcr, 1); 830 831 /* set data bus width */ 832 gc2r = reg_read(ldev->regs, LTDC_GC2R); 833 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 834 ldev->caps.bus_width = 8 << bus_width_log2; 835 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 836 837 switch (ldev->caps.hw_version) { 838 case HWVER_10200: 839 case HWVER_10300: 840 ldev->caps.reg_ofs = REG_OFS_NONE; 841 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 842 break; 843 case HWVER_20101: 844 ldev->caps.reg_ofs = REG_OFS_4; 845 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 846 break; 847 default: 848 return -ENODEV; 849 } 850 851 return 0; 852 } 853 854 int ltdc_load(struct drm_device *ddev) 855 { 856 struct platform_device *pdev = to_platform_device(ddev->dev); 857 struct ltdc_device *ldev = ddev->dev_private; 858 struct device *dev = ddev->dev; 859 struct device_node *np = dev->of_node; 860 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 861 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 862 struct drm_crtc *crtc; 863 struct reset_control *rstc; 864 struct resource *res; 865 int irq, ret, i, endpoint_not_ready = -ENODEV; 866 867 DRM_DEBUG_DRIVER("\n"); 868 869 /* Get endpoints if any */ 870 for (i = 0; i < MAX_ENDPOINTS; i++) { 871 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 872 &bridge[i]); 873 874 /* 875 * If at least one endpoint is ready, continue probing, 876 * else if at least one endpoint is -EPROBE_DEFER and 877 * there is no previous ready endpoints, defer probing. 878 */ 879 if (!ret) 880 endpoint_not_ready = 0; 881 else if (ret == -EPROBE_DEFER && endpoint_not_ready) 882 endpoint_not_ready = -EPROBE_DEFER; 883 } 884 885 if (endpoint_not_ready) 886 return endpoint_not_ready; 887 888 rstc = devm_reset_control_get_exclusive(dev, NULL); 889 890 mutex_init(&ldev->err_lock); 891 892 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 893 if (IS_ERR(ldev->pixel_clk)) { 894 DRM_ERROR("Unable to get lcd clock\n"); 895 return -ENODEV; 896 } 897 898 if (clk_prepare_enable(ldev->pixel_clk)) { 899 DRM_ERROR("Unable to prepare pixel clock\n"); 900 return -ENODEV; 901 } 902 903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 904 ldev->regs = devm_ioremap_resource(dev, res); 905 if (IS_ERR(ldev->regs)) { 906 DRM_ERROR("Unable to get ltdc registers\n"); 907 ret = PTR_ERR(ldev->regs); 908 goto err; 909 } 910 911 for (i = 0; i < MAX_IRQ; i++) { 912 irq = platform_get_irq(pdev, i); 913 if (irq < 0) 914 continue; 915 916 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 917 ltdc_irq_thread, IRQF_ONESHOT, 918 dev_name(dev), ddev); 919 if (ret) { 920 DRM_ERROR("Failed to register LTDC interrupt\n"); 921 goto err; 922 } 923 } 924 925 if (!IS_ERR(rstc)) 926 reset_control_deassert(rstc); 927 928 /* Disable interrupts */ 929 reg_clear(ldev->regs, LTDC_IER, 930 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 931 932 ret = ltdc_get_caps(ddev); 933 if (ret) { 934 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 935 ldev->caps.hw_version); 936 goto err; 937 } 938 939 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 940 941 /* Add endpoints panels or bridges if any */ 942 for (i = 0; i < MAX_ENDPOINTS; i++) { 943 if (panel[i]) { 944 bridge[i] = drm_panel_bridge_add(panel[i], 945 DRM_MODE_CONNECTOR_DPI); 946 if (IS_ERR(bridge[i])) { 947 DRM_ERROR("panel-bridge endpoint %d\n", i); 948 ret = PTR_ERR(bridge[i]); 949 goto err; 950 } 951 } 952 953 if (bridge[i]) { 954 ret = ltdc_encoder_init(ddev, bridge[i]); 955 if (ret) { 956 DRM_ERROR("init encoder endpoint %d\n", i); 957 goto err; 958 } 959 } 960 } 961 962 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 963 if (!crtc) { 964 DRM_ERROR("Failed to allocate crtc\n"); 965 ret = -ENOMEM; 966 goto err; 967 } 968 969 ret = ltdc_crtc_init(ddev, crtc); 970 if (ret) { 971 DRM_ERROR("Failed to init crtc\n"); 972 goto err; 973 } 974 975 ret = drm_vblank_init(ddev, NB_CRTC); 976 if (ret) { 977 DRM_ERROR("Failed calling drm_vblank_init()\n"); 978 goto err; 979 } 980 981 /* Allow usage of vblank without having to call drm_irq_install */ 982 ddev->irq_enabled = 1; 983 984 return 0; 985 986 err: 987 for (i = 0; i < MAX_ENDPOINTS; i++) 988 drm_panel_bridge_remove(bridge[i]); 989 990 clk_disable_unprepare(ldev->pixel_clk); 991 992 return ret; 993 } 994 995 void ltdc_unload(struct drm_device *ddev) 996 { 997 struct ltdc_device *ldev = ddev->dev_private; 998 int i; 999 1000 DRM_DEBUG_DRIVER("\n"); 1001 1002 for (i = 0; i < MAX_ENDPOINTS; i++) 1003 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1004 1005 clk_disable_unprepare(ldev->pixel_clk); 1006 } 1007 1008 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1009 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1010 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1011 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1012 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1013 MODULE_LICENSE("GPL v2"); 1014