1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_device.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_gem_cma_helper.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_plane_helper.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/drm_vblank.h> 35 36 #include <video/videomode.h> 37 38 #include "ltdc.h" 39 40 #define NB_CRTC 1 41 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 42 43 #define MAX_IRQ 4 44 45 #define HWVER_10200 0x010200 46 #define HWVER_10300 0x010300 47 #define HWVER_20101 0x020101 48 49 /* 50 * The address of some registers depends on the HW version: such registers have 51 * an extra offset specified with reg_ofs. 52 */ 53 #define REG_OFS_NONE 0 54 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 55 #define REG_OFS (ldev->caps.reg_ofs) 56 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 57 58 /* Global register offsets */ 59 #define LTDC_IDR 0x0000 /* IDentification */ 60 #define LTDC_LCR 0x0004 /* Layer Count */ 61 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 62 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 63 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 64 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 65 #define LTDC_GCR 0x0018 /* Global Control */ 66 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 67 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 68 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 69 #define LTDC_GACR 0x0028 /* GAmma Correction */ 70 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 71 #define LTDC_IER 0x0034 /* Interrupt Enable */ 72 #define LTDC_ISR 0x0038 /* Interrupt Status */ 73 #define LTDC_ICR 0x003C /* Interrupt Clear */ 74 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 75 #define LTDC_CPSR 0x0044 /* Current Position Status */ 76 #define LTDC_CDSR 0x0048 /* Current Display Status */ 77 78 /* Layer register offsets */ 79 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 80 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 81 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 82 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 83 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 84 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 85 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 86 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 87 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 88 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 89 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 90 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 91 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 92 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 93 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 94 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 95 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 96 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 97 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 98 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 99 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 100 101 /* Bit definitions */ 102 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 103 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 104 105 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 106 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 107 108 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 109 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 110 111 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 112 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 113 114 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 115 #define GCR_DEN BIT(16) /* Dither ENable */ 116 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 117 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 118 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 119 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 120 121 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 122 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 123 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 124 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 125 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 126 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 127 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 128 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 129 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 130 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 131 #define GC1R_TP BIT(25) /* Timing Programmable */ 132 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 133 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 134 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 135 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 136 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 137 138 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 139 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 140 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 141 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 142 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 143 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 144 145 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 146 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 147 148 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 149 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 150 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 151 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 152 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 153 154 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 155 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 156 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 157 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 158 159 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 160 161 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 162 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 163 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 164 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 165 166 #define LXCR_LEN BIT(0) /* Layer ENable */ 167 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 168 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 169 170 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 171 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 172 173 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 174 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 175 176 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 177 178 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 179 180 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 181 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 182 183 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 184 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 185 186 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 187 188 #define CLUT_SIZE 256 189 190 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 191 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 192 #define BF1_CA 0x400 /* Constant Alpha */ 193 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 194 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 195 196 #define NB_PF 8 /* Max nb of HW pixel format */ 197 198 enum ltdc_pix_fmt { 199 PF_NONE, 200 /* RGB formats */ 201 PF_ARGB8888, /* ARGB [32 bits] */ 202 PF_RGBA8888, /* RGBA [32 bits] */ 203 PF_RGB888, /* RGB [24 bits] */ 204 PF_RGB565, /* RGB [16 bits] */ 205 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 206 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 207 /* Indexed formats */ 208 PF_L8, /* Indexed 8 bits [8 bits] */ 209 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 210 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 211 }; 212 213 /* The index gives the encoding of the pixel format for an HW version */ 214 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 215 PF_ARGB8888, /* 0x00 */ 216 PF_RGB888, /* 0x01 */ 217 PF_RGB565, /* 0x02 */ 218 PF_ARGB1555, /* 0x03 */ 219 PF_ARGB4444, /* 0x04 */ 220 PF_L8, /* 0x05 */ 221 PF_AL44, /* 0x06 */ 222 PF_AL88 /* 0x07 */ 223 }; 224 225 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 226 PF_ARGB8888, /* 0x00 */ 227 PF_RGB888, /* 0x01 */ 228 PF_RGB565, /* 0x02 */ 229 PF_RGBA8888, /* 0x03 */ 230 PF_AL44, /* 0x04 */ 231 PF_L8, /* 0x05 */ 232 PF_ARGB1555, /* 0x06 */ 233 PF_ARGB4444 /* 0x07 */ 234 }; 235 236 static const u64 ltdc_format_modifiers[] = { 237 DRM_FORMAT_MOD_LINEAR, 238 DRM_FORMAT_MOD_INVALID 239 }; 240 241 static inline u32 reg_read(void __iomem *base, u32 reg) 242 { 243 return readl_relaxed(base + reg); 244 } 245 246 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 247 { 248 writel_relaxed(val, base + reg); 249 } 250 251 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 252 { 253 reg_write(base, reg, reg_read(base, reg) | mask); 254 } 255 256 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 257 { 258 reg_write(base, reg, reg_read(base, reg) & ~mask); 259 } 260 261 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 262 u32 val) 263 { 264 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 265 } 266 267 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 268 { 269 return (struct ltdc_device *)crtc->dev->dev_private; 270 } 271 272 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 273 { 274 return (struct ltdc_device *)plane->dev->dev_private; 275 } 276 277 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 278 { 279 return (struct ltdc_device *)enc->dev->dev_private; 280 } 281 282 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 283 { 284 enum ltdc_pix_fmt pf; 285 286 switch (drm_fmt) { 287 case DRM_FORMAT_ARGB8888: 288 case DRM_FORMAT_XRGB8888: 289 pf = PF_ARGB8888; 290 break; 291 case DRM_FORMAT_RGBA8888: 292 case DRM_FORMAT_RGBX8888: 293 pf = PF_RGBA8888; 294 break; 295 case DRM_FORMAT_RGB888: 296 pf = PF_RGB888; 297 break; 298 case DRM_FORMAT_RGB565: 299 pf = PF_RGB565; 300 break; 301 case DRM_FORMAT_ARGB1555: 302 case DRM_FORMAT_XRGB1555: 303 pf = PF_ARGB1555; 304 break; 305 case DRM_FORMAT_ARGB4444: 306 case DRM_FORMAT_XRGB4444: 307 pf = PF_ARGB4444; 308 break; 309 case DRM_FORMAT_C8: 310 pf = PF_L8; 311 break; 312 default: 313 pf = PF_NONE; 314 break; 315 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 316 } 317 318 return pf; 319 } 320 321 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 322 { 323 switch (pf) { 324 case PF_ARGB8888: 325 return DRM_FORMAT_ARGB8888; 326 case PF_RGBA8888: 327 return DRM_FORMAT_RGBA8888; 328 case PF_RGB888: 329 return DRM_FORMAT_RGB888; 330 case PF_RGB565: 331 return DRM_FORMAT_RGB565; 332 case PF_ARGB1555: 333 return DRM_FORMAT_ARGB1555; 334 case PF_ARGB4444: 335 return DRM_FORMAT_ARGB4444; 336 case PF_L8: 337 return DRM_FORMAT_C8; 338 case PF_AL44: /* No DRM support */ 339 case PF_AL88: /* No DRM support */ 340 case PF_NONE: 341 default: 342 return 0; 343 } 344 } 345 346 static inline u32 get_pixelformat_without_alpha(u32 drm) 347 { 348 switch (drm) { 349 case DRM_FORMAT_ARGB4444: 350 return DRM_FORMAT_XRGB4444; 351 case DRM_FORMAT_RGBA4444: 352 return DRM_FORMAT_RGBX4444; 353 case DRM_FORMAT_ARGB1555: 354 return DRM_FORMAT_XRGB1555; 355 case DRM_FORMAT_RGBA5551: 356 return DRM_FORMAT_RGBX5551; 357 case DRM_FORMAT_ARGB8888: 358 return DRM_FORMAT_XRGB8888; 359 case DRM_FORMAT_RGBA8888: 360 return DRM_FORMAT_RGBX8888; 361 default: 362 return 0; 363 } 364 } 365 366 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 367 { 368 struct drm_device *ddev = arg; 369 struct ltdc_device *ldev = ddev->dev_private; 370 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 371 372 /* Line IRQ : trigger the vblank event */ 373 if (ldev->irq_status & ISR_LIF) 374 drm_crtc_handle_vblank(crtc); 375 376 /* Save FIFO Underrun & Transfer Error status */ 377 mutex_lock(&ldev->err_lock); 378 if (ldev->irq_status & ISR_FUIF) 379 ldev->error_status |= ISR_FUIF; 380 if (ldev->irq_status & ISR_TERRIF) 381 ldev->error_status |= ISR_TERRIF; 382 mutex_unlock(&ldev->err_lock); 383 384 return IRQ_HANDLED; 385 } 386 387 static irqreturn_t ltdc_irq(int irq, void *arg) 388 { 389 struct drm_device *ddev = arg; 390 struct ltdc_device *ldev = ddev->dev_private; 391 392 /* Read & Clear the interrupt status */ 393 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 394 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 395 396 return IRQ_WAKE_THREAD; 397 } 398 399 /* 400 * DRM_CRTC 401 */ 402 403 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 404 { 405 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 406 struct drm_color_lut *lut; 407 u32 val; 408 int i; 409 410 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 411 return; 412 413 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 414 415 for (i = 0; i < CLUT_SIZE; i++, lut++) { 416 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 417 (lut->blue >> 8) | (i << 24); 418 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 419 } 420 } 421 422 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 423 struct drm_atomic_state *state) 424 { 425 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 426 struct drm_device *ddev = crtc->dev; 427 428 DRM_DEBUG_DRIVER("\n"); 429 430 pm_runtime_get_sync(ddev->dev); 431 432 /* Sets the background color value */ 433 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 434 435 /* Enable IRQ */ 436 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 437 438 /* Commit shadow registers = update planes at next vblank */ 439 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 440 441 drm_crtc_vblank_on(crtc); 442 } 443 444 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 445 struct drm_atomic_state *state) 446 { 447 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 448 struct drm_device *ddev = crtc->dev; 449 450 DRM_DEBUG_DRIVER("\n"); 451 452 drm_crtc_vblank_off(crtc); 453 454 /* disable IRQ */ 455 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 456 457 /* immediately commit disable of layers before switching off LTDC */ 458 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 459 460 pm_runtime_put_sync(ddev->dev); 461 } 462 463 #define CLK_TOLERANCE_HZ 50 464 465 static enum drm_mode_status 466 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 467 const struct drm_display_mode *mode) 468 { 469 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 470 int target = mode->clock * 1000; 471 int target_min = target - CLK_TOLERANCE_HZ; 472 int target_max = target + CLK_TOLERANCE_HZ; 473 int result; 474 475 result = clk_round_rate(ldev->pixel_clk, target); 476 477 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 478 479 /* Filter modes according to the max frequency supported by the pads */ 480 if (result > ldev->caps.pad_max_freq_hz) 481 return MODE_CLOCK_HIGH; 482 483 /* 484 * Accept all "preferred" modes: 485 * - this is important for panels because panel clock tolerances are 486 * bigger than hdmi ones and there is no reason to not accept them 487 * (the fps may vary a little but it is not a problem). 488 * - the hdmi preferred mode will be accepted too, but userland will 489 * be able to use others hdmi "valid" modes if necessary. 490 */ 491 if (mode->type & DRM_MODE_TYPE_PREFERRED) 492 return MODE_OK; 493 494 /* 495 * Filter modes according to the clock value, particularly useful for 496 * hdmi modes that require precise pixel clocks. 497 */ 498 if (result < target_min || result > target_max) 499 return MODE_CLOCK_RANGE; 500 501 return MODE_OK; 502 } 503 504 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 505 const struct drm_display_mode *mode, 506 struct drm_display_mode *adjusted_mode) 507 { 508 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 509 int rate = mode->clock * 1000; 510 511 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 512 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 513 return false; 514 } 515 516 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 517 518 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 519 mode->clock, adjusted_mode->clock); 520 521 return true; 522 } 523 524 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 525 { 526 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 527 struct drm_device *ddev = crtc->dev; 528 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 529 struct videomode vm; 530 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 531 u32 total_width, total_height; 532 u32 val; 533 int ret; 534 535 if (!pm_runtime_active(ddev->dev)) { 536 ret = pm_runtime_get_sync(ddev->dev); 537 if (ret) { 538 DRM_ERROR("Failed to set mode, cannot get sync\n"); 539 return; 540 } 541 } 542 543 drm_display_mode_to_videomode(mode, &vm); 544 545 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 546 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 547 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 548 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 549 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 550 551 /* Convert video timings to ltdc timings */ 552 hsync = vm.hsync_len - 1; 553 vsync = vm.vsync_len - 1; 554 accum_hbp = hsync + vm.hback_porch; 555 accum_vbp = vsync + vm.vback_porch; 556 accum_act_w = accum_hbp + vm.hactive; 557 accum_act_h = accum_vbp + vm.vactive; 558 total_width = accum_act_w + vm.hfront_porch; 559 total_height = accum_act_h + vm.vfront_porch; 560 561 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 562 val = 0; 563 564 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 565 val |= GCR_HSPOL; 566 567 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 568 val |= GCR_VSPOL; 569 570 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 571 val |= GCR_DEPOL; 572 573 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 574 val |= GCR_PCPOL; 575 576 reg_update_bits(ldev->regs, LTDC_GCR, 577 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 578 579 /* Set Synchronization size */ 580 val = (hsync << 16) | vsync; 581 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 582 583 /* Set Accumulated Back porch */ 584 val = (accum_hbp << 16) | accum_vbp; 585 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 586 587 /* Set Accumulated Active Width */ 588 val = (accum_act_w << 16) | accum_act_h; 589 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 590 591 /* Set total width & height */ 592 val = (total_width << 16) | total_height; 593 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 594 595 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 596 } 597 598 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 599 struct drm_atomic_state *state) 600 { 601 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 602 struct drm_device *ddev = crtc->dev; 603 struct drm_pending_vblank_event *event = crtc->state->event; 604 605 DRM_DEBUG_ATOMIC("\n"); 606 607 ltdc_crtc_update_clut(crtc); 608 609 /* Commit shadow registers = update planes at next vblank */ 610 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 611 612 if (event) { 613 crtc->state->event = NULL; 614 615 spin_lock_irq(&ddev->event_lock); 616 if (drm_crtc_vblank_get(crtc) == 0) 617 drm_crtc_arm_vblank_event(crtc, event); 618 else 619 drm_crtc_send_vblank_event(crtc, event); 620 spin_unlock_irq(&ddev->event_lock); 621 } 622 } 623 624 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 625 bool in_vblank_irq, 626 int *vpos, int *hpos, 627 ktime_t *stime, ktime_t *etime, 628 const struct drm_display_mode *mode) 629 { 630 struct drm_device *ddev = crtc->dev; 631 struct ltdc_device *ldev = ddev->dev_private; 632 int line, vactive_start, vactive_end, vtotal; 633 634 if (stime) 635 *stime = ktime_get(); 636 637 /* The active area starts after vsync + front porch and ends 638 * at vsync + front porc + display size. 639 * The total height also include back porch. 640 * We have 3 possible cases to handle: 641 * - line < vactive_start: vpos = line - vactive_start and will be 642 * negative 643 * - vactive_start < line < vactive_end: vpos = line - vactive_start 644 * and will be positive 645 * - line > vactive_end: vpos = line - vtotal - vactive_start 646 * and will negative 647 * 648 * Computation for the two first cases are identical so we can 649 * simplify the code and only test if line > vactive_end 650 */ 651 if (pm_runtime_active(ddev->dev)) { 652 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 653 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 654 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 655 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 656 657 if (line > vactive_end) 658 *vpos = line - vtotal - vactive_start; 659 else 660 *vpos = line - vactive_start; 661 } else { 662 *vpos = 0; 663 } 664 665 *hpos = 0; 666 667 if (etime) 668 *etime = ktime_get(); 669 670 return true; 671 } 672 673 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 674 .mode_valid = ltdc_crtc_mode_valid, 675 .mode_fixup = ltdc_crtc_mode_fixup, 676 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 677 .atomic_flush = ltdc_crtc_atomic_flush, 678 .atomic_enable = ltdc_crtc_atomic_enable, 679 .atomic_disable = ltdc_crtc_atomic_disable, 680 .get_scanout_position = ltdc_crtc_get_scanout_position, 681 }; 682 683 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 684 { 685 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 686 struct drm_crtc_state *state = crtc->state; 687 688 DRM_DEBUG_DRIVER("\n"); 689 690 if (state->enable) 691 reg_set(ldev->regs, LTDC_IER, IER_LIE); 692 else 693 return -EPERM; 694 695 return 0; 696 } 697 698 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 699 { 700 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 701 702 DRM_DEBUG_DRIVER("\n"); 703 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 704 } 705 706 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 707 .destroy = drm_crtc_cleanup, 708 .set_config = drm_atomic_helper_set_config, 709 .page_flip = drm_atomic_helper_page_flip, 710 .reset = drm_atomic_helper_crtc_reset, 711 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 712 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 713 .enable_vblank = ltdc_crtc_enable_vblank, 714 .disable_vblank = ltdc_crtc_disable_vblank, 715 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 716 }; 717 718 /* 719 * DRM_PLANE 720 */ 721 722 static int ltdc_plane_atomic_check(struct drm_plane *plane, 723 struct drm_plane_state *state) 724 { 725 struct drm_framebuffer *fb = state->fb; 726 u32 src_w, src_h; 727 728 DRM_DEBUG_DRIVER("\n"); 729 730 if (!fb) 731 return 0; 732 733 /* convert src_ from 16:16 format */ 734 src_w = state->src_w >> 16; 735 src_h = state->src_h >> 16; 736 737 /* Reject scaling */ 738 if (src_w != state->crtc_w || src_h != state->crtc_h) { 739 DRM_ERROR("Scaling is not supported"); 740 return -EINVAL; 741 } 742 743 return 0; 744 } 745 746 static void ltdc_plane_atomic_update(struct drm_plane *plane, 747 struct drm_plane_state *oldstate) 748 { 749 struct ltdc_device *ldev = plane_to_ltdc(plane); 750 struct drm_plane_state *state = plane->state; 751 struct drm_framebuffer *fb = state->fb; 752 u32 lofs = plane->index * LAY_OFS; 753 u32 x0 = state->crtc_x; 754 u32 x1 = state->crtc_x + state->crtc_w - 1; 755 u32 y0 = state->crtc_y; 756 u32 y1 = state->crtc_y + state->crtc_h - 1; 757 u32 src_x, src_y, src_w, src_h; 758 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 759 enum ltdc_pix_fmt pf; 760 761 if (!state->crtc || !fb) { 762 DRM_DEBUG_DRIVER("fb or crtc NULL"); 763 return; 764 } 765 766 /* convert src_ from 16:16 format */ 767 src_x = state->src_x >> 16; 768 src_y = state->src_y >> 16; 769 src_w = state->src_w >> 16; 770 src_h = state->src_h >> 16; 771 772 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 773 plane->base.id, fb->base.id, 774 src_w, src_h, src_x, src_y, 775 state->crtc_w, state->crtc_h, 776 state->crtc_x, state->crtc_y); 777 778 bpcr = reg_read(ldev->regs, LTDC_BPCR); 779 ahbp = (bpcr & BPCR_AHBP) >> 16; 780 avbp = bpcr & BPCR_AVBP; 781 782 /* Configures the horizontal start and stop position */ 783 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 784 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 785 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 786 787 /* Configures the vertical start and stop position */ 788 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 789 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 790 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 791 792 /* Specifies the pixel format */ 793 pf = to_ltdc_pixelformat(fb->format->format); 794 for (val = 0; val < NB_PF; val++) 795 if (ldev->caps.pix_fmt_hw[val] == pf) 796 break; 797 798 if (val == NB_PF) { 799 DRM_ERROR("Pixel format %.4s not supported\n", 800 (char *)&fb->format->format); 801 val = 0; /* set by default ARGB 32 bits */ 802 } 803 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 804 805 /* Configures the color frame buffer pitch in bytes & line length */ 806 pitch_in_bytes = fb->pitches[0]; 807 line_length = fb->format->cpp[0] * 808 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 809 val = ((pitch_in_bytes << 16) | line_length); 810 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 811 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 812 813 /* Specifies the constant alpha value */ 814 val = CONSTA_MAX; 815 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 816 817 /* Specifies the blending factors */ 818 val = BF1_PAXCA | BF2_1PAXCA; 819 if (!fb->format->has_alpha) 820 val = BF1_CA | BF2_1CA; 821 822 /* Manage hw-specific capabilities */ 823 if (ldev->caps.non_alpha_only_l1 && 824 plane->type != DRM_PLANE_TYPE_PRIMARY) 825 val = BF1_PAXCA | BF2_1PAXCA; 826 827 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 828 LXBFCR_BF2 | LXBFCR_BF1, val); 829 830 /* Configures the frame buffer line number */ 831 val = y1 - y0 + 1; 832 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 833 834 /* Sets the FB address */ 835 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 836 837 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 838 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 839 840 /* Enable layer and CLUT if needed */ 841 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 842 val |= LXCR_LEN; 843 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 844 LXCR_LEN | LXCR_CLUTEN, val); 845 846 ldev->plane_fpsi[plane->index].counter++; 847 848 mutex_lock(&ldev->err_lock); 849 if (ldev->error_status & ISR_FUIF) { 850 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 851 ldev->error_status &= ~ISR_FUIF; 852 } 853 if (ldev->error_status & ISR_TERRIF) { 854 DRM_WARN("ltdc transfer error\n"); 855 ldev->error_status &= ~ISR_TERRIF; 856 } 857 mutex_unlock(&ldev->err_lock); 858 } 859 860 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 861 struct drm_plane_state *oldstate) 862 { 863 struct ltdc_device *ldev = plane_to_ltdc(plane); 864 u32 lofs = plane->index * LAY_OFS; 865 866 /* disable layer */ 867 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 868 869 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 870 oldstate->crtc->base.id, plane->base.id); 871 } 872 873 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 874 const struct drm_plane_state *state) 875 { 876 struct drm_plane *plane = state->plane; 877 struct ltdc_device *ldev = plane_to_ltdc(plane); 878 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 879 int ms_since_last; 880 ktime_t now; 881 882 now = ktime_get(); 883 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 884 885 drm_printf(p, "\tuser_updates=%dfps\n", 886 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 887 888 fpsi->last_timestamp = now; 889 fpsi->counter = 0; 890 } 891 892 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 893 u32 format, 894 u64 modifier) 895 { 896 if (modifier == DRM_FORMAT_MOD_LINEAR) 897 return true; 898 899 return false; 900 } 901 902 static const struct drm_plane_funcs ltdc_plane_funcs = { 903 .update_plane = drm_atomic_helper_update_plane, 904 .disable_plane = drm_atomic_helper_disable_plane, 905 .destroy = drm_plane_cleanup, 906 .reset = drm_atomic_helper_plane_reset, 907 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 908 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 909 .atomic_print_state = ltdc_plane_atomic_print_state, 910 .format_mod_supported = ltdc_plane_format_mod_supported, 911 }; 912 913 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 914 .prepare_fb = drm_gem_fb_prepare_fb, 915 .atomic_check = ltdc_plane_atomic_check, 916 .atomic_update = ltdc_plane_atomic_update, 917 .atomic_disable = ltdc_plane_atomic_disable, 918 }; 919 920 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 921 enum drm_plane_type type) 922 { 923 unsigned long possible_crtcs = CRTC_MASK; 924 struct ltdc_device *ldev = ddev->dev_private; 925 struct device *dev = ddev->dev; 926 struct drm_plane *plane; 927 unsigned int i, nb_fmt = 0; 928 u32 formats[NB_PF * 2]; 929 u32 drm_fmt, drm_fmt_no_alpha; 930 const u64 *modifiers = ltdc_format_modifiers; 931 int ret; 932 933 /* Get supported pixel formats */ 934 for (i = 0; i < NB_PF; i++) { 935 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 936 if (!drm_fmt) 937 continue; 938 formats[nb_fmt++] = drm_fmt; 939 940 /* Add the no-alpha related format if any & supported */ 941 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 942 if (!drm_fmt_no_alpha) 943 continue; 944 945 /* Manage hw-specific capabilities */ 946 if (ldev->caps.non_alpha_only_l1 && 947 type != DRM_PLANE_TYPE_PRIMARY) 948 continue; 949 950 formats[nb_fmt++] = drm_fmt_no_alpha; 951 } 952 953 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 954 if (!plane) 955 return NULL; 956 957 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 958 <dc_plane_funcs, formats, nb_fmt, 959 modifiers, type, NULL); 960 if (ret < 0) 961 return NULL; 962 963 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 964 965 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 966 967 return plane; 968 } 969 970 static void ltdc_plane_destroy_all(struct drm_device *ddev) 971 { 972 struct drm_plane *plane, *plane_temp; 973 974 list_for_each_entry_safe(plane, plane_temp, 975 &ddev->mode_config.plane_list, head) 976 drm_plane_cleanup(plane); 977 } 978 979 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 980 { 981 struct ltdc_device *ldev = ddev->dev_private; 982 struct drm_plane *primary, *overlay; 983 unsigned int i; 984 int ret; 985 986 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 987 if (!primary) { 988 DRM_ERROR("Can not create primary plane\n"); 989 return -EINVAL; 990 } 991 992 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 993 <dc_crtc_funcs, NULL); 994 if (ret) { 995 DRM_ERROR("Can not initialize CRTC\n"); 996 goto cleanup; 997 } 998 999 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1000 1001 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1002 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1003 1004 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1005 1006 /* Add planes. Note : the first layer is used by primary plane */ 1007 for (i = 1; i < ldev->caps.nb_layers; i++) { 1008 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 1009 if (!overlay) { 1010 ret = -ENOMEM; 1011 DRM_ERROR("Can not create overlay plane %d\n", i); 1012 goto cleanup; 1013 } 1014 } 1015 1016 return 0; 1017 1018 cleanup: 1019 ltdc_plane_destroy_all(ddev); 1020 return ret; 1021 } 1022 1023 /* 1024 * DRM_ENCODER 1025 */ 1026 1027 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 1028 .destroy = drm_encoder_cleanup, 1029 }; 1030 1031 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1032 { 1033 struct drm_device *ddev = encoder->dev; 1034 struct ltdc_device *ldev = ddev->dev_private; 1035 1036 DRM_DEBUG_DRIVER("\n"); 1037 1038 /* Disable LTDC */ 1039 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 1040 1041 /* Set to sleep state the pinctrl whatever type of encoder */ 1042 pinctrl_pm_select_sleep_state(ddev->dev); 1043 } 1044 1045 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1046 { 1047 struct drm_device *ddev = encoder->dev; 1048 struct ltdc_device *ldev = ddev->dev_private; 1049 1050 DRM_DEBUG_DRIVER("\n"); 1051 1052 /* Enable LTDC */ 1053 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 1054 } 1055 1056 static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1057 struct drm_display_mode *mode, 1058 struct drm_display_mode *adjusted_mode) 1059 { 1060 struct drm_device *ddev = encoder->dev; 1061 1062 DRM_DEBUG_DRIVER("\n"); 1063 1064 /* 1065 * Set to default state the pinctrl only with DPI type. 1066 * Others types like DSI, don't need pinctrl due to 1067 * internal bridge (the signals do not come out of the chipset). 1068 */ 1069 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1070 pinctrl_pm_select_default_state(ddev->dev); 1071 } 1072 1073 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1074 .disable = ltdc_encoder_disable, 1075 .enable = ltdc_encoder_enable, 1076 .mode_set = ltdc_encoder_mode_set, 1077 }; 1078 1079 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1080 { 1081 struct drm_encoder *encoder; 1082 int ret; 1083 1084 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1085 if (!encoder) 1086 return -ENOMEM; 1087 1088 encoder->possible_crtcs = CRTC_MASK; 1089 encoder->possible_clones = 0; /* No cloning support */ 1090 1091 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1092 DRM_MODE_ENCODER_DPI, NULL); 1093 1094 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1095 1096 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1097 if (ret) { 1098 drm_encoder_cleanup(encoder); 1099 return -EINVAL; 1100 } 1101 1102 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1103 1104 return 0; 1105 } 1106 1107 static int ltdc_get_caps(struct drm_device *ddev) 1108 { 1109 struct ltdc_device *ldev = ddev->dev_private; 1110 u32 bus_width_log2, lcr, gc2r; 1111 1112 /* 1113 * at least 1 layer must be managed & the number of layers 1114 * must not exceed LTDC_MAX_LAYER 1115 */ 1116 lcr = reg_read(ldev->regs, LTDC_LCR); 1117 1118 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1119 1120 /* set data bus width */ 1121 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1122 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1123 ldev->caps.bus_width = 8 << bus_width_log2; 1124 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1125 1126 switch (ldev->caps.hw_version) { 1127 case HWVER_10200: 1128 case HWVER_10300: 1129 ldev->caps.reg_ofs = REG_OFS_NONE; 1130 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1131 /* 1132 * Hw older versions support non-alpha color formats derived 1133 * from native alpha color formats only on the primary layer. 1134 * For instance, RG16 native format without alpha works fine 1135 * on 2nd layer but XR24 (derived color format from AR24) 1136 * does not work on 2nd layer. 1137 */ 1138 ldev->caps.non_alpha_only_l1 = true; 1139 ldev->caps.pad_max_freq_hz = 90000000; 1140 if (ldev->caps.hw_version == HWVER_10200) 1141 ldev->caps.pad_max_freq_hz = 65000000; 1142 ldev->caps.nb_irq = 2; 1143 break; 1144 case HWVER_20101: 1145 ldev->caps.reg_ofs = REG_OFS_4; 1146 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1147 ldev->caps.non_alpha_only_l1 = false; 1148 ldev->caps.pad_max_freq_hz = 150000000; 1149 ldev->caps.nb_irq = 4; 1150 break; 1151 default: 1152 return -ENODEV; 1153 } 1154 1155 return 0; 1156 } 1157 1158 void ltdc_suspend(struct drm_device *ddev) 1159 { 1160 struct ltdc_device *ldev = ddev->dev_private; 1161 1162 DRM_DEBUG_DRIVER("\n"); 1163 clk_disable_unprepare(ldev->pixel_clk); 1164 } 1165 1166 int ltdc_resume(struct drm_device *ddev) 1167 { 1168 struct ltdc_device *ldev = ddev->dev_private; 1169 int ret; 1170 1171 DRM_DEBUG_DRIVER("\n"); 1172 1173 ret = clk_prepare_enable(ldev->pixel_clk); 1174 if (ret) { 1175 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1176 return ret; 1177 } 1178 1179 return 0; 1180 } 1181 1182 int ltdc_load(struct drm_device *ddev) 1183 { 1184 struct platform_device *pdev = to_platform_device(ddev->dev); 1185 struct ltdc_device *ldev = ddev->dev_private; 1186 struct device *dev = ddev->dev; 1187 struct device_node *np = dev->of_node; 1188 struct drm_bridge *bridge; 1189 struct drm_panel *panel; 1190 struct drm_crtc *crtc; 1191 struct reset_control *rstc; 1192 struct resource *res; 1193 int irq, i, nb_endpoints; 1194 int ret = -ENODEV; 1195 1196 DRM_DEBUG_DRIVER("\n"); 1197 1198 /* Get number of endpoints */ 1199 nb_endpoints = of_graph_get_endpoint_count(np); 1200 if (!nb_endpoints) 1201 return -ENODEV; 1202 1203 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1204 if (IS_ERR(ldev->pixel_clk)) { 1205 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1206 DRM_ERROR("Unable to get lcd clock\n"); 1207 return PTR_ERR(ldev->pixel_clk); 1208 } 1209 1210 if (clk_prepare_enable(ldev->pixel_clk)) { 1211 DRM_ERROR("Unable to prepare pixel clock\n"); 1212 return -ENODEV; 1213 } 1214 1215 /* Get endpoints if any */ 1216 for (i = 0; i < nb_endpoints; i++) { 1217 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1218 1219 /* 1220 * If at least one endpoint is -ENODEV, continue probing, 1221 * else if at least one endpoint returned an error 1222 * (ie -EPROBE_DEFER) then stop probing. 1223 */ 1224 if (ret == -ENODEV) 1225 continue; 1226 else if (ret) 1227 goto err; 1228 1229 if (panel) { 1230 bridge = drm_panel_bridge_add_typed(panel, 1231 DRM_MODE_CONNECTOR_DPI); 1232 if (IS_ERR(bridge)) { 1233 DRM_ERROR("panel-bridge endpoint %d\n", i); 1234 ret = PTR_ERR(bridge); 1235 goto err; 1236 } 1237 } 1238 1239 if (bridge) { 1240 ret = ltdc_encoder_init(ddev, bridge); 1241 if (ret) { 1242 DRM_ERROR("init encoder endpoint %d\n", i); 1243 goto err; 1244 } 1245 } 1246 } 1247 1248 rstc = devm_reset_control_get_exclusive(dev, NULL); 1249 1250 mutex_init(&ldev->err_lock); 1251 1252 if (!IS_ERR(rstc)) { 1253 reset_control_assert(rstc); 1254 usleep_range(10, 20); 1255 reset_control_deassert(rstc); 1256 } 1257 1258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1259 ldev->regs = devm_ioremap_resource(dev, res); 1260 if (IS_ERR(ldev->regs)) { 1261 DRM_ERROR("Unable to get ltdc registers\n"); 1262 ret = PTR_ERR(ldev->regs); 1263 goto err; 1264 } 1265 1266 /* Disable interrupts */ 1267 reg_clear(ldev->regs, LTDC_IER, 1268 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1269 1270 ret = ltdc_get_caps(ddev); 1271 if (ret) { 1272 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1273 ldev->caps.hw_version); 1274 goto err; 1275 } 1276 1277 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1278 1279 for (i = 0; i < ldev->caps.nb_irq; i++) { 1280 irq = platform_get_irq(pdev, i); 1281 if (irq < 0) { 1282 ret = irq; 1283 goto err; 1284 } 1285 1286 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1287 ltdc_irq_thread, IRQF_ONESHOT, 1288 dev_name(dev), ddev); 1289 if (ret) { 1290 DRM_ERROR("Failed to register LTDC interrupt\n"); 1291 goto err; 1292 } 1293 1294 } 1295 1296 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1297 if (!crtc) { 1298 DRM_ERROR("Failed to allocate crtc\n"); 1299 ret = -ENOMEM; 1300 goto err; 1301 } 1302 1303 ddev->mode_config.allow_fb_modifiers = true; 1304 1305 ret = ltdc_crtc_init(ddev, crtc); 1306 if (ret) { 1307 DRM_ERROR("Failed to init crtc\n"); 1308 goto err; 1309 } 1310 1311 ret = drm_vblank_init(ddev, NB_CRTC); 1312 if (ret) { 1313 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1314 goto err; 1315 } 1316 1317 /* Allow usage of vblank without having to call drm_irq_install */ 1318 ddev->irq_enabled = 1; 1319 1320 clk_disable_unprepare(ldev->pixel_clk); 1321 1322 pinctrl_pm_select_sleep_state(ddev->dev); 1323 1324 pm_runtime_enable(ddev->dev); 1325 1326 return 0; 1327 err: 1328 for (i = 0; i < nb_endpoints; i++) 1329 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1330 1331 clk_disable_unprepare(ldev->pixel_clk); 1332 1333 return ret; 1334 } 1335 1336 void ltdc_unload(struct drm_device *ddev) 1337 { 1338 struct device *dev = ddev->dev; 1339 int nb_endpoints, i; 1340 1341 DRM_DEBUG_DRIVER("\n"); 1342 1343 nb_endpoints = of_graph_get_endpoint_count(dev->of_node); 1344 1345 for (i = 0; i < nb_endpoints; i++) 1346 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1347 1348 pm_runtime_disable(ddev->dev); 1349 } 1350 1351 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1352 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1353 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1354 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1355 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1356 MODULE_LICENSE("GPL v2"); 1357