1 /* 2 * Copyright (C) STMicroelectronics SA 2017 3 * 4 * Authors: Philippe Cornu <philippe.cornu@st.com> 5 * Yannick Fertre <yannick.fertre@st.com> 6 * Fabien Dessenne <fabien.dessenne@st.com> 7 * Mickael Reulier <mickael.reulier@st.com> 8 * 9 * License terms: GNU General Public License (GPL), version 2 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/component.h> 14 #include <linux/of_address.h> 15 #include <linux/of_graph.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_crtc_helper.h> 21 #include <drm/drm_fb_cma_helper.h> 22 #include <drm/drm_gem_cma_helper.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_plane_helper.h> 26 27 #include <video/videomode.h> 28 29 #include "ltdc.h" 30 31 #define NB_CRTC 1 32 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 33 34 #define MAX_IRQ 4 35 36 #define HWVER_10200 0x010200 37 #define HWVER_10300 0x010300 38 #define HWVER_20101 0x020101 39 40 /* 41 * The address of some registers depends on the HW version: such registers have 42 * an extra offset specified with reg_ofs. 43 */ 44 #define REG_OFS_NONE 0 45 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 46 #define REG_OFS (ldev->caps.reg_ofs) 47 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 48 49 /* Global register offsets */ 50 #define LTDC_IDR 0x0000 /* IDentification */ 51 #define LTDC_LCR 0x0004 /* Layer Count */ 52 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 53 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 54 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 55 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 56 #define LTDC_GCR 0x0018 /* Global Control */ 57 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 58 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 59 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 60 #define LTDC_GACR 0x0028 /* GAmma Correction */ 61 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 62 #define LTDC_IER 0x0034 /* Interrupt Enable */ 63 #define LTDC_ISR 0x0038 /* Interrupt Status */ 64 #define LTDC_ICR 0x003C /* Interrupt Clear */ 65 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 66 #define LTDC_CPSR 0x0044 /* Current Position Status */ 67 #define LTDC_CDSR 0x0048 /* Current Display Status */ 68 69 /* Layer register offsets */ 70 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 71 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 72 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 73 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 74 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 75 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 76 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 77 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 78 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 79 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 80 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 81 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 82 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 83 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 84 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 85 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 86 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 87 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 88 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 89 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 90 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 91 92 /* Bit definitions */ 93 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 94 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 95 96 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 97 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 98 99 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 100 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 101 102 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 103 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 104 105 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 106 #define GCR_DEN BIT(16) /* Dither ENable */ 107 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 108 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 109 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 110 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 111 112 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 113 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 114 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 115 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 116 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 117 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 118 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 119 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 120 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 121 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 122 #define GC1R_TP BIT(25) /* Timing Programmable */ 123 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 124 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 125 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 126 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 127 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 128 129 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 130 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 131 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 132 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 133 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 134 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 135 136 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 137 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 138 139 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 140 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 141 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 142 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 143 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 144 145 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 146 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 147 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 148 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 149 150 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 151 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 152 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 153 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 154 155 #define LXCR_LEN BIT(0) /* Layer ENable */ 156 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 157 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 158 159 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 160 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 161 162 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 163 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 164 165 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 166 167 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 168 169 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 170 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 171 172 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 173 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 174 175 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 176 177 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 178 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 179 #define BF1_CA 0x400 /* Constant Alpha */ 180 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 181 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 182 183 #define NB_PF 8 /* Max nb of HW pixel format */ 184 185 enum ltdc_pix_fmt { 186 PF_NONE, 187 /* RGB formats */ 188 PF_ARGB8888, /* ARGB [32 bits] */ 189 PF_RGBA8888, /* RGBA [32 bits] */ 190 PF_RGB888, /* RGB [24 bits] */ 191 PF_RGB565, /* RGB [16 bits] */ 192 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 193 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 194 /* Indexed formats */ 195 PF_L8, /* Indexed 8 bits [8 bits] */ 196 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 197 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 198 }; 199 200 /* The index gives the encoding of the pixel format for an HW version */ 201 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 202 PF_ARGB8888, /* 0x00 */ 203 PF_RGB888, /* 0x01 */ 204 PF_RGB565, /* 0x02 */ 205 PF_ARGB1555, /* 0x03 */ 206 PF_ARGB4444, /* 0x04 */ 207 PF_L8, /* 0x05 */ 208 PF_AL44, /* 0x06 */ 209 PF_AL88 /* 0x07 */ 210 }; 211 212 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 213 PF_ARGB8888, /* 0x00 */ 214 PF_RGB888, /* 0x01 */ 215 PF_RGB565, /* 0x02 */ 216 PF_RGBA8888, /* 0x03 */ 217 PF_AL44, /* 0x04 */ 218 PF_L8, /* 0x05 */ 219 PF_ARGB1555, /* 0x06 */ 220 PF_ARGB4444 /* 0x07 */ 221 }; 222 223 static inline u32 reg_read(void __iomem *base, u32 reg) 224 { 225 return readl_relaxed(base + reg); 226 } 227 228 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 229 { 230 writel_relaxed(val, base + reg); 231 } 232 233 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 234 { 235 reg_write(base, reg, reg_read(base, reg) | mask); 236 } 237 238 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 239 { 240 reg_write(base, reg, reg_read(base, reg) & ~mask); 241 } 242 243 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 244 u32 val) 245 { 246 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 247 } 248 249 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 250 { 251 return (struct ltdc_device *)crtc->dev->dev_private; 252 } 253 254 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 255 { 256 return (struct ltdc_device *)plane->dev->dev_private; 257 } 258 259 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 260 { 261 return (struct ltdc_device *)enc->dev->dev_private; 262 } 263 264 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 265 { 266 enum ltdc_pix_fmt pf; 267 268 switch (drm_fmt) { 269 case DRM_FORMAT_ARGB8888: 270 case DRM_FORMAT_XRGB8888: 271 pf = PF_ARGB8888; 272 break; 273 case DRM_FORMAT_RGBA8888: 274 case DRM_FORMAT_RGBX8888: 275 pf = PF_RGBA8888; 276 break; 277 case DRM_FORMAT_RGB888: 278 pf = PF_RGB888; 279 break; 280 case DRM_FORMAT_RGB565: 281 pf = PF_RGB565; 282 break; 283 case DRM_FORMAT_ARGB1555: 284 case DRM_FORMAT_XRGB1555: 285 pf = PF_ARGB1555; 286 break; 287 case DRM_FORMAT_ARGB4444: 288 case DRM_FORMAT_XRGB4444: 289 pf = PF_ARGB4444; 290 break; 291 case DRM_FORMAT_C8: 292 pf = PF_L8; 293 break; 294 default: 295 pf = PF_NONE; 296 break; 297 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 298 } 299 300 return pf; 301 } 302 303 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 304 { 305 switch (pf) { 306 case PF_ARGB8888: 307 return DRM_FORMAT_ARGB8888; 308 case PF_RGBA8888: 309 return DRM_FORMAT_RGBA8888; 310 case PF_RGB888: 311 return DRM_FORMAT_RGB888; 312 case PF_RGB565: 313 return DRM_FORMAT_RGB565; 314 case PF_ARGB1555: 315 return DRM_FORMAT_ARGB1555; 316 case PF_ARGB4444: 317 return DRM_FORMAT_ARGB4444; 318 case PF_L8: 319 return DRM_FORMAT_C8; 320 case PF_AL44: /* No DRM support */ 321 case PF_AL88: /* No DRM support */ 322 case PF_NONE: 323 default: 324 return 0; 325 } 326 } 327 328 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 329 { 330 struct drm_device *ddev = arg; 331 struct ltdc_device *ldev = ddev->dev_private; 332 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 333 334 /* Line IRQ : trigger the vblank event */ 335 if (ldev->irq_status & ISR_LIF) 336 drm_crtc_handle_vblank(crtc); 337 338 /* Save FIFO Underrun & Transfer Error status */ 339 mutex_lock(&ldev->err_lock); 340 if (ldev->irq_status & ISR_FUIF) 341 ldev->error_status |= ISR_FUIF; 342 if (ldev->irq_status & ISR_TERRIF) 343 ldev->error_status |= ISR_TERRIF; 344 mutex_unlock(&ldev->err_lock); 345 346 return IRQ_HANDLED; 347 } 348 349 static irqreturn_t ltdc_irq(int irq, void *arg) 350 { 351 struct drm_device *ddev = arg; 352 struct ltdc_device *ldev = ddev->dev_private; 353 354 /* Read & Clear the interrupt status */ 355 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 356 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 357 358 return IRQ_WAKE_THREAD; 359 } 360 361 /* 362 * DRM_CRTC 363 */ 364 365 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 366 struct drm_crtc_state *old_state) 367 { 368 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 369 370 DRM_DEBUG_DRIVER("\n"); 371 372 /* Sets the background color value */ 373 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 374 375 /* Enable IRQ */ 376 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 377 378 /* Immediately commit the planes */ 379 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 380 381 /* Enable LTDC */ 382 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 383 384 drm_crtc_vblank_on(crtc); 385 } 386 387 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 388 struct drm_crtc_state *old_state) 389 { 390 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 391 392 DRM_DEBUG_DRIVER("\n"); 393 394 drm_crtc_vblank_off(crtc); 395 396 /* disable LTDC */ 397 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 398 399 /* disable IRQ */ 400 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 401 402 /* immediately commit disable of layers before switching off LTDC */ 403 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 404 } 405 406 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 407 { 408 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 409 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 410 struct videomode vm; 411 int rate = mode->clock * 1000; 412 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 413 u32 total_width, total_height; 414 u32 val; 415 416 drm_display_mode_to_videomode(mode, &vm); 417 418 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 419 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 420 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 421 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 422 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 423 424 /* Convert video timings to ltdc timings */ 425 hsync = vm.hsync_len - 1; 426 vsync = vm.vsync_len - 1; 427 accum_hbp = hsync + vm.hback_porch; 428 accum_vbp = vsync + vm.vback_porch; 429 accum_act_w = accum_hbp + vm.hactive; 430 accum_act_h = accum_vbp + vm.vactive; 431 total_width = accum_act_w + vm.hfront_porch; 432 total_height = accum_act_h + vm.vfront_porch; 433 434 clk_disable(ldev->pixel_clk); 435 436 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 437 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 438 return; 439 } 440 441 clk_enable(ldev->pixel_clk); 442 443 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 444 val = 0; 445 446 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 447 val |= GCR_HSPOL; 448 449 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 450 val |= GCR_VSPOL; 451 452 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 453 val |= GCR_DEPOL; 454 455 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 456 val |= GCR_PCPOL; 457 458 reg_update_bits(ldev->regs, LTDC_GCR, 459 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 460 461 /* Set Synchronization size */ 462 val = (hsync << 16) | vsync; 463 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 464 465 /* Set Accumulated Back porch */ 466 val = (accum_hbp << 16) | accum_vbp; 467 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 468 469 /* Set Accumulated Active Width */ 470 val = (accum_act_w << 16) | accum_act_h; 471 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 472 473 /* Set total width & height */ 474 val = (total_width << 16) | total_height; 475 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 476 477 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 478 } 479 480 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 481 struct drm_crtc_state *old_crtc_state) 482 { 483 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 484 struct drm_pending_vblank_event *event = crtc->state->event; 485 486 DRM_DEBUG_ATOMIC("\n"); 487 488 /* Commit shadow registers = update planes at next vblank */ 489 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 490 491 if (event) { 492 crtc->state->event = NULL; 493 494 spin_lock_irq(&crtc->dev->event_lock); 495 if (drm_crtc_vblank_get(crtc) == 0) 496 drm_crtc_arm_vblank_event(crtc, event); 497 else 498 drm_crtc_send_vblank_event(crtc, event); 499 spin_unlock_irq(&crtc->dev->event_lock); 500 } 501 } 502 503 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 504 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 505 .atomic_flush = ltdc_crtc_atomic_flush, 506 .atomic_enable = ltdc_crtc_atomic_enable, 507 .atomic_disable = ltdc_crtc_atomic_disable, 508 }; 509 510 int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe) 511 { 512 struct ltdc_device *ldev = ddev->dev_private; 513 514 DRM_DEBUG_DRIVER("\n"); 515 reg_set(ldev->regs, LTDC_IER, IER_LIE); 516 517 return 0; 518 } 519 520 void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe) 521 { 522 struct ltdc_device *ldev = ddev->dev_private; 523 524 DRM_DEBUG_DRIVER("\n"); 525 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 526 } 527 528 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 529 .destroy = drm_crtc_cleanup, 530 .set_config = drm_atomic_helper_set_config, 531 .page_flip = drm_atomic_helper_page_flip, 532 .reset = drm_atomic_helper_crtc_reset, 533 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 534 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 535 }; 536 537 /* 538 * DRM_PLANE 539 */ 540 541 static int ltdc_plane_atomic_check(struct drm_plane *plane, 542 struct drm_plane_state *state) 543 { 544 struct drm_framebuffer *fb = state->fb; 545 u32 src_x, src_y, src_w, src_h; 546 547 DRM_DEBUG_DRIVER("\n"); 548 549 if (!fb) 550 return 0; 551 552 /* convert src_ from 16:16 format */ 553 src_x = state->src_x >> 16; 554 src_y = state->src_y >> 16; 555 src_w = state->src_w >> 16; 556 src_h = state->src_h >> 16; 557 558 /* Reject scaling */ 559 if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) { 560 DRM_ERROR("Scaling is not supported"); 561 return -EINVAL; 562 } 563 564 return 0; 565 } 566 567 static void ltdc_plane_atomic_update(struct drm_plane *plane, 568 struct drm_plane_state *oldstate) 569 { 570 struct ltdc_device *ldev = plane_to_ltdc(plane); 571 struct drm_plane_state *state = plane->state; 572 struct drm_framebuffer *fb = state->fb; 573 u32 lofs = plane->index * LAY_OFS; 574 u32 x0 = state->crtc_x; 575 u32 x1 = state->crtc_x + state->crtc_w - 1; 576 u32 y0 = state->crtc_y; 577 u32 y1 = state->crtc_y + state->crtc_h - 1; 578 u32 src_x, src_y, src_w, src_h; 579 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 580 enum ltdc_pix_fmt pf; 581 582 if (!state->crtc || !fb) { 583 DRM_DEBUG_DRIVER("fb or crtc NULL"); 584 return; 585 } 586 587 /* convert src_ from 16:16 format */ 588 src_x = state->src_x >> 16; 589 src_y = state->src_y >> 16; 590 src_w = state->src_w >> 16; 591 src_h = state->src_h >> 16; 592 593 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 594 plane->base.id, fb->base.id, 595 src_w, src_h, src_x, src_y, 596 state->crtc_w, state->crtc_h, 597 state->crtc_x, state->crtc_y); 598 599 bpcr = reg_read(ldev->regs, LTDC_BPCR); 600 ahbp = (bpcr & BPCR_AHBP) >> 16; 601 avbp = bpcr & BPCR_AVBP; 602 603 /* Configures the horizontal start and stop position */ 604 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 605 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 606 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 607 608 /* Configures the vertical start and stop position */ 609 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 610 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 611 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 612 613 /* Specifies the pixel format */ 614 pf = to_ltdc_pixelformat(fb->format->format); 615 for (val = 0; val < NB_PF; val++) 616 if (ldev->caps.pix_fmt_hw[val] == pf) 617 break; 618 619 if (val == NB_PF) { 620 DRM_ERROR("Pixel format %.4s not supported\n", 621 (char *)&fb->format->format); 622 val = 0; /* set by default ARGB 32 bits */ 623 } 624 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 625 626 /* Configures the color frame buffer pitch in bytes & line length */ 627 pitch_in_bytes = fb->pitches[0]; 628 line_length = drm_format_plane_cpp(fb->format->format, 0) * 629 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 630 val = ((pitch_in_bytes << 16) | line_length); 631 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 632 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 633 634 /* Specifies the constant alpha value */ 635 val = CONSTA_MAX; 636 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 637 638 /* Specifies the blending factors */ 639 val = BF1_PAXCA | BF2_1PAXCA; 640 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 641 LXBFCR_BF2 | LXBFCR_BF1, val); 642 643 /* Configures the frame buffer line number */ 644 val = y1 - y0 + 1; 645 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 646 647 /* Sets the FB address */ 648 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 649 650 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 651 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 652 653 /* Enable layer and CLUT if needed */ 654 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 655 val |= LXCR_LEN; 656 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 657 LXCR_LEN | LXCR_CLUTEN, val); 658 659 mutex_lock(&ldev->err_lock); 660 if (ldev->error_status & ISR_FUIF) { 661 DRM_DEBUG_DRIVER("Fifo underrun\n"); 662 ldev->error_status &= ~ISR_FUIF; 663 } 664 if (ldev->error_status & ISR_TERRIF) { 665 DRM_DEBUG_DRIVER("Transfer error\n"); 666 ldev->error_status &= ~ISR_TERRIF; 667 } 668 mutex_unlock(&ldev->err_lock); 669 } 670 671 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 672 struct drm_plane_state *oldstate) 673 { 674 struct ltdc_device *ldev = plane_to_ltdc(plane); 675 u32 lofs = plane->index * LAY_OFS; 676 677 /* disable layer */ 678 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 679 680 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 681 oldstate->crtc->base.id, plane->base.id); 682 } 683 684 static const struct drm_plane_funcs ltdc_plane_funcs = { 685 .update_plane = drm_atomic_helper_update_plane, 686 .disable_plane = drm_atomic_helper_disable_plane, 687 .destroy = drm_plane_cleanup, 688 .reset = drm_atomic_helper_plane_reset, 689 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 690 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 691 }; 692 693 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 694 .atomic_check = ltdc_plane_atomic_check, 695 .atomic_update = ltdc_plane_atomic_update, 696 .atomic_disable = ltdc_plane_atomic_disable, 697 }; 698 699 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 700 enum drm_plane_type type) 701 { 702 unsigned long possible_crtcs = CRTC_MASK; 703 struct ltdc_device *ldev = ddev->dev_private; 704 struct device *dev = ddev->dev; 705 struct drm_plane *plane; 706 unsigned int i, nb_fmt = 0; 707 u32 formats[NB_PF]; 708 u32 drm_fmt; 709 int ret; 710 711 /* Get supported pixel formats */ 712 for (i = 0; i < NB_PF; i++) { 713 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 714 if (!drm_fmt) 715 continue; 716 formats[nb_fmt++] = drm_fmt; 717 } 718 719 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 720 if (!plane) 721 return 0; 722 723 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 724 <dc_plane_funcs, formats, nb_fmt, 725 NULL, type, NULL); 726 if (ret < 0) 727 return 0; 728 729 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 730 731 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 732 733 return plane; 734 } 735 736 static void ltdc_plane_destroy_all(struct drm_device *ddev) 737 { 738 struct drm_plane *plane, *plane_temp; 739 740 list_for_each_entry_safe(plane, plane_temp, 741 &ddev->mode_config.plane_list, head) 742 drm_plane_cleanup(plane); 743 } 744 745 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 746 { 747 struct ltdc_device *ldev = ddev->dev_private; 748 struct drm_plane *primary, *overlay; 749 unsigned int i; 750 int ret; 751 752 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 753 if (!primary) { 754 DRM_ERROR("Can not create primary plane\n"); 755 return -EINVAL; 756 } 757 758 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 759 <dc_crtc_funcs, NULL); 760 if (ret) { 761 DRM_ERROR("Can not initialize CRTC\n"); 762 goto cleanup; 763 } 764 765 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 766 767 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 768 769 /* Add planes. Note : the first layer is used by primary plane */ 770 for (i = 1; i < ldev->caps.nb_layers; i++) { 771 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 772 if (!overlay) { 773 ret = -ENOMEM; 774 DRM_ERROR("Can not create overlay plane %d\n", i); 775 goto cleanup; 776 } 777 } 778 779 return 0; 780 781 cleanup: 782 ltdc_plane_destroy_all(ddev); 783 return ret; 784 } 785 786 /* 787 * DRM_ENCODER 788 */ 789 790 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 791 .destroy = drm_encoder_cleanup, 792 }; 793 794 static int ltdc_encoder_init(struct drm_device *ddev) 795 { 796 struct ltdc_device *ldev = ddev->dev_private; 797 struct drm_encoder *encoder; 798 int ret; 799 800 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 801 if (!encoder) 802 return -ENOMEM; 803 804 encoder->possible_crtcs = CRTC_MASK; 805 encoder->possible_clones = 0; /* No cloning support */ 806 807 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 808 DRM_MODE_ENCODER_DPI, NULL); 809 810 ret = drm_bridge_attach(encoder, ldev->bridge, NULL); 811 if (ret) { 812 drm_encoder_cleanup(encoder); 813 return -EINVAL; 814 } 815 816 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 817 818 return 0; 819 } 820 821 static int ltdc_get_caps(struct drm_device *ddev) 822 { 823 struct ltdc_device *ldev = ddev->dev_private; 824 u32 bus_width_log2, lcr, gc2r; 825 826 /* at least 1 layer must be managed */ 827 lcr = reg_read(ldev->regs, LTDC_LCR); 828 829 ldev->caps.nb_layers = max_t(int, lcr, 1); 830 831 /* set data bus width */ 832 gc2r = reg_read(ldev->regs, LTDC_GC2R); 833 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 834 ldev->caps.bus_width = 8 << bus_width_log2; 835 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 836 837 switch (ldev->caps.hw_version) { 838 case HWVER_10200: 839 case HWVER_10300: 840 ldev->caps.reg_ofs = REG_OFS_NONE; 841 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 842 break; 843 case HWVER_20101: 844 ldev->caps.reg_ofs = REG_OFS_4; 845 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 846 break; 847 default: 848 return -ENODEV; 849 } 850 851 return 0; 852 } 853 854 int ltdc_load(struct drm_device *ddev) 855 { 856 struct platform_device *pdev = to_platform_device(ddev->dev); 857 struct ltdc_device *ldev = ddev->dev_private; 858 struct device *dev = ddev->dev; 859 struct device_node *np = dev->of_node; 860 struct drm_bridge *bridge; 861 struct drm_panel *panel; 862 struct drm_crtc *crtc; 863 struct reset_control *rstc; 864 struct resource *res; 865 int irq, ret, i; 866 867 DRM_DEBUG_DRIVER("\n"); 868 869 ret = drm_of_find_panel_or_bridge(np, 0, 0, &panel, &bridge); 870 if (ret) 871 return ret; 872 873 rstc = devm_reset_control_get_exclusive(dev, NULL); 874 875 mutex_init(&ldev->err_lock); 876 877 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 878 if (IS_ERR(ldev->pixel_clk)) { 879 DRM_ERROR("Unable to get lcd clock\n"); 880 return -ENODEV; 881 } 882 883 if (clk_prepare_enable(ldev->pixel_clk)) { 884 DRM_ERROR("Unable to prepare pixel clock\n"); 885 return -ENODEV; 886 } 887 888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 889 if (!res) { 890 DRM_ERROR("Unable to get resource\n"); 891 ret = -ENODEV; 892 goto err; 893 } 894 895 ldev->regs = devm_ioremap_resource(dev, res); 896 if (IS_ERR(ldev->regs)) { 897 DRM_ERROR("Unable to get ltdc registers\n"); 898 ret = PTR_ERR(ldev->regs); 899 goto err; 900 } 901 902 for (i = 0; i < MAX_IRQ; i++) { 903 irq = platform_get_irq(pdev, i); 904 if (irq < 0) 905 continue; 906 907 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 908 ltdc_irq_thread, IRQF_ONESHOT, 909 dev_name(dev), ddev); 910 if (ret) { 911 DRM_ERROR("Failed to register LTDC interrupt\n"); 912 goto err; 913 } 914 } 915 916 if (!IS_ERR(rstc)) 917 reset_control_deassert(rstc); 918 919 /* Disable interrupts */ 920 reg_clear(ldev->regs, LTDC_IER, 921 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 922 923 ret = ltdc_get_caps(ddev); 924 if (ret) { 925 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 926 ldev->caps.hw_version); 927 goto err; 928 } 929 930 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 931 932 if (panel) { 933 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI); 934 if (IS_ERR(bridge)) { 935 DRM_ERROR("Failed to create panel-bridge\n"); 936 ret = PTR_ERR(bridge); 937 goto err; 938 } 939 ldev->is_panel_bridge = true; 940 } 941 942 ldev->bridge = bridge; 943 944 ret = ltdc_encoder_init(ddev); 945 if (ret) { 946 DRM_ERROR("Failed to init encoder\n"); 947 goto err; 948 } 949 950 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 951 if (!crtc) { 952 DRM_ERROR("Failed to allocate crtc\n"); 953 ret = -ENOMEM; 954 goto err; 955 } 956 957 ret = ltdc_crtc_init(ddev, crtc); 958 if (ret) { 959 DRM_ERROR("Failed to init crtc\n"); 960 goto err; 961 } 962 963 ret = drm_vblank_init(ddev, NB_CRTC); 964 if (ret) { 965 DRM_ERROR("Failed calling drm_vblank_init()\n"); 966 goto err; 967 } 968 969 /* Allow usage of vblank without having to call drm_irq_install */ 970 ddev->irq_enabled = 1; 971 972 return 0; 973 974 err: 975 if (ldev->is_panel_bridge) 976 drm_panel_bridge_remove(bridge); 977 978 clk_disable_unprepare(ldev->pixel_clk); 979 980 return ret; 981 } 982 983 void ltdc_unload(struct drm_device *ddev) 984 { 985 struct ltdc_device *ldev = ddev->dev_private; 986 987 DRM_DEBUG_DRIVER("\n"); 988 989 if (ldev->is_panel_bridge) 990 drm_panel_bridge_remove(ldev->bridge); 991 992 clk_disable_unprepare(ldev->pixel_clk); 993 } 994 995 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 996 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 997 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 998 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 999 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1000 MODULE_LICENSE("GPL v2"); 1001