1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_device.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_gem_cma_helper.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_plane_helper.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/drm_vblank.h> 35 36 #include <video/videomode.h> 37 38 #include "ltdc.h" 39 40 #define NB_CRTC 1 41 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 42 43 #define MAX_IRQ 4 44 45 #define HWVER_10200 0x010200 46 #define HWVER_10300 0x010300 47 #define HWVER_20101 0x020101 48 49 /* 50 * The address of some registers depends on the HW version: such registers have 51 * an extra offset specified with reg_ofs. 52 */ 53 #define REG_OFS_NONE 0 54 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 55 #define REG_OFS (ldev->caps.reg_ofs) 56 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 57 58 /* Global register offsets */ 59 #define LTDC_IDR 0x0000 /* IDentification */ 60 #define LTDC_LCR 0x0004 /* Layer Count */ 61 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 62 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 63 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 64 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 65 #define LTDC_GCR 0x0018 /* Global Control */ 66 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 67 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 68 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 69 #define LTDC_GACR 0x0028 /* GAmma Correction */ 70 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 71 #define LTDC_IER 0x0034 /* Interrupt Enable */ 72 #define LTDC_ISR 0x0038 /* Interrupt Status */ 73 #define LTDC_ICR 0x003C /* Interrupt Clear */ 74 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 75 #define LTDC_CPSR 0x0044 /* Current Position Status */ 76 #define LTDC_CDSR 0x0048 /* Current Display Status */ 77 78 /* Layer register offsets */ 79 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 80 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 81 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 82 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 83 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 84 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 85 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 86 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 87 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 88 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 89 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 90 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 91 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 92 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 93 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 94 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 95 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 96 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 97 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 98 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 99 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 100 101 /* Bit definitions */ 102 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 103 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 104 105 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 106 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 107 108 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 109 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 110 111 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 112 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 113 114 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 115 #define GCR_DEN BIT(16) /* Dither ENable */ 116 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 117 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 118 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 119 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 120 121 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 122 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 123 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 124 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 125 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 126 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 127 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 128 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 129 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 130 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 131 #define GC1R_TP BIT(25) /* Timing Programmable */ 132 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 133 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 134 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 135 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 136 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 137 138 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 139 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 140 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 141 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 142 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 143 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 144 145 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 146 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 147 148 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 149 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 150 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 151 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 152 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 153 154 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 155 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 156 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 157 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 158 159 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 160 161 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 162 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 163 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 164 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 165 166 #define LXCR_LEN BIT(0) /* Layer ENable */ 167 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 168 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 169 170 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 171 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 172 173 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 174 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 175 176 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 177 178 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 179 180 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 181 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 182 183 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 184 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 185 186 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 187 188 #define CLUT_SIZE 256 189 190 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 191 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 192 #define BF1_CA 0x400 /* Constant Alpha */ 193 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 194 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 195 196 #define NB_PF 8 /* Max nb of HW pixel format */ 197 198 enum ltdc_pix_fmt { 199 PF_NONE, 200 /* RGB formats */ 201 PF_ARGB8888, /* ARGB [32 bits] */ 202 PF_RGBA8888, /* RGBA [32 bits] */ 203 PF_RGB888, /* RGB [24 bits] */ 204 PF_RGB565, /* RGB [16 bits] */ 205 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 206 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 207 /* Indexed formats */ 208 PF_L8, /* Indexed 8 bits [8 bits] */ 209 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 210 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 211 }; 212 213 /* The index gives the encoding of the pixel format for an HW version */ 214 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 215 PF_ARGB8888, /* 0x00 */ 216 PF_RGB888, /* 0x01 */ 217 PF_RGB565, /* 0x02 */ 218 PF_ARGB1555, /* 0x03 */ 219 PF_ARGB4444, /* 0x04 */ 220 PF_L8, /* 0x05 */ 221 PF_AL44, /* 0x06 */ 222 PF_AL88 /* 0x07 */ 223 }; 224 225 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 226 PF_ARGB8888, /* 0x00 */ 227 PF_RGB888, /* 0x01 */ 228 PF_RGB565, /* 0x02 */ 229 PF_RGBA8888, /* 0x03 */ 230 PF_AL44, /* 0x04 */ 231 PF_L8, /* 0x05 */ 232 PF_ARGB1555, /* 0x06 */ 233 PF_ARGB4444 /* 0x07 */ 234 }; 235 236 static const u64 ltdc_format_modifiers[] = { 237 DRM_FORMAT_MOD_LINEAR, 238 DRM_FORMAT_MOD_INVALID 239 }; 240 241 static inline u32 reg_read(void __iomem *base, u32 reg) 242 { 243 return readl_relaxed(base + reg); 244 } 245 246 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 247 { 248 writel_relaxed(val, base + reg); 249 } 250 251 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 252 { 253 reg_write(base, reg, reg_read(base, reg) | mask); 254 } 255 256 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 257 { 258 reg_write(base, reg, reg_read(base, reg) & ~mask); 259 } 260 261 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 262 u32 val) 263 { 264 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 265 } 266 267 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 268 { 269 return (struct ltdc_device *)crtc->dev->dev_private; 270 } 271 272 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 273 { 274 return (struct ltdc_device *)plane->dev->dev_private; 275 } 276 277 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 278 { 279 return (struct ltdc_device *)enc->dev->dev_private; 280 } 281 282 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 283 { 284 enum ltdc_pix_fmt pf; 285 286 switch (drm_fmt) { 287 case DRM_FORMAT_ARGB8888: 288 case DRM_FORMAT_XRGB8888: 289 pf = PF_ARGB8888; 290 break; 291 case DRM_FORMAT_RGBA8888: 292 case DRM_FORMAT_RGBX8888: 293 pf = PF_RGBA8888; 294 break; 295 case DRM_FORMAT_RGB888: 296 pf = PF_RGB888; 297 break; 298 case DRM_FORMAT_RGB565: 299 pf = PF_RGB565; 300 break; 301 case DRM_FORMAT_ARGB1555: 302 case DRM_FORMAT_XRGB1555: 303 pf = PF_ARGB1555; 304 break; 305 case DRM_FORMAT_ARGB4444: 306 case DRM_FORMAT_XRGB4444: 307 pf = PF_ARGB4444; 308 break; 309 case DRM_FORMAT_C8: 310 pf = PF_L8; 311 break; 312 default: 313 pf = PF_NONE; 314 break; 315 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 316 } 317 318 return pf; 319 } 320 321 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 322 { 323 switch (pf) { 324 case PF_ARGB8888: 325 return DRM_FORMAT_ARGB8888; 326 case PF_RGBA8888: 327 return DRM_FORMAT_RGBA8888; 328 case PF_RGB888: 329 return DRM_FORMAT_RGB888; 330 case PF_RGB565: 331 return DRM_FORMAT_RGB565; 332 case PF_ARGB1555: 333 return DRM_FORMAT_ARGB1555; 334 case PF_ARGB4444: 335 return DRM_FORMAT_ARGB4444; 336 case PF_L8: 337 return DRM_FORMAT_C8; 338 case PF_AL44: /* No DRM support */ 339 case PF_AL88: /* No DRM support */ 340 case PF_NONE: 341 default: 342 return 0; 343 } 344 } 345 346 static inline u32 get_pixelformat_without_alpha(u32 drm) 347 { 348 switch (drm) { 349 case DRM_FORMAT_ARGB4444: 350 return DRM_FORMAT_XRGB4444; 351 case DRM_FORMAT_RGBA4444: 352 return DRM_FORMAT_RGBX4444; 353 case DRM_FORMAT_ARGB1555: 354 return DRM_FORMAT_XRGB1555; 355 case DRM_FORMAT_RGBA5551: 356 return DRM_FORMAT_RGBX5551; 357 case DRM_FORMAT_ARGB8888: 358 return DRM_FORMAT_XRGB8888; 359 case DRM_FORMAT_RGBA8888: 360 return DRM_FORMAT_RGBX8888; 361 default: 362 return 0; 363 } 364 } 365 366 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 367 { 368 struct drm_device *ddev = arg; 369 struct ltdc_device *ldev = ddev->dev_private; 370 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 371 372 /* Line IRQ : trigger the vblank event */ 373 if (ldev->irq_status & ISR_LIF) 374 drm_crtc_handle_vblank(crtc); 375 376 /* Save FIFO Underrun & Transfer Error status */ 377 mutex_lock(&ldev->err_lock); 378 if (ldev->irq_status & ISR_FUIF) 379 ldev->error_status |= ISR_FUIF; 380 if (ldev->irq_status & ISR_TERRIF) 381 ldev->error_status |= ISR_TERRIF; 382 mutex_unlock(&ldev->err_lock); 383 384 return IRQ_HANDLED; 385 } 386 387 static irqreturn_t ltdc_irq(int irq, void *arg) 388 { 389 struct drm_device *ddev = arg; 390 struct ltdc_device *ldev = ddev->dev_private; 391 392 /* Read & Clear the interrupt status */ 393 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 394 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 395 396 return IRQ_WAKE_THREAD; 397 } 398 399 /* 400 * DRM_CRTC 401 */ 402 403 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 404 { 405 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 406 struct drm_color_lut *lut; 407 u32 val; 408 int i; 409 410 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 411 return; 412 413 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 414 415 for (i = 0; i < CLUT_SIZE; i++, lut++) { 416 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 417 (lut->blue >> 8) | (i << 24); 418 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 419 } 420 } 421 422 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 423 struct drm_crtc_state *old_state) 424 { 425 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 426 427 DRM_DEBUG_DRIVER("\n"); 428 429 /* Sets the background color value */ 430 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 431 432 /* Enable IRQ */ 433 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 434 435 /* Commit shadow registers = update planes at next vblank */ 436 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 437 438 drm_crtc_vblank_on(crtc); 439 } 440 441 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 442 struct drm_crtc_state *old_state) 443 { 444 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 445 struct drm_device *ddev = crtc->dev; 446 447 DRM_DEBUG_DRIVER("\n"); 448 449 drm_crtc_vblank_off(crtc); 450 451 /* disable IRQ */ 452 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 453 454 /* immediately commit disable of layers before switching off LTDC */ 455 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 456 457 pm_runtime_put_sync(ddev->dev); 458 } 459 460 #define CLK_TOLERANCE_HZ 50 461 462 static enum drm_mode_status 463 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 464 const struct drm_display_mode *mode) 465 { 466 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 467 int target = mode->clock * 1000; 468 int target_min = target - CLK_TOLERANCE_HZ; 469 int target_max = target + CLK_TOLERANCE_HZ; 470 int result; 471 472 result = clk_round_rate(ldev->pixel_clk, target); 473 474 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 475 476 /* Filter modes according to the max frequency supported by the pads */ 477 if (result > ldev->caps.pad_max_freq_hz) 478 return MODE_CLOCK_HIGH; 479 480 /* 481 * Accept all "preferred" modes: 482 * - this is important for panels because panel clock tolerances are 483 * bigger than hdmi ones and there is no reason to not accept them 484 * (the fps may vary a little but it is not a problem). 485 * - the hdmi preferred mode will be accepted too, but userland will 486 * be able to use others hdmi "valid" modes if necessary. 487 */ 488 if (mode->type & DRM_MODE_TYPE_PREFERRED) 489 return MODE_OK; 490 491 /* 492 * Filter modes according to the clock value, particularly useful for 493 * hdmi modes that require precise pixel clocks. 494 */ 495 if (result < target_min || result > target_max) 496 return MODE_CLOCK_RANGE; 497 498 return MODE_OK; 499 } 500 501 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 502 const struct drm_display_mode *mode, 503 struct drm_display_mode *adjusted_mode) 504 { 505 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 506 struct drm_device *ddev = crtc->dev; 507 int rate = mode->clock * 1000; 508 bool runtime_active; 509 int ret; 510 511 runtime_active = pm_runtime_active(ddev->dev); 512 513 if (runtime_active) 514 pm_runtime_put_sync(ddev->dev); 515 516 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 517 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 518 return false; 519 } 520 521 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 522 523 if (runtime_active) { 524 ret = pm_runtime_get_sync(ddev->dev); 525 if (ret) { 526 DRM_ERROR("Failed to fixup mode, cannot get sync\n"); 527 return false; 528 } 529 } 530 531 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 532 mode->clock, adjusted_mode->clock); 533 534 return true; 535 } 536 537 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 538 { 539 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 540 struct drm_device *ddev = crtc->dev; 541 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 542 struct videomode vm; 543 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 544 u32 total_width, total_height; 545 u32 val; 546 int ret; 547 548 if (!pm_runtime_active(ddev->dev)) { 549 ret = pm_runtime_get_sync(ddev->dev); 550 if (ret) { 551 DRM_ERROR("Failed to set mode, cannot get sync\n"); 552 return; 553 } 554 } 555 556 drm_display_mode_to_videomode(mode, &vm); 557 558 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 559 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 560 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 561 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 562 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 563 564 /* Convert video timings to ltdc timings */ 565 hsync = vm.hsync_len - 1; 566 vsync = vm.vsync_len - 1; 567 accum_hbp = hsync + vm.hback_porch; 568 accum_vbp = vsync + vm.vback_porch; 569 accum_act_w = accum_hbp + vm.hactive; 570 accum_act_h = accum_vbp + vm.vactive; 571 total_width = accum_act_w + vm.hfront_porch; 572 total_height = accum_act_h + vm.vfront_porch; 573 574 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 575 val = 0; 576 577 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 578 val |= GCR_HSPOL; 579 580 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 581 val |= GCR_VSPOL; 582 583 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 584 val |= GCR_DEPOL; 585 586 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 587 val |= GCR_PCPOL; 588 589 reg_update_bits(ldev->regs, LTDC_GCR, 590 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 591 592 /* Set Synchronization size */ 593 val = (hsync << 16) | vsync; 594 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 595 596 /* Set Accumulated Back porch */ 597 val = (accum_hbp << 16) | accum_vbp; 598 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 599 600 /* Set Accumulated Active Width */ 601 val = (accum_act_w << 16) | accum_act_h; 602 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 603 604 /* Set total width & height */ 605 val = (total_width << 16) | total_height; 606 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 607 608 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 609 } 610 611 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 612 struct drm_crtc_state *old_crtc_state) 613 { 614 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 615 struct drm_device *ddev = crtc->dev; 616 struct drm_pending_vblank_event *event = crtc->state->event; 617 618 DRM_DEBUG_ATOMIC("\n"); 619 620 ltdc_crtc_update_clut(crtc); 621 622 /* Commit shadow registers = update planes at next vblank */ 623 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 624 625 if (event) { 626 crtc->state->event = NULL; 627 628 spin_lock_irq(&ddev->event_lock); 629 if (drm_crtc_vblank_get(crtc) == 0) 630 drm_crtc_arm_vblank_event(crtc, event); 631 else 632 drm_crtc_send_vblank_event(crtc, event); 633 spin_unlock_irq(&ddev->event_lock); 634 } 635 } 636 637 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 638 bool in_vblank_irq, 639 int *vpos, int *hpos, 640 ktime_t *stime, ktime_t *etime, 641 const struct drm_display_mode *mode) 642 { 643 struct drm_device *ddev = crtc->dev; 644 struct ltdc_device *ldev = ddev->dev_private; 645 int line, vactive_start, vactive_end, vtotal; 646 647 if (stime) 648 *stime = ktime_get(); 649 650 /* The active area starts after vsync + front porch and ends 651 * at vsync + front porc + display size. 652 * The total height also include back porch. 653 * We have 3 possible cases to handle: 654 * - line < vactive_start: vpos = line - vactive_start and will be 655 * negative 656 * - vactive_start < line < vactive_end: vpos = line - vactive_start 657 * and will be positive 658 * - line > vactive_end: vpos = line - vtotal - vactive_start 659 * and will negative 660 * 661 * Computation for the two first cases are identical so we can 662 * simplify the code and only test if line > vactive_end 663 */ 664 if (pm_runtime_active(ddev->dev)) { 665 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 666 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 667 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 668 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 669 670 if (line > vactive_end) 671 *vpos = line - vtotal - vactive_start; 672 else 673 *vpos = line - vactive_start; 674 } else { 675 *vpos = 0; 676 } 677 678 *hpos = 0; 679 680 if (etime) 681 *etime = ktime_get(); 682 683 return true; 684 } 685 686 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 687 .mode_valid = ltdc_crtc_mode_valid, 688 .mode_fixup = ltdc_crtc_mode_fixup, 689 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 690 .atomic_flush = ltdc_crtc_atomic_flush, 691 .atomic_enable = ltdc_crtc_atomic_enable, 692 .atomic_disable = ltdc_crtc_atomic_disable, 693 .get_scanout_position = ltdc_crtc_get_scanout_position, 694 }; 695 696 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 697 { 698 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 699 struct drm_crtc_state *state = crtc->state; 700 701 DRM_DEBUG_DRIVER("\n"); 702 703 if (state->enable) 704 reg_set(ldev->regs, LTDC_IER, IER_LIE); 705 else 706 return -EPERM; 707 708 return 0; 709 } 710 711 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 712 { 713 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 714 715 DRM_DEBUG_DRIVER("\n"); 716 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 717 } 718 719 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 720 .destroy = drm_crtc_cleanup, 721 .set_config = drm_atomic_helper_set_config, 722 .page_flip = drm_atomic_helper_page_flip, 723 .reset = drm_atomic_helper_crtc_reset, 724 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 725 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 726 .enable_vblank = ltdc_crtc_enable_vblank, 727 .disable_vblank = ltdc_crtc_disable_vblank, 728 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 729 .gamma_set = drm_atomic_helper_legacy_gamma_set, 730 }; 731 732 /* 733 * DRM_PLANE 734 */ 735 736 static int ltdc_plane_atomic_check(struct drm_plane *plane, 737 struct drm_plane_state *state) 738 { 739 struct drm_framebuffer *fb = state->fb; 740 u32 src_w, src_h; 741 742 DRM_DEBUG_DRIVER("\n"); 743 744 if (!fb) 745 return 0; 746 747 /* convert src_ from 16:16 format */ 748 src_w = state->src_w >> 16; 749 src_h = state->src_h >> 16; 750 751 /* Reject scaling */ 752 if (src_w != state->crtc_w || src_h != state->crtc_h) { 753 DRM_ERROR("Scaling is not supported"); 754 return -EINVAL; 755 } 756 757 return 0; 758 } 759 760 static void ltdc_plane_atomic_update(struct drm_plane *plane, 761 struct drm_plane_state *oldstate) 762 { 763 struct ltdc_device *ldev = plane_to_ltdc(plane); 764 struct drm_plane_state *state = plane->state; 765 struct drm_framebuffer *fb = state->fb; 766 u32 lofs = plane->index * LAY_OFS; 767 u32 x0 = state->crtc_x; 768 u32 x1 = state->crtc_x + state->crtc_w - 1; 769 u32 y0 = state->crtc_y; 770 u32 y1 = state->crtc_y + state->crtc_h - 1; 771 u32 src_x, src_y, src_w, src_h; 772 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 773 enum ltdc_pix_fmt pf; 774 775 if (!state->crtc || !fb) { 776 DRM_DEBUG_DRIVER("fb or crtc NULL"); 777 return; 778 } 779 780 /* convert src_ from 16:16 format */ 781 src_x = state->src_x >> 16; 782 src_y = state->src_y >> 16; 783 src_w = state->src_w >> 16; 784 src_h = state->src_h >> 16; 785 786 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 787 plane->base.id, fb->base.id, 788 src_w, src_h, src_x, src_y, 789 state->crtc_w, state->crtc_h, 790 state->crtc_x, state->crtc_y); 791 792 bpcr = reg_read(ldev->regs, LTDC_BPCR); 793 ahbp = (bpcr & BPCR_AHBP) >> 16; 794 avbp = bpcr & BPCR_AVBP; 795 796 /* Configures the horizontal start and stop position */ 797 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 798 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 799 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 800 801 /* Configures the vertical start and stop position */ 802 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 803 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 804 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 805 806 /* Specifies the pixel format */ 807 pf = to_ltdc_pixelformat(fb->format->format); 808 for (val = 0; val < NB_PF; val++) 809 if (ldev->caps.pix_fmt_hw[val] == pf) 810 break; 811 812 if (val == NB_PF) { 813 DRM_ERROR("Pixel format %.4s not supported\n", 814 (char *)&fb->format->format); 815 val = 0; /* set by default ARGB 32 bits */ 816 } 817 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 818 819 /* Configures the color frame buffer pitch in bytes & line length */ 820 pitch_in_bytes = fb->pitches[0]; 821 line_length = fb->format->cpp[0] * 822 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 823 val = ((pitch_in_bytes << 16) | line_length); 824 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 825 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 826 827 /* Specifies the constant alpha value */ 828 val = CONSTA_MAX; 829 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 830 831 /* Specifies the blending factors */ 832 val = BF1_PAXCA | BF2_1PAXCA; 833 if (!fb->format->has_alpha) 834 val = BF1_CA | BF2_1CA; 835 836 /* Manage hw-specific capabilities */ 837 if (ldev->caps.non_alpha_only_l1 && 838 plane->type != DRM_PLANE_TYPE_PRIMARY) 839 val = BF1_PAXCA | BF2_1PAXCA; 840 841 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 842 LXBFCR_BF2 | LXBFCR_BF1, val); 843 844 /* Configures the frame buffer line number */ 845 val = y1 - y0 + 1; 846 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 847 848 /* Sets the FB address */ 849 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 850 851 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 852 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 853 854 /* Enable layer and CLUT if needed */ 855 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 856 val |= LXCR_LEN; 857 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 858 LXCR_LEN | LXCR_CLUTEN, val); 859 860 ldev->plane_fpsi[plane->index].counter++; 861 862 mutex_lock(&ldev->err_lock); 863 if (ldev->error_status & ISR_FUIF) { 864 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 865 ldev->error_status &= ~ISR_FUIF; 866 } 867 if (ldev->error_status & ISR_TERRIF) { 868 DRM_WARN("ltdc transfer error\n"); 869 ldev->error_status &= ~ISR_TERRIF; 870 } 871 mutex_unlock(&ldev->err_lock); 872 } 873 874 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 875 struct drm_plane_state *oldstate) 876 { 877 struct ltdc_device *ldev = plane_to_ltdc(plane); 878 u32 lofs = plane->index * LAY_OFS; 879 880 /* disable layer */ 881 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 882 883 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 884 oldstate->crtc->base.id, plane->base.id); 885 } 886 887 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 888 const struct drm_plane_state *state) 889 { 890 struct drm_plane *plane = state->plane; 891 struct ltdc_device *ldev = plane_to_ltdc(plane); 892 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 893 int ms_since_last; 894 ktime_t now; 895 896 now = ktime_get(); 897 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 898 899 drm_printf(p, "\tuser_updates=%dfps\n", 900 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 901 902 fpsi->last_timestamp = now; 903 fpsi->counter = 0; 904 } 905 906 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 907 u32 format, 908 u64 modifier) 909 { 910 if (modifier == DRM_FORMAT_MOD_LINEAR) 911 return true; 912 913 return false; 914 } 915 916 static const struct drm_plane_funcs ltdc_plane_funcs = { 917 .update_plane = drm_atomic_helper_update_plane, 918 .disable_plane = drm_atomic_helper_disable_plane, 919 .destroy = drm_plane_cleanup, 920 .reset = drm_atomic_helper_plane_reset, 921 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 922 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 923 .atomic_print_state = ltdc_plane_atomic_print_state, 924 .format_mod_supported = ltdc_plane_format_mod_supported, 925 }; 926 927 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 928 .prepare_fb = drm_gem_fb_prepare_fb, 929 .atomic_check = ltdc_plane_atomic_check, 930 .atomic_update = ltdc_plane_atomic_update, 931 .atomic_disable = ltdc_plane_atomic_disable, 932 }; 933 934 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 935 enum drm_plane_type type) 936 { 937 unsigned long possible_crtcs = CRTC_MASK; 938 struct ltdc_device *ldev = ddev->dev_private; 939 struct device *dev = ddev->dev; 940 struct drm_plane *plane; 941 unsigned int i, nb_fmt = 0; 942 u32 formats[NB_PF * 2]; 943 u32 drm_fmt, drm_fmt_no_alpha; 944 const u64 *modifiers = ltdc_format_modifiers; 945 int ret; 946 947 /* Get supported pixel formats */ 948 for (i = 0; i < NB_PF; i++) { 949 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 950 if (!drm_fmt) 951 continue; 952 formats[nb_fmt++] = drm_fmt; 953 954 /* Add the no-alpha related format if any & supported */ 955 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 956 if (!drm_fmt_no_alpha) 957 continue; 958 959 /* Manage hw-specific capabilities */ 960 if (ldev->caps.non_alpha_only_l1 && 961 type != DRM_PLANE_TYPE_PRIMARY) 962 continue; 963 964 formats[nb_fmt++] = drm_fmt_no_alpha; 965 } 966 967 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 968 if (!plane) 969 return NULL; 970 971 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 972 <dc_plane_funcs, formats, nb_fmt, 973 modifiers, type, NULL); 974 if (ret < 0) 975 return NULL; 976 977 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 978 979 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 980 981 return plane; 982 } 983 984 static void ltdc_plane_destroy_all(struct drm_device *ddev) 985 { 986 struct drm_plane *plane, *plane_temp; 987 988 list_for_each_entry_safe(plane, plane_temp, 989 &ddev->mode_config.plane_list, head) 990 drm_plane_cleanup(plane); 991 } 992 993 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 994 { 995 struct ltdc_device *ldev = ddev->dev_private; 996 struct drm_plane *primary, *overlay; 997 unsigned int i; 998 int ret; 999 1000 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 1001 if (!primary) { 1002 DRM_ERROR("Can not create primary plane\n"); 1003 return -EINVAL; 1004 } 1005 1006 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1007 <dc_crtc_funcs, NULL); 1008 if (ret) { 1009 DRM_ERROR("Can not initialize CRTC\n"); 1010 goto cleanup; 1011 } 1012 1013 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1014 1015 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1016 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1017 1018 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1019 1020 /* Add planes. Note : the first layer is used by primary plane */ 1021 for (i = 1; i < ldev->caps.nb_layers; i++) { 1022 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 1023 if (!overlay) { 1024 ret = -ENOMEM; 1025 DRM_ERROR("Can not create overlay plane %d\n", i); 1026 goto cleanup; 1027 } 1028 } 1029 1030 return 0; 1031 1032 cleanup: 1033 ltdc_plane_destroy_all(ddev); 1034 return ret; 1035 } 1036 1037 /* 1038 * DRM_ENCODER 1039 */ 1040 1041 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 1042 .destroy = drm_encoder_cleanup, 1043 }; 1044 1045 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1046 { 1047 struct drm_device *ddev = encoder->dev; 1048 struct ltdc_device *ldev = ddev->dev_private; 1049 1050 DRM_DEBUG_DRIVER("\n"); 1051 1052 /* Disable LTDC */ 1053 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 1054 1055 /* Set to sleep state the pinctrl whatever type of encoder */ 1056 pinctrl_pm_select_sleep_state(ddev->dev); 1057 } 1058 1059 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1060 { 1061 struct drm_device *ddev = encoder->dev; 1062 struct ltdc_device *ldev = ddev->dev_private; 1063 1064 DRM_DEBUG_DRIVER("\n"); 1065 1066 /* Enable LTDC */ 1067 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 1068 } 1069 1070 static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1071 struct drm_display_mode *mode, 1072 struct drm_display_mode *adjusted_mode) 1073 { 1074 struct drm_device *ddev = encoder->dev; 1075 1076 DRM_DEBUG_DRIVER("\n"); 1077 1078 /* 1079 * Set to default state the pinctrl only with DPI type. 1080 * Others types like DSI, don't need pinctrl due to 1081 * internal bridge (the signals do not come out of the chipset). 1082 */ 1083 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1084 pinctrl_pm_select_default_state(ddev->dev); 1085 } 1086 1087 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1088 .disable = ltdc_encoder_disable, 1089 .enable = ltdc_encoder_enable, 1090 .mode_set = ltdc_encoder_mode_set, 1091 }; 1092 1093 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1094 { 1095 struct drm_encoder *encoder; 1096 int ret; 1097 1098 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1099 if (!encoder) 1100 return -ENOMEM; 1101 1102 encoder->possible_crtcs = CRTC_MASK; 1103 encoder->possible_clones = 0; /* No cloning support */ 1104 1105 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1106 DRM_MODE_ENCODER_DPI, NULL); 1107 1108 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1109 1110 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1111 if (ret) { 1112 drm_encoder_cleanup(encoder); 1113 return -EINVAL; 1114 } 1115 1116 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1117 1118 return 0; 1119 } 1120 1121 static int ltdc_get_caps(struct drm_device *ddev) 1122 { 1123 struct ltdc_device *ldev = ddev->dev_private; 1124 u32 bus_width_log2, lcr, gc2r; 1125 1126 /* 1127 * at least 1 layer must be managed & the number of layers 1128 * must not exceed LTDC_MAX_LAYER 1129 */ 1130 lcr = reg_read(ldev->regs, LTDC_LCR); 1131 1132 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1133 1134 /* set data bus width */ 1135 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1136 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1137 ldev->caps.bus_width = 8 << bus_width_log2; 1138 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1139 1140 switch (ldev->caps.hw_version) { 1141 case HWVER_10200: 1142 case HWVER_10300: 1143 ldev->caps.reg_ofs = REG_OFS_NONE; 1144 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1145 /* 1146 * Hw older versions support non-alpha color formats derived 1147 * from native alpha color formats only on the primary layer. 1148 * For instance, RG16 native format without alpha works fine 1149 * on 2nd layer but XR24 (derived color format from AR24) 1150 * does not work on 2nd layer. 1151 */ 1152 ldev->caps.non_alpha_only_l1 = true; 1153 ldev->caps.pad_max_freq_hz = 90000000; 1154 if (ldev->caps.hw_version == HWVER_10200) 1155 ldev->caps.pad_max_freq_hz = 65000000; 1156 ldev->caps.nb_irq = 2; 1157 break; 1158 case HWVER_20101: 1159 ldev->caps.reg_ofs = REG_OFS_4; 1160 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1161 ldev->caps.non_alpha_only_l1 = false; 1162 ldev->caps.pad_max_freq_hz = 150000000; 1163 ldev->caps.nb_irq = 4; 1164 break; 1165 default: 1166 return -ENODEV; 1167 } 1168 1169 return 0; 1170 } 1171 1172 void ltdc_suspend(struct drm_device *ddev) 1173 { 1174 struct ltdc_device *ldev = ddev->dev_private; 1175 1176 DRM_DEBUG_DRIVER("\n"); 1177 clk_disable_unprepare(ldev->pixel_clk); 1178 } 1179 1180 int ltdc_resume(struct drm_device *ddev) 1181 { 1182 struct ltdc_device *ldev = ddev->dev_private; 1183 int ret; 1184 1185 DRM_DEBUG_DRIVER("\n"); 1186 1187 ret = clk_prepare_enable(ldev->pixel_clk); 1188 if (ret) { 1189 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1190 return ret; 1191 } 1192 1193 return 0; 1194 } 1195 1196 int ltdc_load(struct drm_device *ddev) 1197 { 1198 struct platform_device *pdev = to_platform_device(ddev->dev); 1199 struct ltdc_device *ldev = ddev->dev_private; 1200 struct device *dev = ddev->dev; 1201 struct device_node *np = dev->of_node; 1202 struct drm_bridge *bridge; 1203 struct drm_panel *panel; 1204 struct drm_crtc *crtc; 1205 struct reset_control *rstc; 1206 struct resource *res; 1207 int irq, i, nb_endpoints; 1208 int ret = -ENODEV; 1209 1210 DRM_DEBUG_DRIVER("\n"); 1211 1212 /* Get number of endpoints */ 1213 nb_endpoints = of_graph_get_endpoint_count(np); 1214 if (!nb_endpoints) 1215 return -ENODEV; 1216 1217 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1218 if (IS_ERR(ldev->pixel_clk)) { 1219 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1220 DRM_ERROR("Unable to get lcd clock\n"); 1221 return PTR_ERR(ldev->pixel_clk); 1222 } 1223 1224 if (clk_prepare_enable(ldev->pixel_clk)) { 1225 DRM_ERROR("Unable to prepare pixel clock\n"); 1226 return -ENODEV; 1227 } 1228 1229 /* Get endpoints if any */ 1230 for (i = 0; i < nb_endpoints; i++) { 1231 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1232 1233 /* 1234 * If at least one endpoint is -ENODEV, continue probing, 1235 * else if at least one endpoint returned an error 1236 * (ie -EPROBE_DEFER) then stop probing. 1237 */ 1238 if (ret == -ENODEV) 1239 continue; 1240 else if (ret) 1241 goto err; 1242 1243 if (panel) { 1244 bridge = drm_panel_bridge_add_typed(panel, 1245 DRM_MODE_CONNECTOR_DPI); 1246 if (IS_ERR(bridge)) { 1247 DRM_ERROR("panel-bridge endpoint %d\n", i); 1248 ret = PTR_ERR(bridge); 1249 goto err; 1250 } 1251 } 1252 1253 if (bridge) { 1254 ret = ltdc_encoder_init(ddev, bridge); 1255 if (ret) { 1256 DRM_ERROR("init encoder endpoint %d\n", i); 1257 goto err; 1258 } 1259 } 1260 } 1261 1262 rstc = devm_reset_control_get_exclusive(dev, NULL); 1263 1264 mutex_init(&ldev->err_lock); 1265 1266 if (!IS_ERR(rstc)) { 1267 reset_control_assert(rstc); 1268 usleep_range(10, 20); 1269 reset_control_deassert(rstc); 1270 } 1271 1272 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1273 ldev->regs = devm_ioremap_resource(dev, res); 1274 if (IS_ERR(ldev->regs)) { 1275 DRM_ERROR("Unable to get ltdc registers\n"); 1276 ret = PTR_ERR(ldev->regs); 1277 goto err; 1278 } 1279 1280 /* Disable interrupts */ 1281 reg_clear(ldev->regs, LTDC_IER, 1282 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1283 1284 ret = ltdc_get_caps(ddev); 1285 if (ret) { 1286 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1287 ldev->caps.hw_version); 1288 goto err; 1289 } 1290 1291 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1292 1293 for (i = 0; i < ldev->caps.nb_irq; i++) { 1294 irq = platform_get_irq(pdev, i); 1295 if (irq < 0) { 1296 ret = irq; 1297 goto err; 1298 } 1299 1300 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1301 ltdc_irq_thread, IRQF_ONESHOT, 1302 dev_name(dev), ddev); 1303 if (ret) { 1304 DRM_ERROR("Failed to register LTDC interrupt\n"); 1305 goto err; 1306 } 1307 1308 } 1309 1310 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1311 if (!crtc) { 1312 DRM_ERROR("Failed to allocate crtc\n"); 1313 ret = -ENOMEM; 1314 goto err; 1315 } 1316 1317 ddev->mode_config.allow_fb_modifiers = true; 1318 1319 ret = ltdc_crtc_init(ddev, crtc); 1320 if (ret) { 1321 DRM_ERROR("Failed to init crtc\n"); 1322 goto err; 1323 } 1324 1325 ret = drm_vblank_init(ddev, NB_CRTC); 1326 if (ret) { 1327 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1328 goto err; 1329 } 1330 1331 /* Allow usage of vblank without having to call drm_irq_install */ 1332 ddev->irq_enabled = 1; 1333 1334 clk_disable_unprepare(ldev->pixel_clk); 1335 1336 pinctrl_pm_select_sleep_state(ddev->dev); 1337 1338 pm_runtime_enable(ddev->dev); 1339 1340 return 0; 1341 err: 1342 for (i = 0; i < nb_endpoints; i++) 1343 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1344 1345 clk_disable_unprepare(ldev->pixel_clk); 1346 1347 return ret; 1348 } 1349 1350 void ltdc_unload(struct drm_device *ddev) 1351 { 1352 struct device *dev = ddev->dev; 1353 int nb_endpoints, i; 1354 1355 DRM_DEBUG_DRIVER("\n"); 1356 1357 nb_endpoints = of_graph_get_endpoint_count(dev->of_node); 1358 1359 for (i = 0; i < nb_endpoints; i++) 1360 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1361 1362 pm_runtime_disable(ddev->dev); 1363 } 1364 1365 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1366 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1367 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1368 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1369 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1370 MODULE_LICENSE("GPL v2"); 1371