1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_device.h> 25 #include <drm/drm_fb_cma_helper.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_gem_cma_helper.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_plane_helper.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_vblank.h> 32 33 #include <video/videomode.h> 34 35 #include "ltdc.h" 36 37 #define NB_CRTC 1 38 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 39 40 #define MAX_IRQ 4 41 42 #define MAX_ENDPOINTS 2 43 44 #define HWVER_10200 0x010200 45 #define HWVER_10300 0x010300 46 #define HWVER_20101 0x020101 47 48 /* 49 * The address of some registers depends on the HW version: such registers have 50 * an extra offset specified with reg_ofs. 51 */ 52 #define REG_OFS_NONE 0 53 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 54 #define REG_OFS (ldev->caps.reg_ofs) 55 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 56 57 /* Global register offsets */ 58 #define LTDC_IDR 0x0000 /* IDentification */ 59 #define LTDC_LCR 0x0004 /* Layer Count */ 60 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 61 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 62 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 63 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 64 #define LTDC_GCR 0x0018 /* Global Control */ 65 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 66 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 67 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 68 #define LTDC_GACR 0x0028 /* GAmma Correction */ 69 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 70 #define LTDC_IER 0x0034 /* Interrupt Enable */ 71 #define LTDC_ISR 0x0038 /* Interrupt Status */ 72 #define LTDC_ICR 0x003C /* Interrupt Clear */ 73 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 74 #define LTDC_CPSR 0x0044 /* Current Position Status */ 75 #define LTDC_CDSR 0x0048 /* Current Display Status */ 76 77 /* Layer register offsets */ 78 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 79 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 80 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 81 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 82 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 83 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 84 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 85 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 86 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 87 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 88 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 89 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 90 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 91 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 92 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 93 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 94 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 95 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 96 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 97 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 98 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 99 100 /* Bit definitions */ 101 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 102 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 103 104 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 105 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 106 107 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 108 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 109 110 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 111 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 112 113 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 114 #define GCR_DEN BIT(16) /* Dither ENable */ 115 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 116 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 117 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 118 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 119 120 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 121 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 122 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 123 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 124 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 125 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 126 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 127 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 128 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 129 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 130 #define GC1R_TP BIT(25) /* Timing Programmable */ 131 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 132 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 133 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 134 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 135 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 136 137 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 138 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 139 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 140 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 141 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 142 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 143 144 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 145 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 146 147 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 148 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 149 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 150 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 151 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 152 153 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 154 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 155 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 156 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 157 158 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 159 160 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 161 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 162 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 163 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 164 165 #define LXCR_LEN BIT(0) /* Layer ENable */ 166 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 167 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 168 169 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 170 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 171 172 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 173 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 174 175 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 176 177 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 178 179 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 180 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 181 182 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 183 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 184 185 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 186 187 #define CLUT_SIZE 256 188 189 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 190 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 191 #define BF1_CA 0x400 /* Constant Alpha */ 192 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 193 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 194 195 #define NB_PF 8 /* Max nb of HW pixel format */ 196 197 enum ltdc_pix_fmt { 198 PF_NONE, 199 /* RGB formats */ 200 PF_ARGB8888, /* ARGB [32 bits] */ 201 PF_RGBA8888, /* RGBA [32 bits] */ 202 PF_RGB888, /* RGB [24 bits] */ 203 PF_RGB565, /* RGB [16 bits] */ 204 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 205 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 206 /* Indexed formats */ 207 PF_L8, /* Indexed 8 bits [8 bits] */ 208 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 209 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 210 }; 211 212 /* The index gives the encoding of the pixel format for an HW version */ 213 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 214 PF_ARGB8888, /* 0x00 */ 215 PF_RGB888, /* 0x01 */ 216 PF_RGB565, /* 0x02 */ 217 PF_ARGB1555, /* 0x03 */ 218 PF_ARGB4444, /* 0x04 */ 219 PF_L8, /* 0x05 */ 220 PF_AL44, /* 0x06 */ 221 PF_AL88 /* 0x07 */ 222 }; 223 224 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 225 PF_ARGB8888, /* 0x00 */ 226 PF_RGB888, /* 0x01 */ 227 PF_RGB565, /* 0x02 */ 228 PF_RGBA8888, /* 0x03 */ 229 PF_AL44, /* 0x04 */ 230 PF_L8, /* 0x05 */ 231 PF_ARGB1555, /* 0x06 */ 232 PF_ARGB4444 /* 0x07 */ 233 }; 234 235 static inline u32 reg_read(void __iomem *base, u32 reg) 236 { 237 return readl_relaxed(base + reg); 238 } 239 240 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 241 { 242 writel_relaxed(val, base + reg); 243 } 244 245 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 246 { 247 reg_write(base, reg, reg_read(base, reg) | mask); 248 } 249 250 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 251 { 252 reg_write(base, reg, reg_read(base, reg) & ~mask); 253 } 254 255 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 256 u32 val) 257 { 258 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 259 } 260 261 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 262 { 263 return (struct ltdc_device *)crtc->dev->dev_private; 264 } 265 266 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 267 { 268 return (struct ltdc_device *)plane->dev->dev_private; 269 } 270 271 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 272 { 273 return (struct ltdc_device *)enc->dev->dev_private; 274 } 275 276 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 277 { 278 enum ltdc_pix_fmt pf; 279 280 switch (drm_fmt) { 281 case DRM_FORMAT_ARGB8888: 282 case DRM_FORMAT_XRGB8888: 283 pf = PF_ARGB8888; 284 break; 285 case DRM_FORMAT_RGBA8888: 286 case DRM_FORMAT_RGBX8888: 287 pf = PF_RGBA8888; 288 break; 289 case DRM_FORMAT_RGB888: 290 pf = PF_RGB888; 291 break; 292 case DRM_FORMAT_RGB565: 293 pf = PF_RGB565; 294 break; 295 case DRM_FORMAT_ARGB1555: 296 case DRM_FORMAT_XRGB1555: 297 pf = PF_ARGB1555; 298 break; 299 case DRM_FORMAT_ARGB4444: 300 case DRM_FORMAT_XRGB4444: 301 pf = PF_ARGB4444; 302 break; 303 case DRM_FORMAT_C8: 304 pf = PF_L8; 305 break; 306 default: 307 pf = PF_NONE; 308 break; 309 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 310 } 311 312 return pf; 313 } 314 315 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 316 { 317 switch (pf) { 318 case PF_ARGB8888: 319 return DRM_FORMAT_ARGB8888; 320 case PF_RGBA8888: 321 return DRM_FORMAT_RGBA8888; 322 case PF_RGB888: 323 return DRM_FORMAT_RGB888; 324 case PF_RGB565: 325 return DRM_FORMAT_RGB565; 326 case PF_ARGB1555: 327 return DRM_FORMAT_ARGB1555; 328 case PF_ARGB4444: 329 return DRM_FORMAT_ARGB4444; 330 case PF_L8: 331 return DRM_FORMAT_C8; 332 case PF_AL44: /* No DRM support */ 333 case PF_AL88: /* No DRM support */ 334 case PF_NONE: 335 default: 336 return 0; 337 } 338 } 339 340 static inline u32 get_pixelformat_without_alpha(u32 drm) 341 { 342 switch (drm) { 343 case DRM_FORMAT_ARGB4444: 344 return DRM_FORMAT_XRGB4444; 345 case DRM_FORMAT_RGBA4444: 346 return DRM_FORMAT_RGBX4444; 347 case DRM_FORMAT_ARGB1555: 348 return DRM_FORMAT_XRGB1555; 349 case DRM_FORMAT_RGBA5551: 350 return DRM_FORMAT_RGBX5551; 351 case DRM_FORMAT_ARGB8888: 352 return DRM_FORMAT_XRGB8888; 353 case DRM_FORMAT_RGBA8888: 354 return DRM_FORMAT_RGBX8888; 355 default: 356 return 0; 357 } 358 } 359 360 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 361 { 362 struct drm_device *ddev = arg; 363 struct ltdc_device *ldev = ddev->dev_private; 364 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 365 366 /* Line IRQ : trigger the vblank event */ 367 if (ldev->irq_status & ISR_LIF) 368 drm_crtc_handle_vblank(crtc); 369 370 /* Save FIFO Underrun & Transfer Error status */ 371 mutex_lock(&ldev->err_lock); 372 if (ldev->irq_status & ISR_FUIF) 373 ldev->error_status |= ISR_FUIF; 374 if (ldev->irq_status & ISR_TERRIF) 375 ldev->error_status |= ISR_TERRIF; 376 mutex_unlock(&ldev->err_lock); 377 378 return IRQ_HANDLED; 379 } 380 381 static irqreturn_t ltdc_irq(int irq, void *arg) 382 { 383 struct drm_device *ddev = arg; 384 struct ltdc_device *ldev = ddev->dev_private; 385 386 /* Read & Clear the interrupt status */ 387 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 388 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 389 390 return IRQ_WAKE_THREAD; 391 } 392 393 /* 394 * DRM_CRTC 395 */ 396 397 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 398 { 399 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 400 struct drm_color_lut *lut; 401 u32 val; 402 int i; 403 404 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 405 return; 406 407 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 408 409 for (i = 0; i < CLUT_SIZE; i++, lut++) { 410 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 411 (lut->blue >> 8) | (i << 24); 412 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 413 } 414 } 415 416 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 417 struct drm_crtc_state *old_state) 418 { 419 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 420 421 DRM_DEBUG_DRIVER("\n"); 422 423 /* Sets the background color value */ 424 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 425 426 /* Enable IRQ */ 427 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 428 429 /* Immediately commit the planes */ 430 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 431 432 /* Enable LTDC */ 433 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 434 435 drm_crtc_vblank_on(crtc); 436 } 437 438 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 439 struct drm_crtc_state *old_state) 440 { 441 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 442 443 DRM_DEBUG_DRIVER("\n"); 444 445 drm_crtc_vblank_off(crtc); 446 447 /* disable LTDC */ 448 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 449 450 /* disable IRQ */ 451 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 452 453 /* immediately commit disable of layers before switching off LTDC */ 454 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 455 } 456 457 #define CLK_TOLERANCE_HZ 50 458 459 static enum drm_mode_status 460 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 461 const struct drm_display_mode *mode) 462 { 463 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 464 int target = mode->clock * 1000; 465 int target_min = target - CLK_TOLERANCE_HZ; 466 int target_max = target + CLK_TOLERANCE_HZ; 467 int result; 468 469 result = clk_round_rate(ldev->pixel_clk, target); 470 471 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 472 473 /* Filter modes according to the max frequency supported by the pads */ 474 if (result > ldev->caps.pad_max_freq_hz) 475 return MODE_CLOCK_HIGH; 476 477 /* 478 * Accept all "preferred" modes: 479 * - this is important for panels because panel clock tolerances are 480 * bigger than hdmi ones and there is no reason to not accept them 481 * (the fps may vary a little but it is not a problem). 482 * - the hdmi preferred mode will be accepted too, but userland will 483 * be able to use others hdmi "valid" modes if necessary. 484 */ 485 if (mode->type & DRM_MODE_TYPE_PREFERRED) 486 return MODE_OK; 487 488 /* 489 * Filter modes according to the clock value, particularly useful for 490 * hdmi modes that require precise pixel clocks. 491 */ 492 if (result < target_min || result > target_max) 493 return MODE_CLOCK_RANGE; 494 495 return MODE_OK; 496 } 497 498 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 499 const struct drm_display_mode *mode, 500 struct drm_display_mode *adjusted_mode) 501 { 502 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 503 int rate = mode->clock * 1000; 504 505 /* 506 * TODO clk_round_rate() does not work yet. When ready, it can 507 * be used instead of clk_set_rate() then clk_get_rate(). 508 */ 509 510 clk_disable(ldev->pixel_clk); 511 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 512 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 513 return false; 514 } 515 clk_enable(ldev->pixel_clk); 516 517 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 518 519 return true; 520 } 521 522 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 523 { 524 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 525 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 526 struct videomode vm; 527 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 528 u32 total_width, total_height; 529 u32 val; 530 531 drm_display_mode_to_videomode(mode, &vm); 532 533 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 534 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 535 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 536 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 537 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 538 539 /* Convert video timings to ltdc timings */ 540 hsync = vm.hsync_len - 1; 541 vsync = vm.vsync_len - 1; 542 accum_hbp = hsync + vm.hback_porch; 543 accum_vbp = vsync + vm.vback_porch; 544 accum_act_w = accum_hbp + vm.hactive; 545 accum_act_h = accum_vbp + vm.vactive; 546 total_width = accum_act_w + vm.hfront_porch; 547 total_height = accum_act_h + vm.vfront_porch; 548 549 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 550 val = 0; 551 552 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 553 val |= GCR_HSPOL; 554 555 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 556 val |= GCR_VSPOL; 557 558 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 559 val |= GCR_DEPOL; 560 561 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 562 val |= GCR_PCPOL; 563 564 reg_update_bits(ldev->regs, LTDC_GCR, 565 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 566 567 /* Set Synchronization size */ 568 val = (hsync << 16) | vsync; 569 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 570 571 /* Set Accumulated Back porch */ 572 val = (accum_hbp << 16) | accum_vbp; 573 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 574 575 /* Set Accumulated Active Width */ 576 val = (accum_act_w << 16) | accum_act_h; 577 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 578 579 /* Set total width & height */ 580 val = (total_width << 16) | total_height; 581 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 582 583 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 584 } 585 586 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 587 struct drm_crtc_state *old_crtc_state) 588 { 589 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 590 struct drm_pending_vblank_event *event = crtc->state->event; 591 592 DRM_DEBUG_ATOMIC("\n"); 593 594 ltdc_crtc_update_clut(crtc); 595 596 /* Commit shadow registers = update planes at next vblank */ 597 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 598 599 if (event) { 600 crtc->state->event = NULL; 601 602 spin_lock_irq(&crtc->dev->event_lock); 603 if (drm_crtc_vblank_get(crtc) == 0) 604 drm_crtc_arm_vblank_event(crtc, event); 605 else 606 drm_crtc_send_vblank_event(crtc, event); 607 spin_unlock_irq(&crtc->dev->event_lock); 608 } 609 } 610 611 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 612 .mode_valid = ltdc_crtc_mode_valid, 613 .mode_fixup = ltdc_crtc_mode_fixup, 614 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 615 .atomic_flush = ltdc_crtc_atomic_flush, 616 .atomic_enable = ltdc_crtc_atomic_enable, 617 .atomic_disable = ltdc_crtc_atomic_disable, 618 }; 619 620 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 621 { 622 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 623 624 DRM_DEBUG_DRIVER("\n"); 625 reg_set(ldev->regs, LTDC_IER, IER_LIE); 626 627 return 0; 628 } 629 630 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 631 { 632 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 633 634 DRM_DEBUG_DRIVER("\n"); 635 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 636 } 637 638 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe, 639 bool in_vblank_irq, int *vpos, int *hpos, 640 ktime_t *stime, ktime_t *etime, 641 const struct drm_display_mode *mode) 642 { 643 struct ltdc_device *ldev = ddev->dev_private; 644 int line, vactive_start, vactive_end, vtotal; 645 646 if (stime) 647 *stime = ktime_get(); 648 649 /* The active area starts after vsync + front porch and ends 650 * at vsync + front porc + display size. 651 * The total height also include back porch. 652 * We have 3 possible cases to handle: 653 * - line < vactive_start: vpos = line - vactive_start and will be 654 * negative 655 * - vactive_start < line < vactive_end: vpos = line - vactive_start 656 * and will be positive 657 * - line > vactive_end: vpos = line - vtotal - vactive_start 658 * and will negative 659 * 660 * Computation for the two first cases are identical so we can 661 * simplify the code and only test if line > vactive_end 662 */ 663 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 664 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 665 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 666 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 667 668 if (line > vactive_end) 669 *vpos = line - vtotal - vactive_start; 670 else 671 *vpos = line - vactive_start; 672 673 *hpos = 0; 674 675 if (etime) 676 *etime = ktime_get(); 677 678 return true; 679 } 680 681 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 682 .destroy = drm_crtc_cleanup, 683 .set_config = drm_atomic_helper_set_config, 684 .page_flip = drm_atomic_helper_page_flip, 685 .reset = drm_atomic_helper_crtc_reset, 686 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 687 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 688 .enable_vblank = ltdc_crtc_enable_vblank, 689 .disable_vblank = ltdc_crtc_disable_vblank, 690 .gamma_set = drm_atomic_helper_legacy_gamma_set, 691 }; 692 693 /* 694 * DRM_PLANE 695 */ 696 697 static int ltdc_plane_atomic_check(struct drm_plane *plane, 698 struct drm_plane_state *state) 699 { 700 struct drm_framebuffer *fb = state->fb; 701 u32 src_w, src_h; 702 703 DRM_DEBUG_DRIVER("\n"); 704 705 if (!fb) 706 return 0; 707 708 /* convert src_ from 16:16 format */ 709 src_w = state->src_w >> 16; 710 src_h = state->src_h >> 16; 711 712 /* Reject scaling */ 713 if (src_w != state->crtc_w || src_h != state->crtc_h) { 714 DRM_ERROR("Scaling is not supported"); 715 return -EINVAL; 716 } 717 718 return 0; 719 } 720 721 static void ltdc_plane_atomic_update(struct drm_plane *plane, 722 struct drm_plane_state *oldstate) 723 { 724 struct ltdc_device *ldev = plane_to_ltdc(plane); 725 struct drm_plane_state *state = plane->state; 726 struct drm_framebuffer *fb = state->fb; 727 u32 lofs = plane->index * LAY_OFS; 728 u32 x0 = state->crtc_x; 729 u32 x1 = state->crtc_x + state->crtc_w - 1; 730 u32 y0 = state->crtc_y; 731 u32 y1 = state->crtc_y + state->crtc_h - 1; 732 u32 src_x, src_y, src_w, src_h; 733 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 734 enum ltdc_pix_fmt pf; 735 736 if (!state->crtc || !fb) { 737 DRM_DEBUG_DRIVER("fb or crtc NULL"); 738 return; 739 } 740 741 /* convert src_ from 16:16 format */ 742 src_x = state->src_x >> 16; 743 src_y = state->src_y >> 16; 744 src_w = state->src_w >> 16; 745 src_h = state->src_h >> 16; 746 747 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 748 plane->base.id, fb->base.id, 749 src_w, src_h, src_x, src_y, 750 state->crtc_w, state->crtc_h, 751 state->crtc_x, state->crtc_y); 752 753 bpcr = reg_read(ldev->regs, LTDC_BPCR); 754 ahbp = (bpcr & BPCR_AHBP) >> 16; 755 avbp = bpcr & BPCR_AVBP; 756 757 /* Configures the horizontal start and stop position */ 758 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 759 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 760 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 761 762 /* Configures the vertical start and stop position */ 763 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 764 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 765 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 766 767 /* Specifies the pixel format */ 768 pf = to_ltdc_pixelformat(fb->format->format); 769 for (val = 0; val < NB_PF; val++) 770 if (ldev->caps.pix_fmt_hw[val] == pf) 771 break; 772 773 if (val == NB_PF) { 774 DRM_ERROR("Pixel format %.4s not supported\n", 775 (char *)&fb->format->format); 776 val = 0; /* set by default ARGB 32 bits */ 777 } 778 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 779 780 /* Configures the color frame buffer pitch in bytes & line length */ 781 pitch_in_bytes = fb->pitches[0]; 782 line_length = drm_format_plane_cpp(fb->format->format, 0) * 783 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 784 val = ((pitch_in_bytes << 16) | line_length); 785 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 786 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 787 788 /* Specifies the constant alpha value */ 789 val = CONSTA_MAX; 790 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 791 792 /* Specifies the blending factors */ 793 val = BF1_PAXCA | BF2_1PAXCA; 794 if (!fb->format->has_alpha) 795 val = BF1_CA | BF2_1CA; 796 797 /* Manage hw-specific capabilities */ 798 if (ldev->caps.non_alpha_only_l1 && 799 plane->type != DRM_PLANE_TYPE_PRIMARY) 800 val = BF1_PAXCA | BF2_1PAXCA; 801 802 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 803 LXBFCR_BF2 | LXBFCR_BF1, val); 804 805 /* Configures the frame buffer line number */ 806 val = y1 - y0 + 1; 807 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 808 809 /* Sets the FB address */ 810 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 811 812 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 813 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 814 815 /* Enable layer and CLUT if needed */ 816 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 817 val |= LXCR_LEN; 818 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 819 LXCR_LEN | LXCR_CLUTEN, val); 820 821 ldev->plane_fpsi[plane->index].counter++; 822 823 mutex_lock(&ldev->err_lock); 824 if (ldev->error_status & ISR_FUIF) { 825 DRM_DEBUG_DRIVER("Fifo underrun\n"); 826 ldev->error_status &= ~ISR_FUIF; 827 } 828 if (ldev->error_status & ISR_TERRIF) { 829 DRM_DEBUG_DRIVER("Transfer error\n"); 830 ldev->error_status &= ~ISR_TERRIF; 831 } 832 mutex_unlock(&ldev->err_lock); 833 } 834 835 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 836 struct drm_plane_state *oldstate) 837 { 838 struct ltdc_device *ldev = plane_to_ltdc(plane); 839 u32 lofs = plane->index * LAY_OFS; 840 841 /* disable layer */ 842 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 843 844 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 845 oldstate->crtc->base.id, plane->base.id); 846 } 847 848 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 849 const struct drm_plane_state *state) 850 { 851 struct drm_plane *plane = state->plane; 852 struct ltdc_device *ldev = plane_to_ltdc(plane); 853 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 854 int ms_since_last; 855 ktime_t now; 856 857 now = ktime_get(); 858 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 859 860 drm_printf(p, "\tuser_updates=%dfps\n", 861 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 862 863 fpsi->last_timestamp = now; 864 fpsi->counter = 0; 865 } 866 867 static const struct drm_plane_funcs ltdc_plane_funcs = { 868 .update_plane = drm_atomic_helper_update_plane, 869 .disable_plane = drm_atomic_helper_disable_plane, 870 .destroy = drm_plane_cleanup, 871 .reset = drm_atomic_helper_plane_reset, 872 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 873 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 874 .atomic_print_state = ltdc_plane_atomic_print_state, 875 }; 876 877 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 878 .atomic_check = ltdc_plane_atomic_check, 879 .atomic_update = ltdc_plane_atomic_update, 880 .atomic_disable = ltdc_plane_atomic_disable, 881 }; 882 883 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 884 enum drm_plane_type type) 885 { 886 unsigned long possible_crtcs = CRTC_MASK; 887 struct ltdc_device *ldev = ddev->dev_private; 888 struct device *dev = ddev->dev; 889 struct drm_plane *plane; 890 unsigned int i, nb_fmt = 0; 891 u32 formats[NB_PF * 2]; 892 u32 drm_fmt, drm_fmt_no_alpha; 893 int ret; 894 895 /* Get supported pixel formats */ 896 for (i = 0; i < NB_PF; i++) { 897 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 898 if (!drm_fmt) 899 continue; 900 formats[nb_fmt++] = drm_fmt; 901 902 /* Add the no-alpha related format if any & supported */ 903 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 904 if (!drm_fmt_no_alpha) 905 continue; 906 907 /* Manage hw-specific capabilities */ 908 if (ldev->caps.non_alpha_only_l1 && 909 type != DRM_PLANE_TYPE_PRIMARY) 910 continue; 911 912 formats[nb_fmt++] = drm_fmt_no_alpha; 913 } 914 915 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 916 if (!plane) 917 return NULL; 918 919 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 920 <dc_plane_funcs, formats, nb_fmt, 921 NULL, type, NULL); 922 if (ret < 0) 923 return NULL; 924 925 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 926 927 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 928 929 return plane; 930 } 931 932 static void ltdc_plane_destroy_all(struct drm_device *ddev) 933 { 934 struct drm_plane *plane, *plane_temp; 935 936 list_for_each_entry_safe(plane, plane_temp, 937 &ddev->mode_config.plane_list, head) 938 drm_plane_cleanup(plane); 939 } 940 941 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 942 { 943 struct ltdc_device *ldev = ddev->dev_private; 944 struct drm_plane *primary, *overlay; 945 unsigned int i; 946 int ret; 947 948 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 949 if (!primary) { 950 DRM_ERROR("Can not create primary plane\n"); 951 return -EINVAL; 952 } 953 954 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 955 <dc_crtc_funcs, NULL); 956 if (ret) { 957 DRM_ERROR("Can not initialize CRTC\n"); 958 goto cleanup; 959 } 960 961 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 962 963 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 964 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 965 966 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 967 968 /* Add planes. Note : the first layer is used by primary plane */ 969 for (i = 1; i < ldev->caps.nb_layers; i++) { 970 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 971 if (!overlay) { 972 ret = -ENOMEM; 973 DRM_ERROR("Can not create overlay plane %d\n", i); 974 goto cleanup; 975 } 976 } 977 978 return 0; 979 980 cleanup: 981 ltdc_plane_destroy_all(ddev); 982 return ret; 983 } 984 985 /* 986 * DRM_ENCODER 987 */ 988 989 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 990 .destroy = drm_encoder_cleanup, 991 }; 992 993 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 994 { 995 struct drm_encoder *encoder; 996 int ret; 997 998 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 999 if (!encoder) 1000 return -ENOMEM; 1001 1002 encoder->possible_crtcs = CRTC_MASK; 1003 encoder->possible_clones = 0; /* No cloning support */ 1004 1005 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1006 DRM_MODE_ENCODER_DPI, NULL); 1007 1008 ret = drm_bridge_attach(encoder, bridge, NULL); 1009 if (ret) { 1010 drm_encoder_cleanup(encoder); 1011 return -EINVAL; 1012 } 1013 1014 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1015 1016 return 0; 1017 } 1018 1019 static int ltdc_get_caps(struct drm_device *ddev) 1020 { 1021 struct ltdc_device *ldev = ddev->dev_private; 1022 u32 bus_width_log2, lcr, gc2r; 1023 1024 /* at least 1 layer must be managed */ 1025 lcr = reg_read(ldev->regs, LTDC_LCR); 1026 1027 ldev->caps.nb_layers = max_t(int, lcr, 1); 1028 1029 /* set data bus width */ 1030 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1031 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1032 ldev->caps.bus_width = 8 << bus_width_log2; 1033 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1034 1035 switch (ldev->caps.hw_version) { 1036 case HWVER_10200: 1037 case HWVER_10300: 1038 ldev->caps.reg_ofs = REG_OFS_NONE; 1039 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1040 /* 1041 * Hw older versions support non-alpha color formats derived 1042 * from native alpha color formats only on the primary layer. 1043 * For instance, RG16 native format without alpha works fine 1044 * on 2nd layer but XR24 (derived color format from AR24) 1045 * does not work on 2nd layer. 1046 */ 1047 ldev->caps.non_alpha_only_l1 = true; 1048 ldev->caps.pad_max_freq_hz = 90000000; 1049 if (ldev->caps.hw_version == HWVER_10200) 1050 ldev->caps.pad_max_freq_hz = 65000000; 1051 break; 1052 case HWVER_20101: 1053 ldev->caps.reg_ofs = REG_OFS_4; 1054 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1055 ldev->caps.non_alpha_only_l1 = false; 1056 ldev->caps.pad_max_freq_hz = 150000000; 1057 break; 1058 default: 1059 return -ENODEV; 1060 } 1061 1062 return 0; 1063 } 1064 1065 void ltdc_suspend(struct drm_device *ddev) 1066 { 1067 struct ltdc_device *ldev = ddev->dev_private; 1068 1069 DRM_DEBUG_DRIVER("\n"); 1070 clk_disable_unprepare(ldev->pixel_clk); 1071 } 1072 1073 int ltdc_resume(struct drm_device *ddev) 1074 { 1075 struct ltdc_device *ldev = ddev->dev_private; 1076 int ret; 1077 1078 DRM_DEBUG_DRIVER("\n"); 1079 1080 ret = clk_prepare_enable(ldev->pixel_clk); 1081 if (ret) { 1082 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1083 return ret; 1084 } 1085 1086 return 0; 1087 } 1088 1089 int ltdc_load(struct drm_device *ddev) 1090 { 1091 struct platform_device *pdev = to_platform_device(ddev->dev); 1092 struct ltdc_device *ldev = ddev->dev_private; 1093 struct device *dev = ddev->dev; 1094 struct device_node *np = dev->of_node; 1095 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1096 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1097 struct drm_crtc *crtc; 1098 struct reset_control *rstc; 1099 struct resource *res; 1100 int irq, ret, i, endpoint_not_ready = -ENODEV; 1101 1102 DRM_DEBUG_DRIVER("\n"); 1103 1104 /* Get endpoints if any */ 1105 for (i = 0; i < MAX_ENDPOINTS; i++) { 1106 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1107 &bridge[i]); 1108 1109 /* 1110 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1111 * else if at least one endpoint is ready, continue probing. 1112 */ 1113 if (ret == -EPROBE_DEFER) 1114 return ret; 1115 else if (!ret) 1116 endpoint_not_ready = 0; 1117 } 1118 1119 if (endpoint_not_ready) 1120 return endpoint_not_ready; 1121 1122 rstc = devm_reset_control_get_exclusive(dev, NULL); 1123 1124 mutex_init(&ldev->err_lock); 1125 1126 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1127 if (IS_ERR(ldev->pixel_clk)) { 1128 DRM_ERROR("Unable to get lcd clock\n"); 1129 return -ENODEV; 1130 } 1131 1132 if (clk_prepare_enable(ldev->pixel_clk)) { 1133 DRM_ERROR("Unable to prepare pixel clock\n"); 1134 return -ENODEV; 1135 } 1136 1137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1138 ldev->regs = devm_ioremap_resource(dev, res); 1139 if (IS_ERR(ldev->regs)) { 1140 DRM_ERROR("Unable to get ltdc registers\n"); 1141 ret = PTR_ERR(ldev->regs); 1142 goto err; 1143 } 1144 1145 for (i = 0; i < MAX_IRQ; i++) { 1146 irq = platform_get_irq(pdev, i); 1147 if (irq < 0) 1148 continue; 1149 1150 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1151 ltdc_irq_thread, IRQF_ONESHOT, 1152 dev_name(dev), ddev); 1153 if (ret) { 1154 DRM_ERROR("Failed to register LTDC interrupt\n"); 1155 goto err; 1156 } 1157 } 1158 1159 if (!IS_ERR(rstc)) { 1160 reset_control_assert(rstc); 1161 usleep_range(10, 20); 1162 reset_control_deassert(rstc); 1163 } 1164 1165 /* Disable interrupts */ 1166 reg_clear(ldev->regs, LTDC_IER, 1167 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1168 1169 ret = ltdc_get_caps(ddev); 1170 if (ret) { 1171 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1172 ldev->caps.hw_version); 1173 goto err; 1174 } 1175 1176 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 1177 1178 /* Add endpoints panels or bridges if any */ 1179 for (i = 0; i < MAX_ENDPOINTS; i++) { 1180 if (panel[i]) { 1181 bridge[i] = drm_panel_bridge_add(panel[i], 1182 DRM_MODE_CONNECTOR_DPI); 1183 if (IS_ERR(bridge[i])) { 1184 DRM_ERROR("panel-bridge endpoint %d\n", i); 1185 ret = PTR_ERR(bridge[i]); 1186 goto err; 1187 } 1188 } 1189 1190 if (bridge[i]) { 1191 ret = ltdc_encoder_init(ddev, bridge[i]); 1192 if (ret) { 1193 DRM_ERROR("init encoder endpoint %d\n", i); 1194 goto err; 1195 } 1196 } 1197 } 1198 1199 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1200 if (!crtc) { 1201 DRM_ERROR("Failed to allocate crtc\n"); 1202 ret = -ENOMEM; 1203 goto err; 1204 } 1205 1206 ret = ltdc_crtc_init(ddev, crtc); 1207 if (ret) { 1208 DRM_ERROR("Failed to init crtc\n"); 1209 goto err; 1210 } 1211 1212 ret = drm_vblank_init(ddev, NB_CRTC); 1213 if (ret) { 1214 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1215 goto err; 1216 } 1217 1218 /* Allow usage of vblank without having to call drm_irq_install */ 1219 ddev->irq_enabled = 1; 1220 1221 return 0; 1222 1223 err: 1224 for (i = 0; i < MAX_ENDPOINTS; i++) 1225 drm_panel_bridge_remove(bridge[i]); 1226 1227 clk_disable_unprepare(ldev->pixel_clk); 1228 1229 return ret; 1230 } 1231 1232 void ltdc_unload(struct drm_device *ddev) 1233 { 1234 struct ltdc_device *ldev = ddev->dev_private; 1235 int i; 1236 1237 DRM_DEBUG_DRIVER("\n"); 1238 1239 for (i = 0; i < MAX_ENDPOINTS; i++) 1240 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1241 1242 clk_disable_unprepare(ldev->pixel_clk); 1243 } 1244 1245 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1246 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1247 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1248 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1249 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1250 MODULE_LICENSE("GPL v2"); 1251