1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 24 #include <drm/drm_atomic.h> 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_device.h> 28 #include <drm/drm_fb_cma_helper.h> 29 #include <drm/drm_fourcc.h> 30 #include <drm/drm_gem_atomic_helper.h> 31 #include <drm/drm_gem_cma_helper.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_plane_helper.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/drm_simple_kms_helper.h> 36 #include <drm/drm_vblank.h> 37 38 #include <video/videomode.h> 39 40 #include "ltdc.h" 41 42 #define NB_CRTC 1 43 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 44 45 #define MAX_IRQ 4 46 47 #define HWVER_10200 0x010200 48 #define HWVER_10300 0x010300 49 #define HWVER_20101 0x020101 50 #define HWVER_40100 0x040100 51 52 /* 53 * The address of some registers depends on the HW version: such registers have 54 * an extra offset specified with layer_ofs. 55 */ 56 #define LAY_OFS_0 0x80 57 #define LAY_OFS_1 0x100 58 #define LAY_OFS (ldev->caps.layer_ofs) 59 60 /* Global register offsets */ 61 #define LTDC_IDR 0x0000 /* IDentification */ 62 #define LTDC_LCR 0x0004 /* Layer Count */ 63 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 64 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 65 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 66 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 67 #define LTDC_GCR 0x0018 /* Global Control */ 68 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 69 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 70 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 71 #define LTDC_GACR 0x0028 /* GAmma Correction */ 72 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 73 #define LTDC_IER 0x0034 /* Interrupt Enable */ 74 #define LTDC_ISR 0x0038 /* Interrupt Status */ 75 #define LTDC_ICR 0x003C /* Interrupt Clear */ 76 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 77 #define LTDC_CPSR 0x0044 /* Current Position Status */ 78 #define LTDC_CDSR 0x0048 /* Current Display Status */ 79 #define LTDC_EDCR 0x0060 /* External Display Control */ 80 #define LTDC_FUT 0x0090 /* Fifo underrun Threshold */ 81 82 /* Layer register offsets */ 83 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */ 84 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */ 85 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */ 86 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */ 87 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */ 88 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */ 89 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */ 90 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */ 91 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */ 92 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */ 93 #define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */ 94 #define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */ 95 #define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */ 96 #define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */ 97 #define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */ 98 #define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */ 99 #define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ 100 #define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ 101 #define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */ 102 #define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */ 103 #define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */ 104 #define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */ 105 #define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */ 106 #define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */ 107 #define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */ 108 109 /* Bit definitions */ 110 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 111 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 112 113 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 114 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 115 116 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 117 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 118 119 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 120 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 121 122 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 123 #define GCR_DEN BIT(16) /* Dither ENable */ 124 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 125 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 126 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 127 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 128 129 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 130 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 131 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 132 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 133 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 134 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 135 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 136 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 137 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 138 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 139 #define GC1R_TP BIT(25) /* Timing Programmable */ 140 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 141 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 142 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 143 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 144 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 145 146 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 147 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 148 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 149 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 150 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 151 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 152 153 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 154 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 155 156 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 157 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 158 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 159 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 160 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 161 162 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 163 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 164 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 165 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 166 167 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 168 169 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 170 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 171 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 172 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 173 174 #define EDCR_OCYEN BIT(25) /* Output Conversion to YCbCr 422: ENable */ 175 #define EDCR_OCYSEL BIT(26) /* Output Conversion to YCbCr 422: SELection of the CCIR */ 176 #define EDCR_OCYCO BIT(27) /* Output Conversion to YCbCr 422: Chrominance Order */ 177 178 #define LXCR_LEN BIT(0) /* Layer ENable */ 179 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 180 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 181 182 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 183 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 184 185 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 186 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 187 188 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 189 #define PF_FLEXIBLE 0x7 /* Flexible Pixel Format selected */ 190 191 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 192 193 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 194 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 195 196 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 197 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 198 199 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 200 201 #define LXCR_C1R_YIA BIT(0) /* Ycbcr 422 Interleaved Ability */ 202 #define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */ 203 #define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */ 204 #define LXCR_C1R_SCA BIT(31) /* SCaling Ability*/ 205 206 #define LxPCR_YREN BIT(9) /* Y Rescale Enable for the color dynamic range */ 207 #define LxPCR_OF BIT(8) /* Odd pixel First */ 208 #define LxPCR_CBF BIT(7) /* CB component First */ 209 #define LxPCR_YF BIT(6) /* Y component First */ 210 #define LxPCR_YCM GENMASK(5, 4) /* Ycbcr Conversion Mode */ 211 #define YCM_I 0x0 /* Interleaved 422 */ 212 #define YCM_SP 0x1 /* Semi-Planar 420 */ 213 #define YCM_FP 0x2 /* Full-Planar 420 */ 214 #define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */ 215 216 #define LXRCR_IMR BIT(0) /* IMmediate Reload */ 217 #define LXRCR_VBR BIT(1) /* Vertical Blanking Reload */ 218 #define LXRCR_GRMSK BIT(2) /* Global (centralized) Reload MaSKed */ 219 220 #define CLUT_SIZE 256 221 222 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 223 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 224 #define BF1_CA 0x400 /* Constant Alpha */ 225 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 226 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 227 228 #define NB_PF 8 /* Max nb of HW pixel format */ 229 230 enum ltdc_pix_fmt { 231 PF_NONE, 232 /* RGB formats */ 233 PF_ARGB8888, /* ARGB [32 bits] */ 234 PF_RGBA8888, /* RGBA [32 bits] */ 235 PF_ABGR8888, /* ABGR [32 bits] */ 236 PF_BGRA8888, /* BGRA [32 bits] */ 237 PF_RGB888, /* RGB [24 bits] */ 238 PF_BGR888, /* BGR [24 bits] */ 239 PF_RGB565, /* RGB [16 bits] */ 240 PF_BGR565, /* BGR [16 bits] */ 241 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 242 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 243 /* Indexed formats */ 244 PF_L8, /* Indexed 8 bits [8 bits] */ 245 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 246 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 247 }; 248 249 /* The index gives the encoding of the pixel format for an HW version */ 250 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 251 PF_ARGB8888, /* 0x00 */ 252 PF_RGB888, /* 0x01 */ 253 PF_RGB565, /* 0x02 */ 254 PF_ARGB1555, /* 0x03 */ 255 PF_ARGB4444, /* 0x04 */ 256 PF_L8, /* 0x05 */ 257 PF_AL44, /* 0x06 */ 258 PF_AL88 /* 0x07 */ 259 }; 260 261 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 262 PF_ARGB8888, /* 0x00 */ 263 PF_RGB888, /* 0x01 */ 264 PF_RGB565, /* 0x02 */ 265 PF_RGBA8888, /* 0x03 */ 266 PF_AL44, /* 0x04 */ 267 PF_L8, /* 0x05 */ 268 PF_ARGB1555, /* 0x06 */ 269 PF_ARGB4444 /* 0x07 */ 270 }; 271 272 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = { 273 PF_ARGB8888, /* 0x00 */ 274 PF_ABGR8888, /* 0x01 */ 275 PF_RGBA8888, /* 0x02 */ 276 PF_BGRA8888, /* 0x03 */ 277 PF_RGB565, /* 0x04 */ 278 PF_BGR565, /* 0x05 */ 279 PF_RGB888, /* 0x06 */ 280 PF_NONE /* 0x07 */ 281 }; 282 283 static const u32 ltdc_drm_fmt_a0[] = { 284 DRM_FORMAT_ARGB8888, 285 DRM_FORMAT_XRGB8888, 286 DRM_FORMAT_RGB888, 287 DRM_FORMAT_RGB565, 288 DRM_FORMAT_ARGB1555, 289 DRM_FORMAT_XRGB1555, 290 DRM_FORMAT_ARGB4444, 291 DRM_FORMAT_XRGB4444, 292 DRM_FORMAT_C8 293 }; 294 295 static const u32 ltdc_drm_fmt_a1[] = { 296 DRM_FORMAT_ARGB8888, 297 DRM_FORMAT_XRGB8888, 298 DRM_FORMAT_RGB888, 299 DRM_FORMAT_RGB565, 300 DRM_FORMAT_RGBA8888, 301 DRM_FORMAT_RGBX8888, 302 DRM_FORMAT_ARGB1555, 303 DRM_FORMAT_XRGB1555, 304 DRM_FORMAT_ARGB4444, 305 DRM_FORMAT_XRGB4444, 306 DRM_FORMAT_C8 307 }; 308 309 static const u32 ltdc_drm_fmt_a2[] = { 310 DRM_FORMAT_ARGB8888, 311 DRM_FORMAT_XRGB8888, 312 DRM_FORMAT_ABGR8888, 313 DRM_FORMAT_XBGR8888, 314 DRM_FORMAT_RGBA8888, 315 DRM_FORMAT_RGBX8888, 316 DRM_FORMAT_BGRA8888, 317 DRM_FORMAT_BGRX8888, 318 DRM_FORMAT_RGB565, 319 DRM_FORMAT_BGR565, 320 DRM_FORMAT_RGB888, 321 DRM_FORMAT_BGR888, 322 DRM_FORMAT_ARGB1555, 323 DRM_FORMAT_XRGB1555, 324 DRM_FORMAT_ARGB4444, 325 DRM_FORMAT_XRGB4444, 326 DRM_FORMAT_C8 327 }; 328 329 static const u32 ltdc_drm_fmt_ycbcr_cp[] = { 330 DRM_FORMAT_YUYV, 331 DRM_FORMAT_YVYU, 332 DRM_FORMAT_UYVY, 333 DRM_FORMAT_VYUY 334 }; 335 336 static const u32 ltdc_drm_fmt_ycbcr_sp[] = { 337 DRM_FORMAT_NV12, 338 DRM_FORMAT_NV21 339 }; 340 341 static const u32 ltdc_drm_fmt_ycbcr_fp[] = { 342 DRM_FORMAT_YUV420, 343 DRM_FORMAT_YVU420 344 }; 345 346 /* Layer register offsets */ 347 static const u32 ltdc_layer_regs_a0[] = { 348 0x80, /* L1 configuration 0 */ 349 0x00, /* not available */ 350 0x00, /* not available */ 351 0x84, /* L1 control register */ 352 0x88, /* L1 window horizontal position configuration */ 353 0x8c, /* L1 window vertical position configuration */ 354 0x90, /* L1 color keying configuration */ 355 0x94, /* L1 pixel format configuration */ 356 0x98, /* L1 constant alpha configuration */ 357 0x9c, /* L1 default color configuration */ 358 0xa0, /* L1 blending factors configuration */ 359 0x00, /* not available */ 360 0x00, /* not available */ 361 0xac, /* L1 color frame buffer address */ 362 0xb0, /* L1 color frame buffer length */ 363 0xb4, /* L1 color frame buffer line number */ 364 0x00, /* not available */ 365 0x00, /* not available */ 366 0x00, /* not available */ 367 0x00, /* not available */ 368 0xc4, /* L1 CLUT write */ 369 0x00, /* not available */ 370 0x00, /* not available */ 371 0x00, /* not available */ 372 0x00 /* not available */ 373 }; 374 375 static const u32 ltdc_layer_regs_a1[] = { 376 0x80, /* L1 configuration 0 */ 377 0x84, /* L1 configuration 1 */ 378 0x00, /* L1 reload control */ 379 0x88, /* L1 control register */ 380 0x8c, /* L1 window horizontal position configuration */ 381 0x90, /* L1 window vertical position configuration */ 382 0x94, /* L1 color keying configuration */ 383 0x98, /* L1 pixel format configuration */ 384 0x9c, /* L1 constant alpha configuration */ 385 0xa0, /* L1 default color configuration */ 386 0xa4, /* L1 blending factors configuration */ 387 0xa8, /* L1 burst length configuration */ 388 0x00, /* not available */ 389 0xac, /* L1 color frame buffer address */ 390 0xb0, /* L1 color frame buffer length */ 391 0xb4, /* L1 color frame buffer line number */ 392 0xb8, /* L1 auxiliary frame buffer address 0 */ 393 0xbc, /* L1 auxiliary frame buffer address 1 */ 394 0xc0, /* L1 auxiliary frame buffer length */ 395 0xc4, /* L1 auxiliary frame buffer line number */ 396 0xc8, /* L1 CLUT write */ 397 0x00, /* not available */ 398 0x00, /* not available */ 399 0x00, /* not available */ 400 0x00 /* not available */ 401 }; 402 403 static const u32 ltdc_layer_regs_a2[] = { 404 0x100, /* L1 configuration 0 */ 405 0x104, /* L1 configuration 1 */ 406 0x108, /* L1 reload control */ 407 0x10c, /* L1 control register */ 408 0x110, /* L1 window horizontal position configuration */ 409 0x114, /* L1 window vertical position configuration */ 410 0x118, /* L1 color keying configuration */ 411 0x11c, /* L1 pixel format configuration */ 412 0x120, /* L1 constant alpha configuration */ 413 0x124, /* L1 default color configuration */ 414 0x128, /* L1 blending factors configuration */ 415 0x12c, /* L1 burst length configuration */ 416 0x130, /* L1 planar configuration */ 417 0x134, /* L1 color frame buffer address */ 418 0x138, /* L1 color frame buffer length */ 419 0x13c, /* L1 color frame buffer line number */ 420 0x140, /* L1 auxiliary frame buffer address 0 */ 421 0x144, /* L1 auxiliary frame buffer address 1 */ 422 0x148, /* L1 auxiliary frame buffer length */ 423 0x14c, /* L1 auxiliary frame buffer line number */ 424 0x150, /* L1 CLUT write */ 425 0x16c, /* L1 Conversion YCbCr RGB 0 */ 426 0x170, /* L1 Conversion YCbCr RGB 1 */ 427 0x174, /* L1 Flexible Pixel Format 0 */ 428 0x178 /* L1 Flexible Pixel Format 1 */ 429 }; 430 431 static const u64 ltdc_format_modifiers[] = { 432 DRM_FORMAT_MOD_LINEAR, 433 DRM_FORMAT_MOD_INVALID 434 }; 435 436 static const struct regmap_config stm32_ltdc_regmap_cfg = { 437 .reg_bits = 32, 438 .val_bits = 32, 439 .reg_stride = sizeof(u32), 440 .max_register = 0x400, 441 .use_relaxed_mmio = true, 442 .cache_type = REGCACHE_NONE, 443 }; 444 445 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = { 446 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 447 0x02040199, /* (b_cb = 516 / r_cr = 409) */ 448 0x006400D0 /* (g_cb = 100 / g_cr = 208) */ 449 }, 450 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 451 0x01C60167, /* (b_cb = 454 / r_cr = 359) */ 452 0x005800B7 /* (g_cb = 88 / g_cr = 183) */ 453 }, 454 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 455 0x021D01CB, /* (b_cb = 541 / r_cr = 459) */ 456 0x00370089 /* (g_cb = 55 / g_cr = 137) */ 457 }, 458 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 459 0x01DB0193, /* (b_cb = 475 / r_cr = 403) */ 460 0x00300078 /* (g_cb = 48 / g_cr = 120) */ 461 } 462 /* BT2020 not supported */ 463 }; 464 465 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 466 { 467 return (struct ltdc_device *)crtc->dev->dev_private; 468 } 469 470 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 471 { 472 return (struct ltdc_device *)plane->dev->dev_private; 473 } 474 475 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 476 { 477 return (struct ltdc_device *)enc->dev->dev_private; 478 } 479 480 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 481 { 482 enum ltdc_pix_fmt pf; 483 484 switch (drm_fmt) { 485 case DRM_FORMAT_ARGB8888: 486 case DRM_FORMAT_XRGB8888: 487 pf = PF_ARGB8888; 488 break; 489 case DRM_FORMAT_ABGR8888: 490 case DRM_FORMAT_XBGR8888: 491 pf = PF_ABGR8888; 492 break; 493 case DRM_FORMAT_RGBA8888: 494 case DRM_FORMAT_RGBX8888: 495 pf = PF_RGBA8888; 496 break; 497 case DRM_FORMAT_BGRA8888: 498 case DRM_FORMAT_BGRX8888: 499 pf = PF_BGRA8888; 500 break; 501 case DRM_FORMAT_RGB888: 502 pf = PF_RGB888; 503 break; 504 case DRM_FORMAT_BGR888: 505 pf = PF_BGR888; 506 break; 507 case DRM_FORMAT_RGB565: 508 pf = PF_RGB565; 509 break; 510 case DRM_FORMAT_BGR565: 511 pf = PF_BGR565; 512 break; 513 case DRM_FORMAT_ARGB1555: 514 case DRM_FORMAT_XRGB1555: 515 pf = PF_ARGB1555; 516 break; 517 case DRM_FORMAT_ARGB4444: 518 case DRM_FORMAT_XRGB4444: 519 pf = PF_ARGB4444; 520 break; 521 case DRM_FORMAT_C8: 522 pf = PF_L8; 523 break; 524 default: 525 pf = PF_NONE; 526 break; 527 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 528 } 529 530 return pf; 531 } 532 533 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt) 534 { 535 struct ltdc_device *ldev = plane_to_ltdc(plane); 536 u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE; 537 int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos; 538 539 switch (pix_fmt) { 540 case PF_BGR888: 541 psize = 3; 542 alen = 0; apos = 0; rlen = 8; rpos = 0; 543 glen = 8; gpos = 8; blen = 8; bpos = 16; 544 break; 545 case PF_ARGB1555: 546 psize = 2; 547 alen = 1; apos = 15; rlen = 5; rpos = 10; 548 glen = 5; gpos = 5; blen = 5; bpos = 0; 549 break; 550 case PF_ARGB4444: 551 psize = 2; 552 alen = 4; apos = 12; rlen = 4; rpos = 8; 553 glen = 4; gpos = 4; blen = 4; bpos = 0; 554 break; 555 case PF_L8: 556 psize = 1; 557 alen = 0; apos = 0; rlen = 8; rpos = 0; 558 glen = 8; gpos = 0; blen = 8; bpos = 0; 559 break; 560 case PF_AL44: 561 psize = 1; 562 alen = 4; apos = 4; rlen = 4; rpos = 0; 563 glen = 4; gpos = 0; blen = 4; bpos = 0; 564 break; 565 case PF_AL88: 566 psize = 2; 567 alen = 8; apos = 8; rlen = 8; rpos = 0; 568 glen = 8; gpos = 0; blen = 8; bpos = 0; 569 break; 570 default: 571 ret = NB_PF; /* error case, trace msg is handled by the caller */ 572 break; 573 } 574 575 if (ret == PF_FLEXIBLE) { 576 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs, 577 (rlen << 14) + (rpos << 9) + (alen << 5) + apos); 578 579 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs, 580 (psize << 18) + (blen << 14) + (bpos << 9) + (glen << 5) + gpos); 581 } 582 583 return ret; 584 } 585 586 /* 587 * All non-alpha color formats derived from native alpha color formats are 588 * either characterized by a FourCC format code 589 */ 590 static inline u32 is_xrgb(u32 drm) 591 { 592 return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X'); 593 } 594 595 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt) 596 { 597 struct ltdc_device *ldev = plane_to_ltdc(plane); 598 struct drm_plane_state *state = plane->state; 599 u32 lofs = plane->index * LAY_OFS; 600 u32 val; 601 602 switch (drm_pix_fmt) { 603 case DRM_FORMAT_YUYV: 604 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF; 605 break; 606 case DRM_FORMAT_YVYU: 607 val = (YCM_I << 4) | LxPCR_YF; 608 break; 609 case DRM_FORMAT_UYVY: 610 val = (YCM_I << 4) | LxPCR_CBF; 611 break; 612 case DRM_FORMAT_VYUY: 613 val = (YCM_I << 4); 614 break; 615 case DRM_FORMAT_NV12: 616 val = (YCM_SP << 4) | LxPCR_CBF; 617 break; 618 case DRM_FORMAT_NV21: 619 val = (YCM_SP << 4); 620 break; 621 case DRM_FORMAT_YUV420: 622 case DRM_FORMAT_YVU420: 623 val = (YCM_FP << 4); 624 break; 625 default: 626 /* RGB or not a YCbCr supported format */ 627 break; 628 } 629 630 /* Enable limited range */ 631 if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) 632 val |= LxPCR_YREN; 633 634 /* enable ycbcr conversion */ 635 val |= LxPCR_YCEN; 636 637 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val); 638 } 639 640 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane) 641 { 642 struct ltdc_device *ldev = plane_to_ltdc(plane); 643 struct drm_plane_state *state = plane->state; 644 enum drm_color_encoding enc = state->color_encoding; 645 enum drm_color_range ran = state->color_range; 646 u32 lofs = plane->index * LAY_OFS; 647 648 if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) { 649 DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc); 650 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */ 651 enc = DRM_COLOR_YCBCR_BT601; 652 } 653 654 if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) { 655 DRM_ERROR("color range %d not supported, use limited range by default\n", ran); 656 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */ 657 ran = DRM_COLOR_YCBCR_LIMITED_RANGE; 658 } 659 660 DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran); 661 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, 662 ltdc_ycbcr2rgb_coeffs[enc][ran][0]); 663 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, 664 ltdc_ycbcr2rgb_coeffs[enc][ran][1]); 665 } 666 667 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 668 { 669 struct drm_device *ddev = arg; 670 struct ltdc_device *ldev = ddev->dev_private; 671 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 672 673 /* Line IRQ : trigger the vblank event */ 674 if (ldev->irq_status & ISR_LIF) 675 drm_crtc_handle_vblank(crtc); 676 677 /* Save FIFO Underrun & Transfer Error status */ 678 mutex_lock(&ldev->err_lock); 679 if (ldev->irq_status & ISR_FUIF) 680 ldev->error_status |= ISR_FUIF; 681 if (ldev->irq_status & ISR_TERRIF) 682 ldev->error_status |= ISR_TERRIF; 683 mutex_unlock(&ldev->err_lock); 684 685 return IRQ_HANDLED; 686 } 687 688 static irqreturn_t ltdc_irq(int irq, void *arg) 689 { 690 struct drm_device *ddev = arg; 691 struct ltdc_device *ldev = ddev->dev_private; 692 693 /* 694 * Read & Clear the interrupt status 695 * In order to write / read registers in this critical section 696 * very quickly, the regmap functions are not used. 697 */ 698 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR); 699 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR); 700 701 return IRQ_WAKE_THREAD; 702 } 703 704 /* 705 * DRM_CRTC 706 */ 707 708 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 709 { 710 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 711 struct drm_color_lut *lut; 712 u32 val; 713 int i; 714 715 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 716 return; 717 718 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 719 720 for (i = 0; i < CLUT_SIZE; i++, lut++) { 721 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 722 (lut->blue >> 8) | (i << 24); 723 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val); 724 } 725 } 726 727 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 728 struct drm_atomic_state *state) 729 { 730 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 731 struct drm_device *ddev = crtc->dev; 732 733 DRM_DEBUG_DRIVER("\n"); 734 735 pm_runtime_get_sync(ddev->dev); 736 737 /* Sets the background color value */ 738 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); 739 740 /* Enable IRQ */ 741 regmap_set_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 742 743 /* Commit shadow registers = update planes at next vblank */ 744 if (!ldev->caps.plane_reg_shadow) 745 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 746 747 drm_crtc_vblank_on(crtc); 748 } 749 750 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 751 struct drm_atomic_state *state) 752 { 753 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 754 struct drm_device *ddev = crtc->dev; 755 756 DRM_DEBUG_DRIVER("\n"); 757 758 drm_crtc_vblank_off(crtc); 759 760 /* disable IRQ */ 761 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 762 763 /* immediately commit disable of layers before switching off LTDC */ 764 if (!ldev->caps.plane_reg_shadow) 765 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); 766 767 pm_runtime_put_sync(ddev->dev); 768 } 769 770 #define CLK_TOLERANCE_HZ 50 771 772 static enum drm_mode_status 773 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 774 const struct drm_display_mode *mode) 775 { 776 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 777 int target = mode->clock * 1000; 778 int target_min = target - CLK_TOLERANCE_HZ; 779 int target_max = target + CLK_TOLERANCE_HZ; 780 int result; 781 782 result = clk_round_rate(ldev->pixel_clk, target); 783 784 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 785 786 /* Filter modes according to the max frequency supported by the pads */ 787 if (result > ldev->caps.pad_max_freq_hz) 788 return MODE_CLOCK_HIGH; 789 790 /* 791 * Accept all "preferred" modes: 792 * - this is important for panels because panel clock tolerances are 793 * bigger than hdmi ones and there is no reason to not accept them 794 * (the fps may vary a little but it is not a problem). 795 * - the hdmi preferred mode will be accepted too, but userland will 796 * be able to use others hdmi "valid" modes if necessary. 797 */ 798 if (mode->type & DRM_MODE_TYPE_PREFERRED) 799 return MODE_OK; 800 801 /* 802 * Filter modes according to the clock value, particularly useful for 803 * hdmi modes that require precise pixel clocks. 804 */ 805 if (result < target_min || result > target_max) 806 return MODE_CLOCK_RANGE; 807 808 return MODE_OK; 809 } 810 811 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 812 const struct drm_display_mode *mode, 813 struct drm_display_mode *adjusted_mode) 814 { 815 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 816 int rate = mode->clock * 1000; 817 818 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 819 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 820 return false; 821 } 822 823 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 824 825 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 826 mode->clock, adjusted_mode->clock); 827 828 return true; 829 } 830 831 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 832 { 833 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 834 struct drm_device *ddev = crtc->dev; 835 struct drm_connector_list_iter iter; 836 struct drm_connector *connector = NULL; 837 struct drm_encoder *encoder = NULL; 838 struct drm_bridge *bridge = NULL; 839 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 840 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 841 u32 total_width, total_height; 842 u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24; 843 u32 bus_flags = 0; 844 u32 val; 845 int ret; 846 847 /* get encoder from crtc */ 848 drm_for_each_encoder(encoder, ddev) 849 if (encoder->crtc == crtc) 850 break; 851 852 if (encoder) { 853 /* get bridge from encoder */ 854 list_for_each_entry(bridge, &encoder->bridge_chain, chain_node) 855 if (bridge->encoder == encoder) 856 break; 857 858 /* Get the connector from encoder */ 859 drm_connector_list_iter_begin(ddev, &iter); 860 drm_for_each_connector_iter(connector, &iter) 861 if (connector->encoder == encoder) 862 break; 863 drm_connector_list_iter_end(&iter); 864 } 865 866 if (bridge && bridge->timings) 867 bus_flags = bridge->timings->input_bus_flags; 868 else if (connector) { 869 bus_flags = connector->display_info.bus_flags; 870 if (connector->display_info.num_bus_formats) 871 bus_formats = connector->display_info.bus_formats[0]; 872 } 873 874 if (!pm_runtime_active(ddev->dev)) { 875 ret = pm_runtime_get_sync(ddev->dev); 876 if (ret) { 877 DRM_ERROR("Failed to set mode, cannot get sync\n"); 878 return; 879 } 880 } 881 882 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 883 DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 884 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 885 mode->hsync_start - mode->hdisplay, 886 mode->htotal - mode->hsync_end, 887 mode->hsync_end - mode->hsync_start, 888 mode->vsync_start - mode->vdisplay, 889 mode->vtotal - mode->vsync_end, 890 mode->vsync_end - mode->vsync_start); 891 892 /* Convert video timings to ltdc timings */ 893 hsync = mode->hsync_end - mode->hsync_start - 1; 894 vsync = mode->vsync_end - mode->vsync_start - 1; 895 accum_hbp = mode->htotal - mode->hsync_start - 1; 896 accum_vbp = mode->vtotal - mode->vsync_start - 1; 897 accum_act_w = accum_hbp + mode->hdisplay; 898 accum_act_h = accum_vbp + mode->vdisplay; 899 total_width = mode->htotal - 1; 900 total_height = mode->vtotal - 1; 901 902 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 903 val = 0; 904 905 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 906 val |= GCR_HSPOL; 907 908 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 909 val |= GCR_VSPOL; 910 911 if (bus_flags & DRM_BUS_FLAG_DE_LOW) 912 val |= GCR_DEPOL; 913 914 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 915 val |= GCR_PCPOL; 916 917 regmap_update_bits(ldev->regmap, LTDC_GCR, 918 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 919 920 /* Set Synchronization size */ 921 val = (hsync << 16) | vsync; 922 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 923 924 /* Set Accumulated Back porch */ 925 val = (accum_hbp << 16) | accum_vbp; 926 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 927 928 /* Set Accumulated Active Width */ 929 val = (accum_act_w << 16) | accum_act_h; 930 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 931 932 /* Set total width & height */ 933 val = (total_width << 16) | total_height; 934 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 935 936 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1)); 937 938 /* Configure the output format (hw version dependent) */ 939 if (ldev->caps.ycbcr_output) { 940 /* Input video dynamic_range & colorimetry */ 941 int vic = drm_match_cea_mode(mode); 942 u32 val; 943 944 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 || 945 vic == 2 || vic == 3 || vic == 17 || vic == 18) 946 /* ITU-R BT.601 */ 947 val = 0; 948 else 949 /* ITU-R BT.709 */ 950 val = EDCR_OCYSEL; 951 952 switch (bus_formats) { 953 case MEDIA_BUS_FMT_YUYV8_1X16: 954 /* enable ycbcr output converter */ 955 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val); 956 break; 957 case MEDIA_BUS_FMT_YVYU8_1X16: 958 /* enable ycbcr output converter & invert chrominance order */ 959 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val); 960 break; 961 default: 962 /* disable ycbcr output converter */ 963 regmap_write(ldev->regmap, LTDC_EDCR, 0); 964 break; 965 } 966 } 967 } 968 969 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 970 struct drm_atomic_state *state) 971 { 972 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 973 struct drm_device *ddev = crtc->dev; 974 struct drm_pending_vblank_event *event = crtc->state->event; 975 976 DRM_DEBUG_ATOMIC("\n"); 977 978 ltdc_crtc_update_clut(crtc); 979 980 /* Commit shadow registers = update planes at next vblank */ 981 if (!ldev->caps.plane_reg_shadow) 982 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 983 984 if (event) { 985 crtc->state->event = NULL; 986 987 spin_lock_irq(&ddev->event_lock); 988 if (drm_crtc_vblank_get(crtc) == 0) 989 drm_crtc_arm_vblank_event(crtc, event); 990 else 991 drm_crtc_send_vblank_event(crtc, event); 992 spin_unlock_irq(&ddev->event_lock); 993 } 994 } 995 996 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 997 bool in_vblank_irq, 998 int *vpos, int *hpos, 999 ktime_t *stime, ktime_t *etime, 1000 const struct drm_display_mode *mode) 1001 { 1002 struct drm_device *ddev = crtc->dev; 1003 struct ltdc_device *ldev = ddev->dev_private; 1004 int line, vactive_start, vactive_end, vtotal; 1005 1006 if (stime) 1007 *stime = ktime_get(); 1008 1009 /* The active area starts after vsync + front porch and ends 1010 * at vsync + front porc + display size. 1011 * The total height also include back porch. 1012 * We have 3 possible cases to handle: 1013 * - line < vactive_start: vpos = line - vactive_start and will be 1014 * negative 1015 * - vactive_start < line < vactive_end: vpos = line - vactive_start 1016 * and will be positive 1017 * - line > vactive_end: vpos = line - vtotal - vactive_start 1018 * and will negative 1019 * 1020 * Computation for the two first cases are identical so we can 1021 * simplify the code and only test if line > vactive_end 1022 */ 1023 if (pm_runtime_active(ddev->dev)) { 1024 regmap_read(ldev->regmap, LTDC_CPSR, &line); 1025 line &= CPSR_CYPOS; 1026 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start); 1027 vactive_start &= BPCR_AVBP; 1028 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end); 1029 vactive_end &= AWCR_AAH; 1030 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal); 1031 vtotal &= TWCR_TOTALH; 1032 1033 if (line > vactive_end) 1034 *vpos = line - vtotal - vactive_start; 1035 else 1036 *vpos = line - vactive_start; 1037 } else { 1038 *vpos = 0; 1039 } 1040 1041 *hpos = 0; 1042 1043 if (etime) 1044 *etime = ktime_get(); 1045 1046 return true; 1047 } 1048 1049 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 1050 .mode_valid = ltdc_crtc_mode_valid, 1051 .mode_fixup = ltdc_crtc_mode_fixup, 1052 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 1053 .atomic_flush = ltdc_crtc_atomic_flush, 1054 .atomic_enable = ltdc_crtc_atomic_enable, 1055 .atomic_disable = ltdc_crtc_atomic_disable, 1056 .get_scanout_position = ltdc_crtc_get_scanout_position, 1057 }; 1058 1059 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 1060 { 1061 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1062 struct drm_crtc_state *state = crtc->state; 1063 1064 DRM_DEBUG_DRIVER("\n"); 1065 1066 if (state->enable) 1067 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); 1068 else 1069 return -EPERM; 1070 1071 return 0; 1072 } 1073 1074 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 1075 { 1076 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1077 1078 DRM_DEBUG_DRIVER("\n"); 1079 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); 1080 } 1081 1082 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 1083 .destroy = drm_crtc_cleanup, 1084 .set_config = drm_atomic_helper_set_config, 1085 .page_flip = drm_atomic_helper_page_flip, 1086 .reset = drm_atomic_helper_crtc_reset, 1087 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1088 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1089 .enable_vblank = ltdc_crtc_enable_vblank, 1090 .disable_vblank = ltdc_crtc_disable_vblank, 1091 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1092 }; 1093 1094 /* 1095 * DRM_PLANE 1096 */ 1097 1098 static int ltdc_plane_atomic_check(struct drm_plane *plane, 1099 struct drm_atomic_state *state) 1100 { 1101 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1102 plane); 1103 struct drm_framebuffer *fb = new_plane_state->fb; 1104 u32 src_w, src_h; 1105 1106 DRM_DEBUG_DRIVER("\n"); 1107 1108 if (!fb) 1109 return 0; 1110 1111 /* convert src_ from 16:16 format */ 1112 src_w = new_plane_state->src_w >> 16; 1113 src_h = new_plane_state->src_h >> 16; 1114 1115 /* Reject scaling */ 1116 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 1117 DRM_ERROR("Scaling is not supported"); 1118 return -EINVAL; 1119 } 1120 1121 return 0; 1122 } 1123 1124 static void ltdc_plane_atomic_update(struct drm_plane *plane, 1125 struct drm_atomic_state *state) 1126 { 1127 struct ltdc_device *ldev = plane_to_ltdc(plane); 1128 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 1129 plane); 1130 struct drm_framebuffer *fb = newstate->fb; 1131 u32 lofs = plane->index * LAY_OFS; 1132 u32 x0 = newstate->crtc_x; 1133 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; 1134 u32 y0 = newstate->crtc_y; 1135 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; 1136 u32 src_x, src_y, src_w, src_h; 1137 u32 val, pitch_in_bytes, line_length, line_number, paddr, ahbp, avbp, bpcr; 1138 enum ltdc_pix_fmt pf; 1139 1140 if (!newstate->crtc || !fb) { 1141 DRM_DEBUG_DRIVER("fb or crtc NULL"); 1142 return; 1143 } 1144 1145 /* convert src_ from 16:16 format */ 1146 src_x = newstate->src_x >> 16; 1147 src_y = newstate->src_y >> 16; 1148 src_w = newstate->src_w >> 16; 1149 src_h = newstate->src_h >> 16; 1150 1151 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 1152 plane->base.id, fb->base.id, 1153 src_w, src_h, src_x, src_y, 1154 newstate->crtc_w, newstate->crtc_h, 1155 newstate->crtc_x, newstate->crtc_y); 1156 1157 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); 1158 1159 ahbp = (bpcr & BPCR_AHBP) >> 16; 1160 avbp = bpcr & BPCR_AVBP; 1161 1162 /* Configures the horizontal start and stop position */ 1163 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 1164 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs, 1165 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 1166 1167 /* Configures the vertical start and stop position */ 1168 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 1169 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs, 1170 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 1171 1172 /* Specifies the pixel format */ 1173 pf = to_ltdc_pixelformat(fb->format->format); 1174 for (val = 0; val < NB_PF; val++) 1175 if (ldev->caps.pix_fmt_hw[val] == pf) 1176 break; 1177 1178 /* Use the flexible color format feature if necessary and available */ 1179 if (ldev->caps.pix_fmt_flex && val == NB_PF) 1180 val = ltdc_set_flexible_pixel_format(plane, pf); 1181 1182 if (val == NB_PF) { 1183 DRM_ERROR("Pixel format %.4s not supported\n", 1184 (char *)&fb->format->format); 1185 val = 0; /* set by default ARGB 32 bits */ 1186 } 1187 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 1188 1189 /* Configures the color frame buffer pitch in bytes & line length */ 1190 pitch_in_bytes = fb->pitches[0]; 1191 line_length = fb->format->cpp[0] * 1192 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 1193 val = ((pitch_in_bytes << 16) | line_length); 1194 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 1195 1196 /* Specifies the constant alpha value */ 1197 val = newstate->alpha >> 8; 1198 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 1199 1200 /* Specifies the blending factors */ 1201 val = BF1_PAXCA | BF2_1PAXCA; 1202 if (!fb->format->has_alpha) 1203 val = BF1_CA | BF2_1CA; 1204 1205 /* Manage hw-specific capabilities */ 1206 if (ldev->caps.non_alpha_only_l1 && 1207 plane->type != DRM_PLANE_TYPE_PRIMARY) 1208 val = BF1_PAXCA | BF2_1PAXCA; 1209 1210 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, LXBFCR_BF2 | LXBFCR_BF1, val); 1211 1212 /* Configures the frame buffer line number */ 1213 line_number = y1 - y0 + 1; 1214 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); 1215 1216 /* Sets the FB address */ 1217 paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 0); 1218 1219 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 1220 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); 1221 1222 if (ldev->caps.ycbcr_input) { 1223 if (fb->format->is_yuv) { 1224 switch (fb->format->format) { 1225 case DRM_FORMAT_NV12: 1226 case DRM_FORMAT_NV21: 1227 /* Configure the auxiliary frame buffer address 0 & 1 */ 1228 paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); 1229 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr); 1230 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr + 1); 1231 1232 /* Configure the buffer length */ 1233 val = ((pitch_in_bytes << 16) | line_length); 1234 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); 1235 1236 /* Configure the frame buffer line number */ 1237 val = (line_number >> 1); 1238 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); 1239 break; 1240 case DRM_FORMAT_YUV420: 1241 /* Configure the auxiliary frame buffer address 0 */ 1242 paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); 1243 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr); 1244 1245 /* Configure the auxiliary frame buffer address 1 */ 1246 paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2); 1247 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr); 1248 1249 line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) + 1250 (ldev->caps.bus_width >> 3) - 1; 1251 1252 /* Configure the buffer length */ 1253 val = (((pitch_in_bytes >> 1) << 16) | line_length); 1254 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); 1255 1256 /* Configure the frame buffer line number */ 1257 val = (line_number >> 1); 1258 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); 1259 break; 1260 case DRM_FORMAT_YVU420: 1261 /* Configure the auxiliary frame buffer address 0 */ 1262 paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2); 1263 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr); 1264 1265 /* Configure the auxiliary frame buffer address 1 */ 1266 paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1); 1267 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr); 1268 1269 line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) + 1270 (ldev->caps.bus_width >> 3) - 1; 1271 1272 /* Configure the buffer length */ 1273 val = (((pitch_in_bytes >> 1) << 16) | line_length); 1274 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); 1275 1276 /* Configure the frame buffer line number */ 1277 val = (line_number >> 1); 1278 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); 1279 break; 1280 } 1281 1282 /* Configure YCbC conversion coefficient */ 1283 ltdc_set_ycbcr_coeffs(plane); 1284 1285 /* Configure YCbCr format and enable/disable conversion */ 1286 ltdc_set_ycbcr_config(plane, fb->format->format); 1287 } else { 1288 /* disable ycbcr conversion */ 1289 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0); 1290 } 1291 } 1292 1293 /* Enable layer and CLUT if needed */ 1294 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 1295 val |= LXCR_LEN; 1296 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN, val); 1297 1298 /* Commit shadow registers = update plane at next vblank */ 1299 if (ldev->caps.plane_reg_shadow) 1300 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1301 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1302 1303 ldev->plane_fpsi[plane->index].counter++; 1304 1305 mutex_lock(&ldev->err_lock); 1306 if (ldev->error_status & ISR_FUIF) { 1307 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1308 ldev->error_status &= ~ISR_FUIF; 1309 } 1310 if (ldev->error_status & ISR_TERRIF) { 1311 DRM_WARN("ltdc transfer error\n"); 1312 ldev->error_status &= ~ISR_TERRIF; 1313 } 1314 mutex_unlock(&ldev->err_lock); 1315 } 1316 1317 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 1318 struct drm_atomic_state *state) 1319 { 1320 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 1321 plane); 1322 struct ltdc_device *ldev = plane_to_ltdc(plane); 1323 u32 lofs = plane->index * LAY_OFS; 1324 1325 /* disable layer */ 1326 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN, 0); 1327 1328 /* Commit shadow registers = update plane at next vblank */ 1329 if (ldev->caps.plane_reg_shadow) 1330 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1331 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1332 1333 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 1334 oldstate->crtc->base.id, plane->base.id); 1335 } 1336 1337 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 1338 const struct drm_plane_state *state) 1339 { 1340 struct drm_plane *plane = state->plane; 1341 struct ltdc_device *ldev = plane_to_ltdc(plane); 1342 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 1343 int ms_since_last; 1344 ktime_t now; 1345 1346 now = ktime_get(); 1347 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 1348 1349 drm_printf(p, "\tuser_updates=%dfps\n", 1350 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 1351 1352 fpsi->last_timestamp = now; 1353 fpsi->counter = 0; 1354 } 1355 1356 static const struct drm_plane_funcs ltdc_plane_funcs = { 1357 .update_plane = drm_atomic_helper_update_plane, 1358 .disable_plane = drm_atomic_helper_disable_plane, 1359 .destroy = drm_plane_cleanup, 1360 .reset = drm_atomic_helper_plane_reset, 1361 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1362 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1363 .atomic_print_state = ltdc_plane_atomic_print_state, 1364 }; 1365 1366 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 1367 .atomic_check = ltdc_plane_atomic_check, 1368 .atomic_update = ltdc_plane_atomic_update, 1369 .atomic_disable = ltdc_plane_atomic_disable, 1370 }; 1371 1372 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 1373 enum drm_plane_type type, 1374 int index) 1375 { 1376 unsigned long possible_crtcs = CRTC_MASK; 1377 struct ltdc_device *ldev = ddev->dev_private; 1378 struct device *dev = ddev->dev; 1379 struct drm_plane *plane; 1380 unsigned int i, nb_fmt = 0; 1381 u32 *formats; 1382 u32 drm_fmt; 1383 const u64 *modifiers = ltdc_format_modifiers; 1384 u32 lofs = index * LAY_OFS; 1385 u32 val; 1386 int ret; 1387 1388 /* Allocate the biggest size according to supported color formats */ 1389 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb + 1390 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) + 1391 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) + 1392 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) * 1393 sizeof(*formats), GFP_KERNEL); 1394 1395 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) { 1396 drm_fmt = ldev->caps.pix_fmt_drm[i]; 1397 1398 /* Manage hw-specific capabilities */ 1399 if (ldev->caps.non_alpha_only_l1) 1400 /* XR24 & RX24 like formats supported only on primary layer */ 1401 if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt)) 1402 continue; 1403 1404 formats[nb_fmt++] = drm_fmt; 1405 } 1406 1407 /* Add YCbCr supported pixel formats */ 1408 if (ldev->caps.ycbcr_input) { 1409 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val); 1410 if (val & LXCR_C1R_YIA) { 1411 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp, 1412 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats)); 1413 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp); 1414 } 1415 if (val & LXCR_C1R_YSPA) { 1416 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp, 1417 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats)); 1418 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp); 1419 } 1420 if (val & LXCR_C1R_YFPA) { 1421 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp, 1422 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats)); 1423 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp); 1424 } 1425 } 1426 1427 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 1428 if (!plane) 1429 return NULL; 1430 1431 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 1432 <dc_plane_funcs, formats, nb_fmt, 1433 modifiers, type, NULL); 1434 if (ret < 0) 1435 return NULL; 1436 1437 if (ldev->caps.ycbcr_input) { 1438 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA)) 1439 drm_plane_create_color_properties(plane, 1440 BIT(DRM_COLOR_YCBCR_BT601) | 1441 BIT(DRM_COLOR_YCBCR_BT709), 1442 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1443 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1444 DRM_COLOR_YCBCR_BT601, 1445 DRM_COLOR_YCBCR_LIMITED_RANGE); 1446 } 1447 1448 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 1449 1450 drm_plane_create_alpha_property(plane); 1451 1452 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 1453 1454 return plane; 1455 } 1456 1457 static void ltdc_plane_destroy_all(struct drm_device *ddev) 1458 { 1459 struct drm_plane *plane, *plane_temp; 1460 1461 list_for_each_entry_safe(plane, plane_temp, 1462 &ddev->mode_config.plane_list, head) 1463 drm_plane_cleanup(plane); 1464 } 1465 1466 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 1467 { 1468 struct ltdc_device *ldev = ddev->dev_private; 1469 struct drm_plane *primary, *overlay; 1470 unsigned int i; 1471 int ret; 1472 1473 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); 1474 if (!primary) { 1475 DRM_ERROR("Can not create primary plane\n"); 1476 return -EINVAL; 1477 } 1478 1479 drm_plane_create_zpos_immutable_property(primary, 0); 1480 1481 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1482 <dc_crtc_funcs, NULL); 1483 if (ret) { 1484 DRM_ERROR("Can not initialize CRTC\n"); 1485 goto cleanup; 1486 } 1487 1488 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1489 1490 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1491 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1492 1493 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1494 1495 /* Add planes. Note : the first layer is used by primary plane */ 1496 for (i = 1; i < ldev->caps.nb_layers; i++) { 1497 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i); 1498 if (!overlay) { 1499 ret = -ENOMEM; 1500 DRM_ERROR("Can not create overlay plane %d\n", i); 1501 goto cleanup; 1502 } 1503 drm_plane_create_zpos_immutable_property(overlay, i); 1504 } 1505 1506 return 0; 1507 1508 cleanup: 1509 ltdc_plane_destroy_all(ddev); 1510 return ret; 1511 } 1512 1513 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1514 { 1515 struct drm_device *ddev = encoder->dev; 1516 struct ltdc_device *ldev = ddev->dev_private; 1517 1518 DRM_DEBUG_DRIVER("\n"); 1519 1520 /* Disable LTDC */ 1521 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1522 1523 /* Set to sleep state the pinctrl whatever type of encoder */ 1524 pinctrl_pm_select_sleep_state(ddev->dev); 1525 } 1526 1527 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1528 { 1529 struct drm_device *ddev = encoder->dev; 1530 struct ltdc_device *ldev = ddev->dev_private; 1531 1532 DRM_DEBUG_DRIVER("\n"); 1533 1534 /* Enable LTDC */ 1535 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1536 } 1537 1538 static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1539 struct drm_display_mode *mode, 1540 struct drm_display_mode *adjusted_mode) 1541 { 1542 struct drm_device *ddev = encoder->dev; 1543 1544 DRM_DEBUG_DRIVER("\n"); 1545 1546 /* 1547 * Set to default state the pinctrl only with DPI type. 1548 * Others types like DSI, don't need pinctrl due to 1549 * internal bridge (the signals do not come out of the chipset). 1550 */ 1551 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1552 pinctrl_pm_select_default_state(ddev->dev); 1553 } 1554 1555 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1556 .disable = ltdc_encoder_disable, 1557 .enable = ltdc_encoder_enable, 1558 .mode_set = ltdc_encoder_mode_set, 1559 }; 1560 1561 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1562 { 1563 struct drm_encoder *encoder; 1564 int ret; 1565 1566 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1567 if (!encoder) 1568 return -ENOMEM; 1569 1570 encoder->possible_crtcs = CRTC_MASK; 1571 encoder->possible_clones = 0; /* No cloning support */ 1572 1573 drm_simple_encoder_init(ddev, encoder, DRM_MODE_ENCODER_DPI); 1574 1575 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1576 1577 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1578 if (ret) { 1579 if (ret != -EPROBE_DEFER) 1580 drm_encoder_cleanup(encoder); 1581 return ret; 1582 } 1583 1584 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1585 1586 return 0; 1587 } 1588 1589 static int ltdc_get_caps(struct drm_device *ddev) 1590 { 1591 struct ltdc_device *ldev = ddev->dev_private; 1592 u32 bus_width_log2, lcr, gc2r; 1593 1594 /* 1595 * at least 1 layer must be managed & the number of layers 1596 * must not exceed LTDC_MAX_LAYER 1597 */ 1598 regmap_read(ldev->regmap, LTDC_LCR, &lcr); 1599 1600 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1601 1602 /* set data bus width */ 1603 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r); 1604 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1605 ldev->caps.bus_width = 8 << bus_width_log2; 1606 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); 1607 1608 switch (ldev->caps.hw_version) { 1609 case HWVER_10200: 1610 case HWVER_10300: 1611 ldev->caps.layer_ofs = LAY_OFS_0; 1612 ldev->caps.layer_regs = ltdc_layer_regs_a0; 1613 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1614 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0; 1615 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0); 1616 ldev->caps.pix_fmt_flex = false; 1617 /* 1618 * Hw older versions support non-alpha color formats derived 1619 * from native alpha color formats only on the primary layer. 1620 * For instance, RG16 native format without alpha works fine 1621 * on 2nd layer but XR24 (derived color format from AR24) 1622 * does not work on 2nd layer. 1623 */ 1624 ldev->caps.non_alpha_only_l1 = true; 1625 ldev->caps.pad_max_freq_hz = 90000000; 1626 if (ldev->caps.hw_version == HWVER_10200) 1627 ldev->caps.pad_max_freq_hz = 65000000; 1628 ldev->caps.nb_irq = 2; 1629 ldev->caps.ycbcr_input = false; 1630 ldev->caps.ycbcr_output = false; 1631 ldev->caps.plane_reg_shadow = false; 1632 break; 1633 case HWVER_20101: 1634 ldev->caps.layer_ofs = LAY_OFS_0; 1635 ldev->caps.layer_regs = ltdc_layer_regs_a1; 1636 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1637 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1; 1638 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1); 1639 ldev->caps.pix_fmt_flex = false; 1640 ldev->caps.non_alpha_only_l1 = false; 1641 ldev->caps.pad_max_freq_hz = 150000000; 1642 ldev->caps.nb_irq = 4; 1643 ldev->caps.ycbcr_input = false; 1644 ldev->caps.ycbcr_output = false; 1645 ldev->caps.plane_reg_shadow = false; 1646 break; 1647 case HWVER_40100: 1648 ldev->caps.layer_ofs = LAY_OFS_1; 1649 ldev->caps.layer_regs = ltdc_layer_regs_a2; 1650 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; 1651 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2; 1652 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2); 1653 ldev->caps.pix_fmt_flex = true; 1654 ldev->caps.non_alpha_only_l1 = false; 1655 ldev->caps.pad_max_freq_hz = 90000000; 1656 ldev->caps.nb_irq = 2; 1657 ldev->caps.ycbcr_input = true; 1658 ldev->caps.ycbcr_output = true; 1659 ldev->caps.plane_reg_shadow = true; 1660 break; 1661 default: 1662 return -ENODEV; 1663 } 1664 1665 return 0; 1666 } 1667 1668 void ltdc_suspend(struct drm_device *ddev) 1669 { 1670 struct ltdc_device *ldev = ddev->dev_private; 1671 1672 DRM_DEBUG_DRIVER("\n"); 1673 clk_disable_unprepare(ldev->pixel_clk); 1674 } 1675 1676 int ltdc_resume(struct drm_device *ddev) 1677 { 1678 struct ltdc_device *ldev = ddev->dev_private; 1679 int ret; 1680 1681 DRM_DEBUG_DRIVER("\n"); 1682 1683 ret = clk_prepare_enable(ldev->pixel_clk); 1684 if (ret) { 1685 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1686 return ret; 1687 } 1688 1689 return 0; 1690 } 1691 1692 int ltdc_load(struct drm_device *ddev) 1693 { 1694 struct platform_device *pdev = to_platform_device(ddev->dev); 1695 struct ltdc_device *ldev = ddev->dev_private; 1696 struct device *dev = ddev->dev; 1697 struct device_node *np = dev->of_node; 1698 struct drm_bridge *bridge; 1699 struct drm_panel *panel; 1700 struct drm_crtc *crtc; 1701 struct reset_control *rstc; 1702 struct resource *res; 1703 int irq, i, nb_endpoints; 1704 int ret = -ENODEV; 1705 1706 DRM_DEBUG_DRIVER("\n"); 1707 1708 /* Get number of endpoints */ 1709 nb_endpoints = of_graph_get_endpoint_count(np); 1710 if (!nb_endpoints) 1711 return -ENODEV; 1712 1713 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1714 if (IS_ERR(ldev->pixel_clk)) { 1715 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1716 DRM_ERROR("Unable to get lcd clock\n"); 1717 return PTR_ERR(ldev->pixel_clk); 1718 } 1719 1720 if (clk_prepare_enable(ldev->pixel_clk)) { 1721 DRM_ERROR("Unable to prepare pixel clock\n"); 1722 return -ENODEV; 1723 } 1724 1725 /* Get endpoints if any */ 1726 for (i = 0; i < nb_endpoints; i++) { 1727 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1728 1729 /* 1730 * If at least one endpoint is -ENODEV, continue probing, 1731 * else if at least one endpoint returned an error 1732 * (ie -EPROBE_DEFER) then stop probing. 1733 */ 1734 if (ret == -ENODEV) 1735 continue; 1736 else if (ret) 1737 goto err; 1738 1739 if (panel) { 1740 bridge = drm_panel_bridge_add_typed(panel, 1741 DRM_MODE_CONNECTOR_DPI); 1742 if (IS_ERR(bridge)) { 1743 DRM_ERROR("panel-bridge endpoint %d\n", i); 1744 ret = PTR_ERR(bridge); 1745 goto err; 1746 } 1747 } 1748 1749 if (bridge) { 1750 ret = ltdc_encoder_init(ddev, bridge); 1751 if (ret) { 1752 if (ret != -EPROBE_DEFER) 1753 DRM_ERROR("init encoder endpoint %d\n", i); 1754 goto err; 1755 } 1756 } 1757 } 1758 1759 rstc = devm_reset_control_get_exclusive(dev, NULL); 1760 1761 mutex_init(&ldev->err_lock); 1762 1763 if (!IS_ERR(rstc)) { 1764 reset_control_assert(rstc); 1765 usleep_range(10, 20); 1766 reset_control_deassert(rstc); 1767 } 1768 1769 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1770 ldev->regs = devm_ioremap_resource(dev, res); 1771 if (IS_ERR(ldev->regs)) { 1772 DRM_ERROR("Unable to get ltdc registers\n"); 1773 ret = PTR_ERR(ldev->regs); 1774 goto err; 1775 } 1776 1777 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); 1778 if (IS_ERR(ldev->regmap)) { 1779 DRM_ERROR("Unable to regmap ltdc registers\n"); 1780 ret = PTR_ERR(ldev->regmap); 1781 goto err; 1782 } 1783 1784 /* Disable interrupts */ 1785 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1786 1787 ret = ltdc_get_caps(ddev); 1788 if (ret) { 1789 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1790 ldev->caps.hw_version); 1791 goto err; 1792 } 1793 1794 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1795 1796 for (i = 0; i < ldev->caps.nb_irq; i++) { 1797 irq = platform_get_irq(pdev, i); 1798 if (irq < 0) { 1799 ret = irq; 1800 goto err; 1801 } 1802 1803 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1804 ltdc_irq_thread, IRQF_ONESHOT, 1805 dev_name(dev), ddev); 1806 if (ret) { 1807 DRM_ERROR("Failed to register LTDC interrupt\n"); 1808 goto err; 1809 } 1810 1811 } 1812 1813 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1814 if (!crtc) { 1815 DRM_ERROR("Failed to allocate crtc\n"); 1816 ret = -ENOMEM; 1817 goto err; 1818 } 1819 1820 ret = ltdc_crtc_init(ddev, crtc); 1821 if (ret) { 1822 DRM_ERROR("Failed to init crtc\n"); 1823 goto err; 1824 } 1825 1826 ret = drm_vblank_init(ddev, NB_CRTC); 1827 if (ret) { 1828 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1829 goto err; 1830 } 1831 1832 clk_disable_unprepare(ldev->pixel_clk); 1833 1834 pinctrl_pm_select_sleep_state(ddev->dev); 1835 1836 pm_runtime_enable(ddev->dev); 1837 1838 return 0; 1839 err: 1840 for (i = 0; i < nb_endpoints; i++) 1841 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1842 1843 clk_disable_unprepare(ldev->pixel_clk); 1844 1845 return ret; 1846 } 1847 1848 void ltdc_unload(struct drm_device *ddev) 1849 { 1850 struct device *dev = ddev->dev; 1851 int nb_endpoints, i; 1852 1853 DRM_DEBUG_DRIVER("\n"); 1854 1855 nb_endpoints = of_graph_get_endpoint_count(dev->of_node); 1856 1857 for (i = 0; i < nb_endpoints; i++) 1858 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1859 1860 pm_runtime_disable(ddev->dev); 1861 } 1862 1863 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1864 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1865 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1866 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1867 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1868 MODULE_LICENSE("GPL v2"); 1869