1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/media-bus-format.h> 16 #include <linux/module.h> 17 #include <linux/of_graph.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 24 #include <drm/drm_atomic.h> 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_blend.h> 27 #include <drm/drm_bridge.h> 28 #include <drm/drm_device.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_fb_dma_helper.h> 31 #include <drm/drm_fourcc.h> 32 #include <drm/drm_framebuffer.h> 33 #include <drm/drm_gem_atomic_helper.h> 34 #include <drm/drm_gem_dma_helper.h> 35 #include <drm/drm_of.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_vblank.h> 39 #include <drm/drm_managed.h> 40 41 #include <video/videomode.h> 42 43 #include "ltdc.h" 44 45 #define NB_CRTC 1 46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 47 48 #define MAX_IRQ 4 49 50 #define HWVER_10200 0x010200 51 #define HWVER_10300 0x010300 52 #define HWVER_20101 0x020101 53 #define HWVER_40100 0x040100 54 55 /* 56 * The address of some registers depends on the HW version: such registers have 57 * an extra offset specified with layer_ofs. 58 */ 59 #define LAY_OFS_0 0x80 60 #define LAY_OFS_1 0x100 61 #define LAY_OFS (ldev->caps.layer_ofs) 62 63 /* Global register offsets */ 64 #define LTDC_IDR 0x0000 /* IDentification */ 65 #define LTDC_LCR 0x0004 /* Layer Count */ 66 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 67 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 68 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 69 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 70 #define LTDC_GCR 0x0018 /* Global Control */ 71 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 72 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 73 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 74 #define LTDC_GACR 0x0028 /* GAmma Correction */ 75 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 76 #define LTDC_IER 0x0034 /* Interrupt Enable */ 77 #define LTDC_ISR 0x0038 /* Interrupt Status */ 78 #define LTDC_ICR 0x003C /* Interrupt Clear */ 79 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 80 #define LTDC_CPSR 0x0044 /* Current Position Status */ 81 #define LTDC_CDSR 0x0048 /* Current Display Status */ 82 #define LTDC_EDCR 0x0060 /* External Display Control */ 83 #define LTDC_CCRCR 0x007C /* Computed CRC value */ 84 #define LTDC_FUT 0x0090 /* Fifo underrun Threshold */ 85 86 /* Layer register offsets */ 87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */ 88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */ 89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */ 90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */ 91 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */ 92 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */ 93 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */ 94 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */ 95 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */ 96 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */ 97 #define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */ 98 #define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */ 99 #define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */ 100 #define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */ 101 #define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */ 102 #define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */ 103 #define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ 104 #define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ 105 #define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */ 106 #define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */ 107 #define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */ 108 #define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */ 109 #define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */ 110 #define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */ 111 #define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */ 112 113 /* Bit definitions */ 114 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 115 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 116 117 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 118 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 119 120 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 121 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 122 123 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 124 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 125 126 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 127 #define GCR_DEN BIT(16) /* Dither ENable */ 128 #define GCR_CRCEN BIT(19) /* CRC ENable */ 129 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 130 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 131 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 132 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 133 134 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 135 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 136 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 137 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 138 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 139 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 140 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 141 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 142 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 143 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 144 #define GC1R_TP BIT(25) /* Timing Programmable */ 145 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 146 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 147 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 148 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 149 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 150 151 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 152 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 153 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 154 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 155 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 156 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 157 158 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 159 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 160 161 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 162 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 163 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 164 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 165 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 166 167 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 168 #define IER_FUWIE BIT(1) /* Fifo Underrun Warning Interrupt Enable */ 169 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 170 #define IER_RRIE BIT(3) /* Register Reload Interrupt Enable */ 171 #define IER_FUEIE BIT(6) /* Fifo Underrun Error Interrupt Enable */ 172 #define IER_CRCIE BIT(7) /* CRC Error Interrupt Enable */ 173 174 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 175 176 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 177 #define ISR_FUWIF BIT(1) /* Fifo Underrun Warning Interrupt Flag */ 178 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 179 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 180 #define ISR_FUEIF BIT(6) /* Fifo Underrun Error Interrupt Flag */ 181 #define ISR_CRCIF BIT(7) /* CRC Error Interrupt Flag */ 182 183 #define EDCR_OCYEN BIT(25) /* Output Conversion to YCbCr 422: ENable */ 184 #define EDCR_OCYSEL BIT(26) /* Output Conversion to YCbCr 422: SELection of the CCIR */ 185 #define EDCR_OCYCO BIT(27) /* Output Conversion to YCbCr 422: Chrominance Order */ 186 187 #define LXCR_LEN BIT(0) /* Layer ENable */ 188 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 189 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 190 #define LXCR_HMEN BIT(8) /* Horizontal Mirroring ENable */ 191 192 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 193 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 194 195 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 196 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 197 198 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 199 #define PF_FLEXIBLE 0x7 /* Flexible Pixel Format selected */ 200 201 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 202 203 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 204 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 205 #define LXBFCR_BOR GENMASK(18, 16) /* Blending ORder */ 206 207 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 208 #define LXCFBLR_CFBP GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */ 209 210 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 211 212 #define LXCR_C1R_YIA BIT(0) /* Ycbcr 422 Interleaved Ability */ 213 #define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */ 214 #define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */ 215 #define LXCR_C1R_SCA BIT(31) /* SCaling Ability*/ 216 217 #define LxPCR_YREN BIT(9) /* Y Rescale Enable for the color dynamic range */ 218 #define LxPCR_OF BIT(8) /* Odd pixel First */ 219 #define LxPCR_CBF BIT(7) /* CB component First */ 220 #define LxPCR_YF BIT(6) /* Y component First */ 221 #define LxPCR_YCM GENMASK(5, 4) /* Ycbcr Conversion Mode */ 222 #define YCM_I 0x0 /* Interleaved 422 */ 223 #define YCM_SP 0x1 /* Semi-Planar 420 */ 224 #define YCM_FP 0x2 /* Full-Planar 420 */ 225 #define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */ 226 227 #define LXRCR_IMR BIT(0) /* IMmediate Reload */ 228 #define LXRCR_VBR BIT(1) /* Vertical Blanking Reload */ 229 #define LXRCR_GRMSK BIT(2) /* Global (centralized) Reload MaSKed */ 230 231 #define CLUT_SIZE 256 232 233 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 234 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 235 #define BF1_CA 0x400 /* Constant Alpha */ 236 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 237 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 238 239 #define NB_PF 8 /* Max nb of HW pixel format */ 240 241 #define FUT_DFT 128 /* Default value of fifo underrun threshold */ 242 243 /* 244 * Skip the first value and the second in case CRC was enabled during 245 * the thread irq. This is to be sure CRC value is relevant for the 246 * frame. 247 */ 248 #define CRC_SKIP_FRAMES 2 249 250 enum ltdc_pix_fmt { 251 PF_NONE, 252 /* RGB formats */ 253 PF_ARGB8888, /* ARGB [32 bits] */ 254 PF_RGBA8888, /* RGBA [32 bits] */ 255 PF_ABGR8888, /* ABGR [32 bits] */ 256 PF_BGRA8888, /* BGRA [32 bits] */ 257 PF_RGB888, /* RGB [24 bits] */ 258 PF_BGR888, /* BGR [24 bits] */ 259 PF_RGB565, /* RGB [16 bits] */ 260 PF_BGR565, /* BGR [16 bits] */ 261 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 262 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 263 /* Indexed formats */ 264 PF_L8, /* Indexed 8 bits [8 bits] */ 265 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 266 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 267 }; 268 269 /* The index gives the encoding of the pixel format for an HW version */ 270 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 271 PF_ARGB8888, /* 0x00 */ 272 PF_RGB888, /* 0x01 */ 273 PF_RGB565, /* 0x02 */ 274 PF_ARGB1555, /* 0x03 */ 275 PF_ARGB4444, /* 0x04 */ 276 PF_L8, /* 0x05 */ 277 PF_AL44, /* 0x06 */ 278 PF_AL88 /* 0x07 */ 279 }; 280 281 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 282 PF_ARGB8888, /* 0x00 */ 283 PF_RGB888, /* 0x01 */ 284 PF_RGB565, /* 0x02 */ 285 PF_RGBA8888, /* 0x03 */ 286 PF_AL44, /* 0x04 */ 287 PF_L8, /* 0x05 */ 288 PF_ARGB1555, /* 0x06 */ 289 PF_ARGB4444 /* 0x07 */ 290 }; 291 292 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = { 293 PF_ARGB8888, /* 0x00 */ 294 PF_ABGR8888, /* 0x01 */ 295 PF_RGBA8888, /* 0x02 */ 296 PF_BGRA8888, /* 0x03 */ 297 PF_RGB565, /* 0x04 */ 298 PF_BGR565, /* 0x05 */ 299 PF_RGB888, /* 0x06 */ 300 PF_NONE /* 0x07 */ 301 }; 302 303 static const u32 ltdc_drm_fmt_a0[] = { 304 DRM_FORMAT_ARGB8888, 305 DRM_FORMAT_XRGB8888, 306 DRM_FORMAT_RGB888, 307 DRM_FORMAT_RGB565, 308 DRM_FORMAT_ARGB1555, 309 DRM_FORMAT_XRGB1555, 310 DRM_FORMAT_ARGB4444, 311 DRM_FORMAT_XRGB4444, 312 DRM_FORMAT_C8 313 }; 314 315 static const u32 ltdc_drm_fmt_a1[] = { 316 DRM_FORMAT_ARGB8888, 317 DRM_FORMAT_XRGB8888, 318 DRM_FORMAT_RGB888, 319 DRM_FORMAT_RGB565, 320 DRM_FORMAT_RGBA8888, 321 DRM_FORMAT_RGBX8888, 322 DRM_FORMAT_ARGB1555, 323 DRM_FORMAT_XRGB1555, 324 DRM_FORMAT_ARGB4444, 325 DRM_FORMAT_XRGB4444, 326 DRM_FORMAT_C8 327 }; 328 329 static const u32 ltdc_drm_fmt_a2[] = { 330 DRM_FORMAT_ARGB8888, 331 DRM_FORMAT_XRGB8888, 332 DRM_FORMAT_ABGR8888, 333 DRM_FORMAT_XBGR8888, 334 DRM_FORMAT_RGBA8888, 335 DRM_FORMAT_RGBX8888, 336 DRM_FORMAT_BGRA8888, 337 DRM_FORMAT_BGRX8888, 338 DRM_FORMAT_RGB565, 339 DRM_FORMAT_BGR565, 340 DRM_FORMAT_RGB888, 341 DRM_FORMAT_BGR888, 342 DRM_FORMAT_ARGB1555, 343 DRM_FORMAT_XRGB1555, 344 DRM_FORMAT_ARGB4444, 345 DRM_FORMAT_XRGB4444, 346 DRM_FORMAT_C8 347 }; 348 349 static const u32 ltdc_drm_fmt_ycbcr_cp[] = { 350 DRM_FORMAT_YUYV, 351 DRM_FORMAT_YVYU, 352 DRM_FORMAT_UYVY, 353 DRM_FORMAT_VYUY 354 }; 355 356 static const u32 ltdc_drm_fmt_ycbcr_sp[] = { 357 DRM_FORMAT_NV12, 358 DRM_FORMAT_NV21 359 }; 360 361 static const u32 ltdc_drm_fmt_ycbcr_fp[] = { 362 DRM_FORMAT_YUV420, 363 DRM_FORMAT_YVU420 364 }; 365 366 /* Layer register offsets */ 367 static const u32 ltdc_layer_regs_a0[] = { 368 0x80, /* L1 configuration 0 */ 369 0x00, /* not available */ 370 0x00, /* not available */ 371 0x84, /* L1 control register */ 372 0x88, /* L1 window horizontal position configuration */ 373 0x8c, /* L1 window vertical position configuration */ 374 0x90, /* L1 color keying configuration */ 375 0x94, /* L1 pixel format configuration */ 376 0x98, /* L1 constant alpha configuration */ 377 0x9c, /* L1 default color configuration */ 378 0xa0, /* L1 blending factors configuration */ 379 0x00, /* not available */ 380 0x00, /* not available */ 381 0xac, /* L1 color frame buffer address */ 382 0xb0, /* L1 color frame buffer length */ 383 0xb4, /* L1 color frame buffer line number */ 384 0x00, /* not available */ 385 0x00, /* not available */ 386 0x00, /* not available */ 387 0x00, /* not available */ 388 0xc4, /* L1 CLUT write */ 389 0x00, /* not available */ 390 0x00, /* not available */ 391 0x00, /* not available */ 392 0x00 /* not available */ 393 }; 394 395 static const u32 ltdc_layer_regs_a1[] = { 396 0x80, /* L1 configuration 0 */ 397 0x84, /* L1 configuration 1 */ 398 0x00, /* L1 reload control */ 399 0x88, /* L1 control register */ 400 0x8c, /* L1 window horizontal position configuration */ 401 0x90, /* L1 window vertical position configuration */ 402 0x94, /* L1 color keying configuration */ 403 0x98, /* L1 pixel format configuration */ 404 0x9c, /* L1 constant alpha configuration */ 405 0xa0, /* L1 default color configuration */ 406 0xa4, /* L1 blending factors configuration */ 407 0xa8, /* L1 burst length configuration */ 408 0x00, /* not available */ 409 0xac, /* L1 color frame buffer address */ 410 0xb0, /* L1 color frame buffer length */ 411 0xb4, /* L1 color frame buffer line number */ 412 0xb8, /* L1 auxiliary frame buffer address 0 */ 413 0xbc, /* L1 auxiliary frame buffer address 1 */ 414 0xc0, /* L1 auxiliary frame buffer length */ 415 0xc4, /* L1 auxiliary frame buffer line number */ 416 0xc8, /* L1 CLUT write */ 417 0x00, /* not available */ 418 0x00, /* not available */ 419 0x00, /* not available */ 420 0x00 /* not available */ 421 }; 422 423 static const u32 ltdc_layer_regs_a2[] = { 424 0x100, /* L1 configuration 0 */ 425 0x104, /* L1 configuration 1 */ 426 0x108, /* L1 reload control */ 427 0x10c, /* L1 control register */ 428 0x110, /* L1 window horizontal position configuration */ 429 0x114, /* L1 window vertical position configuration */ 430 0x118, /* L1 color keying configuration */ 431 0x11c, /* L1 pixel format configuration */ 432 0x120, /* L1 constant alpha configuration */ 433 0x124, /* L1 default color configuration */ 434 0x128, /* L1 blending factors configuration */ 435 0x12c, /* L1 burst length configuration */ 436 0x130, /* L1 planar configuration */ 437 0x134, /* L1 color frame buffer address */ 438 0x138, /* L1 color frame buffer length */ 439 0x13c, /* L1 color frame buffer line number */ 440 0x140, /* L1 auxiliary frame buffer address 0 */ 441 0x144, /* L1 auxiliary frame buffer address 1 */ 442 0x148, /* L1 auxiliary frame buffer length */ 443 0x14c, /* L1 auxiliary frame buffer line number */ 444 0x150, /* L1 CLUT write */ 445 0x16c, /* L1 Conversion YCbCr RGB 0 */ 446 0x170, /* L1 Conversion YCbCr RGB 1 */ 447 0x174, /* L1 Flexible Pixel Format 0 */ 448 0x178 /* L1 Flexible Pixel Format 1 */ 449 }; 450 451 static const u64 ltdc_format_modifiers[] = { 452 DRM_FORMAT_MOD_LINEAR, 453 DRM_FORMAT_MOD_INVALID 454 }; 455 456 static const struct regmap_config stm32_ltdc_regmap_cfg = { 457 .reg_bits = 32, 458 .val_bits = 32, 459 .reg_stride = sizeof(u32), 460 .max_register = 0x400, 461 .use_relaxed_mmio = true, 462 .cache_type = REGCACHE_NONE, 463 }; 464 465 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = { 466 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 467 0x02040199, /* (b_cb = 516 / r_cr = 409) */ 468 0x006400D0 /* (g_cb = 100 / g_cr = 208) */ 469 }, 470 [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = { 471 0x01C60167, /* (b_cb = 454 / r_cr = 359) */ 472 0x005800B7 /* (g_cb = 88 / g_cr = 183) */ 473 }, 474 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = { 475 0x021D01CB, /* (b_cb = 541 / r_cr = 459) */ 476 0x00370089 /* (g_cb = 55 / g_cr = 137) */ 477 }, 478 [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = { 479 0x01DB0193, /* (b_cb = 475 / r_cr = 403) */ 480 0x00300078 /* (g_cb = 48 / g_cr = 120) */ 481 } 482 /* BT2020 not supported */ 483 }; 484 485 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 486 { 487 return (struct ltdc_device *)crtc->dev->dev_private; 488 } 489 490 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 491 { 492 return (struct ltdc_device *)plane->dev->dev_private; 493 } 494 495 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 496 { 497 return (struct ltdc_device *)enc->dev->dev_private; 498 } 499 500 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 501 { 502 enum ltdc_pix_fmt pf; 503 504 switch (drm_fmt) { 505 case DRM_FORMAT_ARGB8888: 506 case DRM_FORMAT_XRGB8888: 507 pf = PF_ARGB8888; 508 break; 509 case DRM_FORMAT_ABGR8888: 510 case DRM_FORMAT_XBGR8888: 511 pf = PF_ABGR8888; 512 break; 513 case DRM_FORMAT_RGBA8888: 514 case DRM_FORMAT_RGBX8888: 515 pf = PF_RGBA8888; 516 break; 517 case DRM_FORMAT_BGRA8888: 518 case DRM_FORMAT_BGRX8888: 519 pf = PF_BGRA8888; 520 break; 521 case DRM_FORMAT_RGB888: 522 pf = PF_RGB888; 523 break; 524 case DRM_FORMAT_BGR888: 525 pf = PF_BGR888; 526 break; 527 case DRM_FORMAT_RGB565: 528 pf = PF_RGB565; 529 break; 530 case DRM_FORMAT_BGR565: 531 pf = PF_BGR565; 532 break; 533 case DRM_FORMAT_ARGB1555: 534 case DRM_FORMAT_XRGB1555: 535 pf = PF_ARGB1555; 536 break; 537 case DRM_FORMAT_ARGB4444: 538 case DRM_FORMAT_XRGB4444: 539 pf = PF_ARGB4444; 540 break; 541 case DRM_FORMAT_C8: 542 pf = PF_L8; 543 break; 544 default: 545 pf = PF_NONE; 546 break; 547 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 548 } 549 550 return pf; 551 } 552 553 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt) 554 { 555 struct ltdc_device *ldev = plane_to_ltdc(plane); 556 u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE; 557 int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos; 558 559 switch (pix_fmt) { 560 case PF_BGR888: 561 psize = 3; 562 alen = 0; apos = 0; rlen = 8; rpos = 0; 563 glen = 8; gpos = 8; blen = 8; bpos = 16; 564 break; 565 case PF_ARGB1555: 566 psize = 2; 567 alen = 1; apos = 15; rlen = 5; rpos = 10; 568 glen = 5; gpos = 5; blen = 5; bpos = 0; 569 break; 570 case PF_ARGB4444: 571 psize = 2; 572 alen = 4; apos = 12; rlen = 4; rpos = 8; 573 glen = 4; gpos = 4; blen = 4; bpos = 0; 574 break; 575 case PF_L8: 576 psize = 1; 577 alen = 0; apos = 0; rlen = 8; rpos = 0; 578 glen = 8; gpos = 0; blen = 8; bpos = 0; 579 break; 580 case PF_AL44: 581 psize = 1; 582 alen = 4; apos = 4; rlen = 4; rpos = 0; 583 glen = 4; gpos = 0; blen = 4; bpos = 0; 584 break; 585 case PF_AL88: 586 psize = 2; 587 alen = 8; apos = 8; rlen = 8; rpos = 0; 588 glen = 8; gpos = 0; blen = 8; bpos = 0; 589 break; 590 default: 591 ret = NB_PF; /* error case, trace msg is handled by the caller */ 592 break; 593 } 594 595 if (ret == PF_FLEXIBLE) { 596 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs, 597 (rlen << 14) + (rpos << 9) + (alen << 5) + apos); 598 599 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs, 600 (psize << 18) + (blen << 14) + (bpos << 9) + (glen << 5) + gpos); 601 } 602 603 return ret; 604 } 605 606 /* 607 * All non-alpha color formats derived from native alpha color formats are 608 * either characterized by a FourCC format code 609 */ 610 static inline u32 is_xrgb(u32 drm) 611 { 612 return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X'); 613 } 614 615 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt) 616 { 617 struct ltdc_device *ldev = plane_to_ltdc(plane); 618 struct drm_plane_state *state = plane->state; 619 u32 lofs = plane->index * LAY_OFS; 620 u32 val; 621 622 switch (drm_pix_fmt) { 623 case DRM_FORMAT_YUYV: 624 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF; 625 break; 626 case DRM_FORMAT_YVYU: 627 val = (YCM_I << 4) | LxPCR_YF; 628 break; 629 case DRM_FORMAT_UYVY: 630 val = (YCM_I << 4) | LxPCR_CBF; 631 break; 632 case DRM_FORMAT_VYUY: 633 val = (YCM_I << 4); 634 break; 635 case DRM_FORMAT_NV12: 636 val = (YCM_SP << 4) | LxPCR_CBF; 637 break; 638 case DRM_FORMAT_NV21: 639 val = (YCM_SP << 4); 640 break; 641 case DRM_FORMAT_YUV420: 642 case DRM_FORMAT_YVU420: 643 val = (YCM_FP << 4); 644 break; 645 default: 646 /* RGB or not a YCbCr supported format */ 647 DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt); 648 return; 649 } 650 651 /* Enable limited range */ 652 if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) 653 val |= LxPCR_YREN; 654 655 /* enable ycbcr conversion */ 656 val |= LxPCR_YCEN; 657 658 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val); 659 } 660 661 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane) 662 { 663 struct ltdc_device *ldev = plane_to_ltdc(plane); 664 struct drm_plane_state *state = plane->state; 665 enum drm_color_encoding enc = state->color_encoding; 666 enum drm_color_range ran = state->color_range; 667 u32 lofs = plane->index * LAY_OFS; 668 669 if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) { 670 DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc); 671 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */ 672 enc = DRM_COLOR_YCBCR_BT601; 673 } 674 675 if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) { 676 DRM_ERROR("color range %d not supported, use limited range by default\n", ran); 677 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */ 678 ran = DRM_COLOR_YCBCR_LIMITED_RANGE; 679 } 680 681 DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran); 682 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, 683 ltdc_ycbcr2rgb_coeffs[enc][ran][0]); 684 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, 685 ltdc_ycbcr2rgb_coeffs[enc][ran][1]); 686 } 687 688 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev, 689 struct drm_crtc *crtc) 690 { 691 u32 crc; 692 int ret; 693 694 if (ldev->crc_skip_count < CRC_SKIP_FRAMES) { 695 ldev->crc_skip_count++; 696 return; 697 } 698 699 /* Get the CRC of the frame */ 700 ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc); 701 if (ret) 702 return; 703 704 /* Report to DRM the CRC (hw dependent feature) */ 705 drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc); 706 } 707 708 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 709 { 710 struct drm_device *ddev = arg; 711 struct ltdc_device *ldev = ddev->dev_private; 712 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 713 714 /* Line IRQ : trigger the vblank event */ 715 if (ldev->irq_status & ISR_LIF) { 716 drm_crtc_handle_vblank(crtc); 717 718 /* Early return if CRC is not active */ 719 if (ldev->crc_active) 720 ltdc_irq_crc_handle(ldev, crtc); 721 } 722 723 mutex_lock(&ldev->err_lock); 724 if (ldev->irq_status & ISR_TERRIF) 725 ldev->transfer_err++; 726 if (ldev->irq_status & ISR_FUEIF) 727 ldev->fifo_err++; 728 if (ldev->irq_status & ISR_FUWIF) 729 ldev->fifo_warn++; 730 mutex_unlock(&ldev->err_lock); 731 732 return IRQ_HANDLED; 733 } 734 735 static irqreturn_t ltdc_irq(int irq, void *arg) 736 { 737 struct drm_device *ddev = arg; 738 struct ltdc_device *ldev = ddev->dev_private; 739 740 /* 741 * Read & Clear the interrupt status 742 * In order to write / read registers in this critical section 743 * very quickly, the regmap functions are not used. 744 */ 745 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR); 746 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR); 747 748 return IRQ_WAKE_THREAD; 749 } 750 751 /* 752 * DRM_CRTC 753 */ 754 755 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 756 { 757 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 758 struct drm_color_lut *lut; 759 u32 val; 760 int i; 761 762 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 763 return; 764 765 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 766 767 for (i = 0; i < CLUT_SIZE; i++, lut++) { 768 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 769 (lut->blue >> 8) | (i << 24); 770 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val); 771 } 772 } 773 774 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 775 struct drm_atomic_state *state) 776 { 777 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 778 struct drm_device *ddev = crtc->dev; 779 780 DRM_DEBUG_DRIVER("\n"); 781 782 pm_runtime_get_sync(ddev->dev); 783 784 /* Sets the background color value */ 785 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); 786 787 /* Enable IRQ */ 788 regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE); 789 790 /* Commit shadow registers = update planes at next vblank */ 791 if (!ldev->caps.plane_reg_shadow) 792 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 793 794 drm_crtc_vblank_on(crtc); 795 } 796 797 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 798 struct drm_atomic_state *state) 799 { 800 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 801 struct drm_device *ddev = crtc->dev; 802 int layer_index = 0; 803 804 DRM_DEBUG_DRIVER("\n"); 805 806 drm_crtc_vblank_off(crtc); 807 808 /* Disable all layers */ 809 for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) 810 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, 811 LXCR_CLUTEN | LXCR_LEN, 0); 812 813 /* disable IRQ */ 814 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE); 815 816 /* immediately commit disable of layers before switching off LTDC */ 817 if (!ldev->caps.plane_reg_shadow) 818 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); 819 820 pm_runtime_put_sync(ddev->dev); 821 822 /* clear interrupt error counters */ 823 mutex_lock(&ldev->err_lock); 824 ldev->transfer_err = 0; 825 ldev->fifo_err = 0; 826 ldev->fifo_warn = 0; 827 mutex_unlock(&ldev->err_lock); 828 } 829 830 #define CLK_TOLERANCE_HZ 50 831 832 static enum drm_mode_status 833 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 834 const struct drm_display_mode *mode) 835 { 836 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 837 int target = mode->clock * 1000; 838 int target_min = target - CLK_TOLERANCE_HZ; 839 int target_max = target + CLK_TOLERANCE_HZ; 840 int result; 841 842 result = clk_round_rate(ldev->pixel_clk, target); 843 844 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 845 846 /* Filter modes according to the max frequency supported by the pads */ 847 if (result > ldev->caps.pad_max_freq_hz) 848 return MODE_CLOCK_HIGH; 849 850 /* 851 * Accept all "preferred" modes: 852 * - this is important for panels because panel clock tolerances are 853 * bigger than hdmi ones and there is no reason to not accept them 854 * (the fps may vary a little but it is not a problem). 855 * - the hdmi preferred mode will be accepted too, but userland will 856 * be able to use others hdmi "valid" modes if necessary. 857 */ 858 if (mode->type & DRM_MODE_TYPE_PREFERRED) 859 return MODE_OK; 860 861 /* 862 * Filter modes according to the clock value, particularly useful for 863 * hdmi modes that require precise pixel clocks. 864 */ 865 if (result < target_min || result > target_max) 866 return MODE_CLOCK_RANGE; 867 868 return MODE_OK; 869 } 870 871 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 872 const struct drm_display_mode *mode, 873 struct drm_display_mode *adjusted_mode) 874 { 875 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 876 int rate = mode->clock * 1000; 877 878 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 879 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 880 return false; 881 } 882 883 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 884 885 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 886 mode->clock, adjusted_mode->clock); 887 888 return true; 889 } 890 891 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 892 { 893 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 894 struct drm_device *ddev = crtc->dev; 895 struct drm_connector_list_iter iter; 896 struct drm_connector *connector = NULL; 897 struct drm_encoder *encoder = NULL, *en_iter; 898 struct drm_bridge *bridge = NULL, *br_iter; 899 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 900 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 901 u32 total_width, total_height; 902 u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24; 903 u32 bus_flags = 0; 904 u32 val; 905 int ret; 906 907 /* get encoder from crtc */ 908 drm_for_each_encoder(en_iter, ddev) 909 if (en_iter->crtc == crtc) { 910 encoder = en_iter; 911 break; 912 } 913 914 if (encoder) { 915 /* get bridge from encoder */ 916 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node) 917 if (br_iter->encoder == encoder) { 918 bridge = br_iter; 919 break; 920 } 921 922 /* Get the connector from encoder */ 923 drm_connector_list_iter_begin(ddev, &iter); 924 drm_for_each_connector_iter(connector, &iter) 925 if (connector->encoder == encoder) 926 break; 927 drm_connector_list_iter_end(&iter); 928 } 929 930 if (bridge && bridge->timings) { 931 bus_flags = bridge->timings->input_bus_flags; 932 } else if (connector) { 933 bus_flags = connector->display_info.bus_flags; 934 if (connector->display_info.num_bus_formats) 935 bus_formats = connector->display_info.bus_formats[0]; 936 } 937 938 if (!pm_runtime_active(ddev->dev)) { 939 ret = pm_runtime_get_sync(ddev->dev); 940 if (ret) { 941 DRM_ERROR("Failed to set mode, cannot get sync\n"); 942 return; 943 } 944 } 945 946 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 947 DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 948 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 949 mode->hsync_start - mode->hdisplay, 950 mode->htotal - mode->hsync_end, 951 mode->hsync_end - mode->hsync_start, 952 mode->vsync_start - mode->vdisplay, 953 mode->vtotal - mode->vsync_end, 954 mode->vsync_end - mode->vsync_start); 955 956 /* Convert video timings to ltdc timings */ 957 hsync = mode->hsync_end - mode->hsync_start - 1; 958 vsync = mode->vsync_end - mode->vsync_start - 1; 959 accum_hbp = mode->htotal - mode->hsync_start - 1; 960 accum_vbp = mode->vtotal - mode->vsync_start - 1; 961 accum_act_w = accum_hbp + mode->hdisplay; 962 accum_act_h = accum_vbp + mode->vdisplay; 963 total_width = mode->htotal - 1; 964 total_height = mode->vtotal - 1; 965 966 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 967 val = 0; 968 969 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 970 val |= GCR_HSPOL; 971 972 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 973 val |= GCR_VSPOL; 974 975 if (bus_flags & DRM_BUS_FLAG_DE_LOW) 976 val |= GCR_DEPOL; 977 978 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 979 val |= GCR_PCPOL; 980 981 regmap_update_bits(ldev->regmap, LTDC_GCR, 982 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 983 984 /* Set Synchronization size */ 985 val = (hsync << 16) | vsync; 986 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 987 988 /* Set Accumulated Back porch */ 989 val = (accum_hbp << 16) | accum_vbp; 990 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 991 992 /* Set Accumulated Active Width */ 993 val = (accum_act_w << 16) | accum_act_h; 994 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 995 996 /* Set total width & height */ 997 val = (total_width << 16) | total_height; 998 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 999 1000 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1)); 1001 1002 /* Configure the output format (hw version dependent) */ 1003 if (ldev->caps.ycbcr_output) { 1004 /* Input video dynamic_range & colorimetry */ 1005 int vic = drm_match_cea_mode(mode); 1006 u32 val; 1007 1008 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 || 1009 vic == 2 || vic == 3 || vic == 17 || vic == 18) 1010 /* ITU-R BT.601 */ 1011 val = 0; 1012 else 1013 /* ITU-R BT.709 */ 1014 val = EDCR_OCYSEL; 1015 1016 switch (bus_formats) { 1017 case MEDIA_BUS_FMT_YUYV8_1X16: 1018 /* enable ycbcr output converter */ 1019 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val); 1020 break; 1021 case MEDIA_BUS_FMT_YVYU8_1X16: 1022 /* enable ycbcr output converter & invert chrominance order */ 1023 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val); 1024 break; 1025 default: 1026 /* disable ycbcr output converter */ 1027 regmap_write(ldev->regmap, LTDC_EDCR, 0); 1028 break; 1029 } 1030 } 1031 } 1032 1033 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 1034 struct drm_atomic_state *state) 1035 { 1036 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1037 struct drm_device *ddev = crtc->dev; 1038 struct drm_pending_vblank_event *event = crtc->state->event; 1039 1040 DRM_DEBUG_ATOMIC("\n"); 1041 1042 ltdc_crtc_update_clut(crtc); 1043 1044 /* Commit shadow registers = update planes at next vblank */ 1045 if (!ldev->caps.plane_reg_shadow) 1046 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); 1047 1048 if (event) { 1049 crtc->state->event = NULL; 1050 1051 spin_lock_irq(&ddev->event_lock); 1052 if (drm_crtc_vblank_get(crtc) == 0) 1053 drm_crtc_arm_vblank_event(crtc, event); 1054 else 1055 drm_crtc_send_vblank_event(crtc, event); 1056 spin_unlock_irq(&ddev->event_lock); 1057 } 1058 } 1059 1060 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, 1061 bool in_vblank_irq, 1062 int *vpos, int *hpos, 1063 ktime_t *stime, ktime_t *etime, 1064 const struct drm_display_mode *mode) 1065 { 1066 struct drm_device *ddev = crtc->dev; 1067 struct ltdc_device *ldev = ddev->dev_private; 1068 int line, vactive_start, vactive_end, vtotal; 1069 1070 if (stime) 1071 *stime = ktime_get(); 1072 1073 /* The active area starts after vsync + front porch and ends 1074 * at vsync + front porc + display size. 1075 * The total height also include back porch. 1076 * We have 3 possible cases to handle: 1077 * - line < vactive_start: vpos = line - vactive_start and will be 1078 * negative 1079 * - vactive_start < line < vactive_end: vpos = line - vactive_start 1080 * and will be positive 1081 * - line > vactive_end: vpos = line - vtotal - vactive_start 1082 * and will negative 1083 * 1084 * Computation for the two first cases are identical so we can 1085 * simplify the code and only test if line > vactive_end 1086 */ 1087 if (pm_runtime_active(ddev->dev)) { 1088 regmap_read(ldev->regmap, LTDC_CPSR, &line); 1089 line &= CPSR_CYPOS; 1090 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start); 1091 vactive_start &= BPCR_AVBP; 1092 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end); 1093 vactive_end &= AWCR_AAH; 1094 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal); 1095 vtotal &= TWCR_TOTALH; 1096 1097 if (line > vactive_end) 1098 *vpos = line - vtotal - vactive_start; 1099 else 1100 *vpos = line - vactive_start; 1101 } else { 1102 *vpos = 0; 1103 } 1104 1105 *hpos = 0; 1106 1107 if (etime) 1108 *etime = ktime_get(); 1109 1110 return true; 1111 } 1112 1113 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 1114 .mode_valid = ltdc_crtc_mode_valid, 1115 .mode_fixup = ltdc_crtc_mode_fixup, 1116 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 1117 .atomic_flush = ltdc_crtc_atomic_flush, 1118 .atomic_enable = ltdc_crtc_atomic_enable, 1119 .atomic_disable = ltdc_crtc_atomic_disable, 1120 .get_scanout_position = ltdc_crtc_get_scanout_position, 1121 }; 1122 1123 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 1124 { 1125 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1126 struct drm_crtc_state *state = crtc->state; 1127 1128 DRM_DEBUG_DRIVER("\n"); 1129 1130 if (state->enable) 1131 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); 1132 else 1133 return -EPERM; 1134 1135 return 0; 1136 } 1137 1138 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 1139 { 1140 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1141 1142 DRM_DEBUG_DRIVER("\n"); 1143 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); 1144 } 1145 1146 static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source) 1147 { 1148 struct ltdc_device *ldev; 1149 int ret; 1150 1151 DRM_DEBUG_DRIVER("\n"); 1152 1153 if (!crtc) 1154 return -ENODEV; 1155 1156 ldev = crtc_to_ltdc(crtc); 1157 1158 if (source && strcmp(source, "auto") == 0) { 1159 ldev->crc_active = true; 1160 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1161 } else if (!source) { 1162 ldev->crc_active = false; 1163 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); 1164 } else { 1165 ret = -EINVAL; 1166 } 1167 1168 ldev->crc_skip_count = 0; 1169 return ret; 1170 } 1171 1172 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, 1173 const char *source, size_t *values_cnt) 1174 { 1175 DRM_DEBUG_DRIVER("\n"); 1176 1177 if (!crtc) 1178 return -ENODEV; 1179 1180 if (source && strcmp(source, "auto") != 0) { 1181 DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n", 1182 source, crtc->name); 1183 return -EINVAL; 1184 } 1185 1186 *values_cnt = 1; 1187 return 0; 1188 } 1189 1190 static void ltdc_crtc_atomic_print_state(struct drm_printer *p, 1191 const struct drm_crtc_state *state) 1192 { 1193 struct drm_crtc *crtc = state->crtc; 1194 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1195 1196 drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err); 1197 drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err); 1198 drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn); 1199 drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold); 1200 } 1201 1202 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 1203 .set_config = drm_atomic_helper_set_config, 1204 .page_flip = drm_atomic_helper_page_flip, 1205 .reset = drm_atomic_helper_crtc_reset, 1206 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1207 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1208 .enable_vblank = ltdc_crtc_enable_vblank, 1209 .disable_vblank = ltdc_crtc_disable_vblank, 1210 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1211 .atomic_print_state = ltdc_crtc_atomic_print_state, 1212 }; 1213 1214 static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = { 1215 .set_config = drm_atomic_helper_set_config, 1216 .page_flip = drm_atomic_helper_page_flip, 1217 .reset = drm_atomic_helper_crtc_reset, 1218 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1219 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1220 .enable_vblank = ltdc_crtc_enable_vblank, 1221 .disable_vblank = ltdc_crtc_disable_vblank, 1222 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1223 .set_crc_source = ltdc_crtc_set_crc_source, 1224 .verify_crc_source = ltdc_crtc_verify_crc_source, 1225 .atomic_print_state = ltdc_crtc_atomic_print_state, 1226 }; 1227 1228 /* 1229 * DRM_PLANE 1230 */ 1231 1232 static int ltdc_plane_atomic_check(struct drm_plane *plane, 1233 struct drm_atomic_state *state) 1234 { 1235 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1236 plane); 1237 struct drm_framebuffer *fb = new_plane_state->fb; 1238 u32 src_w, src_h; 1239 1240 DRM_DEBUG_DRIVER("\n"); 1241 1242 if (!fb) 1243 return 0; 1244 1245 /* convert src_ from 16:16 format */ 1246 src_w = new_plane_state->src_w >> 16; 1247 src_h = new_plane_state->src_h >> 16; 1248 1249 /* Reject scaling */ 1250 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 1251 DRM_DEBUG_DRIVER("Scaling is not supported"); 1252 1253 return -EINVAL; 1254 } 1255 1256 return 0; 1257 } 1258 1259 static void ltdc_plane_atomic_update(struct drm_plane *plane, 1260 struct drm_atomic_state *state) 1261 { 1262 struct ltdc_device *ldev = plane_to_ltdc(plane); 1263 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 1264 plane); 1265 struct drm_framebuffer *fb = newstate->fb; 1266 u32 lofs = plane->index * LAY_OFS; 1267 u32 x0 = newstate->crtc_x; 1268 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; 1269 u32 y0 = newstate->crtc_y; 1270 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; 1271 u32 src_x, src_y, src_w, src_h; 1272 u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr; 1273 u32 paddr, paddr1, paddr2; 1274 enum ltdc_pix_fmt pf; 1275 1276 if (!newstate->crtc || !fb) { 1277 DRM_DEBUG_DRIVER("fb or crtc NULL"); 1278 return; 1279 } 1280 1281 /* convert src_ from 16:16 format */ 1282 src_x = newstate->src_x >> 16; 1283 src_y = newstate->src_y >> 16; 1284 src_w = newstate->src_w >> 16; 1285 src_h = newstate->src_h >> 16; 1286 1287 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 1288 plane->base.id, fb->base.id, 1289 src_w, src_h, src_x, src_y, 1290 newstate->crtc_w, newstate->crtc_h, 1291 newstate->crtc_x, newstate->crtc_y); 1292 1293 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); 1294 1295 ahbp = (bpcr & BPCR_AHBP) >> 16; 1296 avbp = bpcr & BPCR_AVBP; 1297 1298 /* Configures the horizontal start and stop position */ 1299 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 1300 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs, 1301 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 1302 1303 /* Configures the vertical start and stop position */ 1304 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 1305 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs, 1306 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 1307 1308 /* Specifies the pixel format */ 1309 pf = to_ltdc_pixelformat(fb->format->format); 1310 for (val = 0; val < NB_PF; val++) 1311 if (ldev->caps.pix_fmt_hw[val] == pf) 1312 break; 1313 1314 /* Use the flexible color format feature if necessary and available */ 1315 if (ldev->caps.pix_fmt_flex && val == NB_PF) 1316 val = ltdc_set_flexible_pixel_format(plane, pf); 1317 1318 if (val == NB_PF) { 1319 DRM_ERROR("Pixel format %.4s not supported\n", 1320 (char *)&fb->format->format); 1321 val = 0; /* set by default ARGB 32 bits */ 1322 } 1323 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 1324 1325 /* Specifies the constant alpha value */ 1326 val = newstate->alpha >> 8; 1327 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 1328 1329 /* Specifies the blending factors */ 1330 val = BF1_PAXCA | BF2_1PAXCA; 1331 if (!fb->format->has_alpha) 1332 val = BF1_CA | BF2_1CA; 1333 1334 /* Manage hw-specific capabilities */ 1335 if (ldev->caps.non_alpha_only_l1 && 1336 plane->type != DRM_PLANE_TYPE_PRIMARY) 1337 val = BF1_PAXCA | BF2_1PAXCA; 1338 1339 if (ldev->caps.dynamic_zorder) { 1340 val |= (newstate->normalized_zpos << 16); 1341 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1342 LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val); 1343 } else { 1344 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, 1345 LXBFCR_BF2 | LXBFCR_BF1, val); 1346 } 1347 1348 /* Sets the FB address */ 1349 paddr = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 0); 1350 1351 if (newstate->rotation & DRM_MODE_REFLECT_X) 1352 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1; 1353 1354 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1355 paddr += (fb->pitches[0] * (y1 - y0)); 1356 1357 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 1358 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); 1359 1360 /* Configures the color frame buffer pitch in bytes & line length */ 1361 line_length = fb->format->cpp[0] * 1362 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 1363 1364 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1365 /* Compute negative value (signed on 16 bits) for the picth */ 1366 pitch_in_bytes = 0x10000 - fb->pitches[0]; 1367 else 1368 pitch_in_bytes = fb->pitches[0]; 1369 1370 val = (pitch_in_bytes << 16) | line_length; 1371 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 1372 1373 /* Configures the frame buffer line number */ 1374 line_number = y1 - y0 + 1; 1375 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); 1376 1377 if (ldev->caps.ycbcr_input) { 1378 if (fb->format->is_yuv) { 1379 switch (fb->format->format) { 1380 case DRM_FORMAT_NV12: 1381 case DRM_FORMAT_NV21: 1382 /* Configure the auxiliary frame buffer address 0 */ 1383 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1384 1385 if (newstate->rotation & DRM_MODE_REFLECT_X) 1386 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1387 1388 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1389 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1390 1391 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1392 break; 1393 case DRM_FORMAT_YUV420: 1394 /* Configure the auxiliary frame buffer address 0 & 1 */ 1395 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1396 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1397 1398 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1399 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1400 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1401 } 1402 1403 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1404 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1405 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1406 } 1407 1408 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1409 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1410 break; 1411 case DRM_FORMAT_YVU420: 1412 /* Configure the auxiliary frame buffer address 0 & 1 */ 1413 paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2); 1414 paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1); 1415 1416 if (newstate->rotation & DRM_MODE_REFLECT_X) { 1417 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; 1418 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; 1419 } 1420 1421 if (newstate->rotation & DRM_MODE_REFLECT_Y) { 1422 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; 1423 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; 1424 } 1425 1426 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); 1427 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); 1428 break; 1429 } 1430 1431 /* 1432 * Set the length and the number of lines of the auxiliary 1433 * buffers if the framebuffer contains more than one plane. 1434 */ 1435 if (fb->format->num_planes > 1) { 1436 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1437 /* 1438 * Compute negative value (signed on 16 bits) 1439 * for the picth 1440 */ 1441 pitch_in_bytes = 0x10000 - fb->pitches[1]; 1442 else 1443 pitch_in_bytes = fb->pitches[1]; 1444 1445 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) + 1446 (ldev->caps.bus_width >> 3) - 1; 1447 1448 /* Configure the auxiliary buffer length */ 1449 val = (pitch_in_bytes << 16) | line_length; 1450 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); 1451 1452 /* Configure the auxiliary frame buffer line number */ 1453 val = line_number >> 1; 1454 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); 1455 } 1456 1457 /* Configure YCbC conversion coefficient */ 1458 ltdc_set_ycbcr_coeffs(plane); 1459 1460 /* Configure YCbCr format and enable/disable conversion */ 1461 ltdc_set_ycbcr_config(plane, fb->format->format); 1462 } else { 1463 /* disable ycbcr conversion */ 1464 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0); 1465 } 1466 } 1467 1468 /* Enable layer and CLUT if needed */ 1469 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 1470 val |= LXCR_LEN; 1471 1472 /* Enable horizontal mirroring if requested */ 1473 if (newstate->rotation & DRM_MODE_REFLECT_X) 1474 val |= LXCR_HMEN; 1475 1476 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, val); 1477 1478 /* Commit shadow registers = update plane at next vblank */ 1479 if (ldev->caps.plane_reg_shadow) 1480 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1481 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1482 1483 ldev->plane_fpsi[plane->index].counter++; 1484 1485 mutex_lock(&ldev->err_lock); 1486 if (ldev->transfer_err) { 1487 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); 1488 ldev->transfer_err = 0; 1489 } 1490 1491 if (ldev->caps.fifo_threshold) { 1492 if (ldev->fifo_err) { 1493 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1494 ldev->fifo_err = 0; 1495 } 1496 } else { 1497 if (ldev->fifo_warn >= ldev->fifo_threshold) { 1498 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 1499 ldev->fifo_warn = 0; 1500 } 1501 } 1502 mutex_unlock(&ldev->err_lock); 1503 } 1504 1505 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 1506 struct drm_atomic_state *state) 1507 { 1508 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 1509 plane); 1510 struct ltdc_device *ldev = plane_to_ltdc(plane); 1511 u32 lofs = plane->index * LAY_OFS; 1512 1513 /* Disable layer */ 1514 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, 0); 1515 1516 /* Reset the layer transparency to hide any related background color */ 1517 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, 0x00); 1518 1519 /* Commit shadow registers = update plane at next vblank */ 1520 if (ldev->caps.plane_reg_shadow) 1521 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1522 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1523 1524 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 1525 oldstate->crtc->base.id, plane->base.id); 1526 } 1527 1528 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 1529 const struct drm_plane_state *state) 1530 { 1531 struct drm_plane *plane = state->plane; 1532 struct ltdc_device *ldev = plane_to_ltdc(plane); 1533 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 1534 int ms_since_last; 1535 ktime_t now; 1536 1537 now = ktime_get(); 1538 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 1539 1540 drm_printf(p, "\tuser_updates=%dfps\n", 1541 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 1542 1543 fpsi->last_timestamp = now; 1544 fpsi->counter = 0; 1545 } 1546 1547 static const struct drm_plane_funcs ltdc_plane_funcs = { 1548 .update_plane = drm_atomic_helper_update_plane, 1549 .disable_plane = drm_atomic_helper_disable_plane, 1550 .reset = drm_atomic_helper_plane_reset, 1551 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1552 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1553 .atomic_print_state = ltdc_plane_atomic_print_state, 1554 }; 1555 1556 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 1557 .atomic_check = ltdc_plane_atomic_check, 1558 .atomic_update = ltdc_plane_atomic_update, 1559 .atomic_disable = ltdc_plane_atomic_disable, 1560 }; 1561 1562 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 1563 enum drm_plane_type type, 1564 int index) 1565 { 1566 unsigned long possible_crtcs = CRTC_MASK; 1567 struct ltdc_device *ldev = ddev->dev_private; 1568 struct device *dev = ddev->dev; 1569 struct drm_plane *plane; 1570 unsigned int i, nb_fmt = 0; 1571 u32 *formats; 1572 u32 drm_fmt; 1573 const u64 *modifiers = ltdc_format_modifiers; 1574 u32 lofs = index * LAY_OFS; 1575 u32 val; 1576 1577 /* Allocate the biggest size according to supported color formats */ 1578 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb + 1579 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) + 1580 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) + 1581 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) * 1582 sizeof(*formats), GFP_KERNEL); 1583 if (!formats) 1584 return NULL; 1585 1586 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) { 1587 drm_fmt = ldev->caps.pix_fmt_drm[i]; 1588 1589 /* Manage hw-specific capabilities */ 1590 if (ldev->caps.non_alpha_only_l1) 1591 /* XR24 & RX24 like formats supported only on primary layer */ 1592 if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt)) 1593 continue; 1594 1595 formats[nb_fmt++] = drm_fmt; 1596 } 1597 1598 /* Add YCbCr supported pixel formats */ 1599 if (ldev->caps.ycbcr_input) { 1600 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val); 1601 if (val & LXCR_C1R_YIA) { 1602 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp, 1603 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats)); 1604 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp); 1605 } 1606 if (val & LXCR_C1R_YSPA) { 1607 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp, 1608 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats)); 1609 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp); 1610 } 1611 if (val & LXCR_C1R_YFPA) { 1612 memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp, 1613 ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats)); 1614 nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp); 1615 } 1616 } 1617 1618 plane = drmm_universal_plane_alloc(ddev, struct drm_plane, dev, 1619 possible_crtcs, <dc_plane_funcs, formats, 1620 nb_fmt, modifiers, type, NULL); 1621 if (IS_ERR(plane)) 1622 return NULL; 1623 1624 if (ldev->caps.ycbcr_input) { 1625 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA)) 1626 drm_plane_create_color_properties(plane, 1627 BIT(DRM_COLOR_YCBCR_BT601) | 1628 BIT(DRM_COLOR_YCBCR_BT709), 1629 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1630 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1631 DRM_COLOR_YCBCR_BT601, 1632 DRM_COLOR_YCBCR_LIMITED_RANGE); 1633 } 1634 1635 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 1636 1637 drm_plane_create_alpha_property(plane); 1638 1639 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 1640 1641 return plane; 1642 } 1643 1644 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 1645 { 1646 struct ltdc_device *ldev = ddev->dev_private; 1647 struct drm_plane *primary, *overlay; 1648 int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; 1649 unsigned int i; 1650 int ret; 1651 1652 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); 1653 if (!primary) { 1654 DRM_ERROR("Can not create primary plane\n"); 1655 return -EINVAL; 1656 } 1657 1658 if (ldev->caps.dynamic_zorder) 1659 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1); 1660 else 1661 drm_plane_create_zpos_immutable_property(primary, 0); 1662 1663 if (ldev->caps.plane_rotation) 1664 drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0, 1665 supported_rotations); 1666 1667 /* Init CRTC according to its hardware features */ 1668 if (ldev->caps.crc) 1669 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1670 <dc_crtc_with_crc_support_funcs, NULL); 1671 else 1672 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1673 <dc_crtc_funcs, NULL); 1674 if (ret) { 1675 DRM_ERROR("Can not initialize CRTC\n"); 1676 return ret; 1677 } 1678 1679 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1680 1681 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1682 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1683 1684 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1685 1686 /* Add planes. Note : the first layer is used by primary plane */ 1687 for (i = 1; i < ldev->caps.nb_layers; i++) { 1688 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i); 1689 if (!overlay) { 1690 DRM_ERROR("Can not create overlay plane %d\n", i); 1691 return -ENOMEM; 1692 } 1693 if (ldev->caps.dynamic_zorder) 1694 drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); 1695 else 1696 drm_plane_create_zpos_immutable_property(overlay, i); 1697 1698 if (ldev->caps.plane_rotation) 1699 drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0, 1700 supported_rotations); 1701 } 1702 1703 return 0; 1704 } 1705 1706 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1707 { 1708 struct drm_device *ddev = encoder->dev; 1709 struct ltdc_device *ldev = ddev->dev_private; 1710 1711 DRM_DEBUG_DRIVER("\n"); 1712 1713 /* Disable LTDC */ 1714 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1715 1716 /* Set to sleep state the pinctrl whatever type of encoder */ 1717 pinctrl_pm_select_sleep_state(ddev->dev); 1718 } 1719 1720 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1721 { 1722 struct drm_device *ddev = encoder->dev; 1723 struct ltdc_device *ldev = ddev->dev_private; 1724 1725 DRM_DEBUG_DRIVER("\n"); 1726 1727 /* set fifo underrun threshold register */ 1728 if (ldev->caps.fifo_threshold) 1729 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold); 1730 1731 /* Enable LTDC */ 1732 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); 1733 } 1734 1735 static void ltdc_encoder_mode_set(struct drm_encoder *encoder, 1736 struct drm_display_mode *mode, 1737 struct drm_display_mode *adjusted_mode) 1738 { 1739 struct drm_device *ddev = encoder->dev; 1740 1741 DRM_DEBUG_DRIVER("\n"); 1742 1743 /* 1744 * Set to default state the pinctrl only with DPI type. 1745 * Others types like DSI, don't need pinctrl due to 1746 * internal bridge (the signals do not come out of the chipset). 1747 */ 1748 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1749 pinctrl_pm_select_default_state(ddev->dev); 1750 } 1751 1752 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1753 .disable = ltdc_encoder_disable, 1754 .enable = ltdc_encoder_enable, 1755 .mode_set = ltdc_encoder_mode_set, 1756 }; 1757 1758 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1759 { 1760 struct drm_encoder *encoder; 1761 int ret; 1762 1763 encoder = drmm_simple_encoder_alloc(ddev, struct drm_encoder, dev, 1764 DRM_MODE_ENCODER_DPI); 1765 if (IS_ERR(encoder)) 1766 return PTR_ERR(encoder); 1767 1768 encoder->possible_crtcs = CRTC_MASK; 1769 encoder->possible_clones = 0; /* No cloning support */ 1770 1771 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1772 1773 ret = drm_bridge_attach(encoder, bridge, NULL, 0); 1774 if (ret) 1775 return ret; 1776 1777 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1778 1779 return 0; 1780 } 1781 1782 static int ltdc_get_caps(struct drm_device *ddev) 1783 { 1784 struct ltdc_device *ldev = ddev->dev_private; 1785 u32 bus_width_log2, lcr, gc2r; 1786 1787 /* 1788 * at least 1 layer must be managed & the number of layers 1789 * must not exceed LTDC_MAX_LAYER 1790 */ 1791 regmap_read(ldev->regmap, LTDC_LCR, &lcr); 1792 1793 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1794 1795 /* set data bus width */ 1796 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r); 1797 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1798 ldev->caps.bus_width = 8 << bus_width_log2; 1799 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); 1800 1801 switch (ldev->caps.hw_version) { 1802 case HWVER_10200: 1803 case HWVER_10300: 1804 ldev->caps.layer_ofs = LAY_OFS_0; 1805 ldev->caps.layer_regs = ltdc_layer_regs_a0; 1806 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1807 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0; 1808 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0); 1809 ldev->caps.pix_fmt_flex = false; 1810 /* 1811 * Hw older versions support non-alpha color formats derived 1812 * from native alpha color formats only on the primary layer. 1813 * For instance, RG16 native format without alpha works fine 1814 * on 2nd layer but XR24 (derived color format from AR24) 1815 * does not work on 2nd layer. 1816 */ 1817 ldev->caps.non_alpha_only_l1 = true; 1818 ldev->caps.pad_max_freq_hz = 90000000; 1819 if (ldev->caps.hw_version == HWVER_10200) 1820 ldev->caps.pad_max_freq_hz = 65000000; 1821 ldev->caps.nb_irq = 2; 1822 ldev->caps.ycbcr_input = false; 1823 ldev->caps.ycbcr_output = false; 1824 ldev->caps.plane_reg_shadow = false; 1825 ldev->caps.crc = false; 1826 ldev->caps.dynamic_zorder = false; 1827 ldev->caps.plane_rotation = false; 1828 ldev->caps.fifo_threshold = false; 1829 break; 1830 case HWVER_20101: 1831 ldev->caps.layer_ofs = LAY_OFS_0; 1832 ldev->caps.layer_regs = ltdc_layer_regs_a1; 1833 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1834 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1; 1835 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1); 1836 ldev->caps.pix_fmt_flex = false; 1837 ldev->caps.non_alpha_only_l1 = false; 1838 ldev->caps.pad_max_freq_hz = 150000000; 1839 ldev->caps.nb_irq = 4; 1840 ldev->caps.ycbcr_input = false; 1841 ldev->caps.ycbcr_output = false; 1842 ldev->caps.plane_reg_shadow = false; 1843 ldev->caps.crc = false; 1844 ldev->caps.dynamic_zorder = false; 1845 ldev->caps.plane_rotation = false; 1846 ldev->caps.fifo_threshold = false; 1847 break; 1848 case HWVER_40100: 1849 ldev->caps.layer_ofs = LAY_OFS_1; 1850 ldev->caps.layer_regs = ltdc_layer_regs_a2; 1851 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; 1852 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2; 1853 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2); 1854 ldev->caps.pix_fmt_flex = true; 1855 ldev->caps.non_alpha_only_l1 = false; 1856 ldev->caps.pad_max_freq_hz = 90000000; 1857 ldev->caps.nb_irq = 2; 1858 ldev->caps.ycbcr_input = true; 1859 ldev->caps.ycbcr_output = true; 1860 ldev->caps.plane_reg_shadow = true; 1861 ldev->caps.crc = true; 1862 ldev->caps.dynamic_zorder = true; 1863 ldev->caps.plane_rotation = true; 1864 ldev->caps.fifo_threshold = true; 1865 break; 1866 default: 1867 return -ENODEV; 1868 } 1869 1870 return 0; 1871 } 1872 1873 void ltdc_suspend(struct drm_device *ddev) 1874 { 1875 struct ltdc_device *ldev = ddev->dev_private; 1876 1877 DRM_DEBUG_DRIVER("\n"); 1878 clk_disable_unprepare(ldev->pixel_clk); 1879 } 1880 1881 int ltdc_resume(struct drm_device *ddev) 1882 { 1883 struct ltdc_device *ldev = ddev->dev_private; 1884 int ret; 1885 1886 DRM_DEBUG_DRIVER("\n"); 1887 1888 ret = clk_prepare_enable(ldev->pixel_clk); 1889 if (ret) { 1890 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1891 return ret; 1892 } 1893 1894 return 0; 1895 } 1896 1897 int ltdc_load(struct drm_device *ddev) 1898 { 1899 struct platform_device *pdev = to_platform_device(ddev->dev); 1900 struct ltdc_device *ldev = ddev->dev_private; 1901 struct device *dev = ddev->dev; 1902 struct device_node *np = dev->of_node; 1903 struct drm_bridge *bridge; 1904 struct drm_panel *panel; 1905 struct drm_crtc *crtc; 1906 struct reset_control *rstc; 1907 struct resource *res; 1908 int irq, i, nb_endpoints; 1909 int ret = -ENODEV; 1910 1911 DRM_DEBUG_DRIVER("\n"); 1912 1913 /* Get number of endpoints */ 1914 nb_endpoints = of_graph_get_endpoint_count(np); 1915 if (!nb_endpoints) 1916 return -ENODEV; 1917 1918 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1919 if (IS_ERR(ldev->pixel_clk)) { 1920 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1921 DRM_ERROR("Unable to get lcd clock\n"); 1922 return PTR_ERR(ldev->pixel_clk); 1923 } 1924 1925 if (clk_prepare_enable(ldev->pixel_clk)) { 1926 DRM_ERROR("Unable to prepare pixel clock\n"); 1927 return -ENODEV; 1928 } 1929 1930 /* Get endpoints if any */ 1931 for (i = 0; i < nb_endpoints; i++) { 1932 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); 1933 1934 /* 1935 * If at least one endpoint is -ENODEV, continue probing, 1936 * else if at least one endpoint returned an error 1937 * (ie -EPROBE_DEFER) then stop probing. 1938 */ 1939 if (ret == -ENODEV) 1940 continue; 1941 else if (ret) 1942 goto err; 1943 1944 if (panel) { 1945 bridge = drmm_panel_bridge_add(ddev, panel); 1946 if (IS_ERR(bridge)) { 1947 DRM_ERROR("panel-bridge endpoint %d\n", i); 1948 ret = PTR_ERR(bridge); 1949 goto err; 1950 } 1951 } 1952 1953 if (bridge) { 1954 ret = ltdc_encoder_init(ddev, bridge); 1955 if (ret) { 1956 if (ret != -EPROBE_DEFER) 1957 DRM_ERROR("init encoder endpoint %d\n", i); 1958 goto err; 1959 } 1960 } 1961 } 1962 1963 rstc = devm_reset_control_get_exclusive(dev, NULL); 1964 1965 mutex_init(&ldev->err_lock); 1966 1967 if (!IS_ERR(rstc)) { 1968 reset_control_assert(rstc); 1969 usleep_range(10, 20); 1970 reset_control_deassert(rstc); 1971 } 1972 1973 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1974 ldev->regs = devm_ioremap_resource(dev, res); 1975 if (IS_ERR(ldev->regs)) { 1976 DRM_ERROR("Unable to get ltdc registers\n"); 1977 ret = PTR_ERR(ldev->regs); 1978 goto err; 1979 } 1980 1981 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); 1982 if (IS_ERR(ldev->regmap)) { 1983 DRM_ERROR("Unable to regmap ltdc registers\n"); 1984 ret = PTR_ERR(ldev->regmap); 1985 goto err; 1986 } 1987 1988 ret = ltdc_get_caps(ddev); 1989 if (ret) { 1990 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1991 ldev->caps.hw_version); 1992 goto err; 1993 } 1994 1995 /* Disable interrupts */ 1996 if (ldev->caps.fifo_threshold) 1997 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE | 1998 IER_TERRIE); 1999 else 2000 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE | 2001 IER_TERRIE | IER_FUEIE); 2002 2003 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 2004 2005 /* initialize default value for fifo underrun threshold & clear interrupt error counters */ 2006 ldev->transfer_err = 0; 2007 ldev->fifo_err = 0; 2008 ldev->fifo_warn = 0; 2009 ldev->fifo_threshold = FUT_DFT; 2010 2011 for (i = 0; i < ldev->caps.nb_irq; i++) { 2012 irq = platform_get_irq(pdev, i); 2013 if (irq < 0) { 2014 ret = irq; 2015 goto err; 2016 } 2017 2018 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 2019 ltdc_irq_thread, IRQF_ONESHOT, 2020 dev_name(dev), ddev); 2021 if (ret) { 2022 DRM_ERROR("Failed to register LTDC interrupt\n"); 2023 goto err; 2024 } 2025 } 2026 2027 crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL); 2028 if (!crtc) { 2029 DRM_ERROR("Failed to allocate crtc\n"); 2030 ret = -ENOMEM; 2031 goto err; 2032 } 2033 2034 ret = ltdc_crtc_init(ddev, crtc); 2035 if (ret) { 2036 DRM_ERROR("Failed to init crtc\n"); 2037 goto err; 2038 } 2039 2040 ret = drm_vblank_init(ddev, NB_CRTC); 2041 if (ret) { 2042 DRM_ERROR("Failed calling drm_vblank_init()\n"); 2043 goto err; 2044 } 2045 2046 clk_disable_unprepare(ldev->pixel_clk); 2047 2048 pinctrl_pm_select_sleep_state(ddev->dev); 2049 2050 pm_runtime_enable(ddev->dev); 2051 2052 return 0; 2053 err: 2054 clk_disable_unprepare(ldev->pixel_clk); 2055 2056 return ret; 2057 } 2058 2059 void ltdc_unload(struct drm_device *ddev) 2060 { 2061 DRM_DEBUG_DRIVER("\n"); 2062 2063 pm_runtime_disable(ddev->dev); 2064 } 2065 2066 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 2067 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 2068 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 2069 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 2070 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 2071 MODULE_LICENSE("GPL v2"); 2072