1 /* 2 * Copyright (C) STMicroelectronics SA 2017 3 * 4 * Authors: Philippe Cornu <philippe.cornu@st.com> 5 * Yannick Fertre <yannick.fertre@st.com> 6 * 7 * License terms: GNU General Public License (GPL), version 2 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <drm/drmP.h> 14 #include <drm/drm_mipi_dsi.h> 15 #include <drm/bridge/dw_mipi_dsi.h> 16 #include <video/mipi_display.h> 17 18 /* DSI wrapper register & bit definitions */ 19 /* Note: registers are named as in the Reference Manual */ 20 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */ 21 #define WCFGR_DSIM BIT(0) /* DSI Mode */ 22 #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */ 23 24 #define DSI_WCR 0x0404 /* Wrapper Control Reg */ 25 #define WCR_DSIEN BIT(3) /* DSI ENable */ 26 27 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */ 28 #define WISR_PLLLS BIT(8) /* PLL Lock Status */ 29 #define WISR_RRS BIT(12) /* Regulator Ready Status */ 30 31 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */ 32 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */ 33 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */ 34 35 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */ 36 #define WRPCR_PLLEN BIT(0) /* PLL ENable */ 37 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */ 38 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */ 39 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */ 40 #define WRPCR_REGEN BIT(24) /* REGulator ENable */ 41 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */ 42 #define IDF_MIN 1 43 #define IDF_MAX 7 44 #define NDIV_MIN 10 45 #define NDIV_MAX 125 46 #define ODF_MIN 1 47 #define ODF_MAX 8 48 49 /* dsi color format coding according to the datasheet */ 50 enum dsi_color { 51 DSI_RGB565_CONF1, 52 DSI_RGB565_CONF2, 53 DSI_RGB565_CONF3, 54 DSI_RGB666_CONF1, 55 DSI_RGB666_CONF2, 56 DSI_RGB888, 57 }; 58 59 #define LANE_MIN_KBPS 31250 60 #define LANE_MAX_KBPS 500000 61 62 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */ 63 #define SLEEP_US 1000 64 #define TIMEOUT_US 200000 65 66 struct dw_mipi_dsi_stm { 67 void __iomem *base; 68 struct clk *pllref_clk; 69 }; 70 71 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) 72 { 73 writel(val, dsi->base + reg); 74 } 75 76 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) 77 { 78 return readl(dsi->base + reg); 79 } 80 81 static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 82 { 83 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); 84 } 85 86 static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 87 { 88 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); 89 } 90 91 static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg, 92 u32 mask, u32 val) 93 { 94 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 95 } 96 97 static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt) 98 { 99 switch (fmt) { 100 case MIPI_DSI_FMT_RGB888: 101 return DSI_RGB888; 102 case MIPI_DSI_FMT_RGB666: 103 return DSI_RGB666_CONF2; 104 case MIPI_DSI_FMT_RGB666_PACKED: 105 return DSI_RGB666_CONF1; 106 case MIPI_DSI_FMT_RGB565: 107 return DSI_RGB565_CONF1; 108 default: 109 DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n"); 110 } 111 return DSI_RGB888; 112 } 113 114 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) 115 { 116 int divisor = idf * odf; 117 118 /* prevent from division by 0 */ 119 if (!divisor) 120 return 0; 121 122 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor); 123 } 124 125 static int dsi_pll_get_params(int clkin_khz, int clkout_khz, 126 int *idf, int *ndiv, int *odf) 127 { 128 int i, o, n, n_min, n_max; 129 int fvco_min, fvco_max, delta, best_delta; /* all in khz */ 130 131 /* Early checks preventing division by 0 & odd results */ 132 if ((clkin_khz <= 0) || (clkout_khz <= 0)) 133 return -EINVAL; 134 135 fvco_min = LANE_MIN_KBPS * 2 * ODF_MAX; 136 fvco_max = LANE_MAX_KBPS * 2 * ODF_MIN; 137 138 best_delta = 1000000; /* big started value (1000000khz) */ 139 140 for (i = IDF_MIN; i <= IDF_MAX; i++) { 141 /* Compute ndiv range according to Fvco */ 142 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1; 143 n_max = (fvco_max * i) / (2 * clkin_khz); 144 145 /* No need to continue idf loop if we reach ndiv max */ 146 if (n_min >= NDIV_MAX) 147 break; 148 149 /* Clamp ndiv to valid values */ 150 if (n_min < NDIV_MIN) 151 n_min = NDIV_MIN; 152 if (n_max > NDIV_MAX) 153 n_max = NDIV_MAX; 154 155 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) { 156 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz); 157 /* Check ndiv according to vco range */ 158 if ((n < n_min) || (n > n_max)) 159 continue; 160 /* Check if new delta is better & saves parameters */ 161 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) - 162 clkout_khz; 163 if (delta < 0) 164 delta = -delta; 165 if (delta < best_delta) { 166 *idf = i; 167 *ndiv = n; 168 *odf = o; 169 best_delta = delta; 170 } 171 /* fast return in case of "perfect result" */ 172 if (!delta) 173 return 0; 174 } 175 } 176 177 return 0; 178 } 179 180 static int dw_mipi_dsi_phy_init(void *priv_data) 181 { 182 struct dw_mipi_dsi_stm *dsi = priv_data; 183 u32 val; 184 int ret; 185 186 /* Enable the regulator */ 187 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); 188 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, 189 SLEEP_US, TIMEOUT_US); 190 if (ret) 191 DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n"); 192 193 /* Enable the DSI PLL & wait for its lock */ 194 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN); 195 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, 196 SLEEP_US, TIMEOUT_US); 197 if (ret) 198 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n"); 199 200 /* Enable the DSI wrapper */ 201 dsi_set(dsi, DSI_WCR, WCR_DSIEN); 202 203 return 0; 204 } 205 206 static int 207 dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode, 208 unsigned long mode_flags, u32 lanes, u32 format, 209 unsigned int *lane_mbps) 210 { 211 struct dw_mipi_dsi_stm *dsi = priv_data; 212 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; 213 int ret, bpp; 214 u32 val; 215 216 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000); 217 218 /* Compute requested pll out */ 219 bpp = mipi_dsi_pixel_format_to_bpp(format); 220 pll_out_khz = mode->clock * bpp / lanes; 221 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ 222 pll_out_khz = (pll_out_khz * 12) / 10; 223 if (pll_out_khz > LANE_MAX_KBPS) { 224 pll_out_khz = LANE_MAX_KBPS; 225 DRM_WARN("Warning max phy mbps is used\n"); 226 } 227 if (pll_out_khz < LANE_MIN_KBPS) { 228 pll_out_khz = LANE_MIN_KBPS; 229 DRM_WARN("Warning min phy mbps is used\n"); 230 } 231 232 /* Compute best pll parameters */ 233 idf = 0; 234 ndiv = 0; 235 odf = 0; 236 ret = dsi_pll_get_params(pll_in_khz, pll_out_khz, &idf, &ndiv, &odf); 237 if (ret) 238 DRM_WARN("Warning dsi_pll_get_params(): bad params\n"); 239 240 /* Get the adjusted pll out value */ 241 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); 242 243 /* Set the PLL division factors */ 244 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, 245 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); 246 247 /* Compute uix4 & set the bit period in high-speed mode */ 248 val = 4000000 / pll_out_khz; 249 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); 250 251 /* Select video mode by resetting DSIM bit */ 252 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM); 253 254 /* Select the color coding */ 255 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX, 256 dsi_color_from_mipi(format) << 1); 257 258 *lane_mbps = pll_out_khz / 1000; 259 260 DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", 261 pll_in_khz, pll_out_khz, *lane_mbps); 262 263 return 0; 264 } 265 266 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = { 267 .init = dw_mipi_dsi_phy_init, 268 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 269 }; 270 271 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = { 272 .max_data_lanes = 2, 273 .phy_ops = &dw_mipi_dsi_stm_phy_ops, 274 }; 275 276 static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = { 277 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, }, 278 { }, 279 }; 280 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids); 281 282 static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) 283 { 284 struct device *dev = &pdev->dev; 285 struct dw_mipi_dsi_stm *dsi; 286 struct resource *res; 287 int ret; 288 289 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 290 if (!dsi) 291 return -ENOMEM; 292 293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 294 if (!res) { 295 DRM_ERROR("Unable to get resource\n"); 296 return -ENODEV; 297 } 298 299 dsi->base = devm_ioremap_resource(dev, res); 300 if (IS_ERR(dsi->base)) { 301 DRM_ERROR("Unable to get dsi registers\n"); 302 return PTR_ERR(dsi->base); 303 } 304 305 dsi->pllref_clk = devm_clk_get(dev, "ref"); 306 if (IS_ERR(dsi->pllref_clk)) { 307 ret = PTR_ERR(dsi->pllref_clk); 308 dev_err(dev, "Unable to get pll reference clock: %d\n", ret); 309 return ret; 310 } 311 312 ret = clk_prepare_enable(dsi->pllref_clk); 313 if (ret) { 314 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); 315 return ret; 316 } 317 318 dw_mipi_dsi_stm_plat_data.base = dsi->base; 319 dw_mipi_dsi_stm_plat_data.priv_data = dsi; 320 321 ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data); 322 if (ret) { 323 DRM_ERROR("Failed to initialize mipi dsi host\n"); 324 clk_disable_unprepare(dsi->pllref_clk); 325 } 326 327 return ret; 328 } 329 330 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev) 331 { 332 struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; 333 334 clk_disable_unprepare(dsi->pllref_clk); 335 dw_mipi_dsi_remove(pdev); 336 337 return 0; 338 } 339 340 static struct platform_driver dw_mipi_dsi_stm_driver = { 341 .probe = dw_mipi_dsi_stm_probe, 342 .remove = dw_mipi_dsi_stm_remove, 343 .driver = { 344 .of_match_table = dw_mipi_dsi_stm_dt_ids, 345 .name = "dw_mipi_dsi-stm", 346 }, 347 }; 348 349 module_platform_driver(dw_mipi_dsi_stm_driver); 350 351 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 352 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 353 MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver"); 354 MODULE_LICENSE("GPL v2"); 355