1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics SA 2017
4  *
5  * Authors: Philippe Cornu <philippe.cornu@st.com>
6  *          Yannick Fertre <yannick.fertre@st.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/regulator/consumer.h>
13 #include <drm/drmP.h>
14 #include <drm/drm_mipi_dsi.h>
15 #include <drm/bridge/dw_mipi_dsi.h>
16 #include <video/mipi_display.h>
17 
18 #define HWVER_130			0x31333000	/* IP version 1.30 */
19 #define HWVER_131			0x31333100	/* IP version 1.31 */
20 
21 /* DSI digital registers & bit definitions */
22 #define DSI_VERSION			0x00
23 #define VERSION				GENMASK(31, 8)
24 
25 /* DSI wrapper registers & bit definitions */
26 /* Note: registers are named as in the Reference Manual */
27 #define DSI_WCFGR	0x0400		/* Wrapper ConFiGuration Reg */
28 #define WCFGR_DSIM	BIT(0)		/* DSI Mode */
29 #define WCFGR_COLMUX	GENMASK(3, 1)	/* COLor MUltipleXing */
30 
31 #define DSI_WCR		0x0404		/* Wrapper Control Reg */
32 #define WCR_DSIEN	BIT(3)		/* DSI ENable */
33 
34 #define DSI_WISR	0x040C		/* Wrapper Interrupt and Status Reg */
35 #define WISR_PLLLS	BIT(8)		/* PLL Lock Status */
36 #define WISR_RRS	BIT(12)		/* Regulator Ready Status */
37 
38 #define DSI_WPCR0	0x0418		/* Wrapper Phy Conf Reg 0 */
39 #define WPCR0_UIX4	GENMASK(5, 0)	/* Unit Interval X 4 */
40 #define WPCR0_TDDL	BIT(16)		/* Turn Disable Data Lanes */
41 
42 #define DSI_WRPCR	0x0430		/* Wrapper Regulator & Pll Ctrl Reg */
43 #define WRPCR_PLLEN	BIT(0)		/* PLL ENable */
44 #define WRPCR_NDIV	GENMASK(8, 2)	/* pll loop DIVision Factor */
45 #define WRPCR_IDF	GENMASK(14, 11)	/* pll Input Division Factor */
46 #define WRPCR_ODF	GENMASK(17, 16)	/* pll Output Division Factor */
47 #define WRPCR_REGEN	BIT(24)		/* REGulator ENable */
48 #define WRPCR_BGREN	BIT(28)		/* BandGap Reference ENable */
49 #define IDF_MIN		1
50 #define IDF_MAX		7
51 #define NDIV_MIN	10
52 #define NDIV_MAX	125
53 #define ODF_MIN		1
54 #define ODF_MAX		8
55 
56 /* dsi color format coding according to the datasheet */
57 enum dsi_color {
58 	DSI_RGB565_CONF1,
59 	DSI_RGB565_CONF2,
60 	DSI_RGB565_CONF3,
61 	DSI_RGB666_CONF1,
62 	DSI_RGB666_CONF2,
63 	DSI_RGB888,
64 };
65 
66 #define LANE_MIN_KBPS	31250
67 #define LANE_MAX_KBPS	500000
68 
69 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
70 #define SLEEP_US	1000
71 #define TIMEOUT_US	200000
72 
73 struct dw_mipi_dsi_stm {
74 	void __iomem *base;
75 	struct clk *pllref_clk;
76 	struct dw_mipi_dsi *dsi;
77 	u32 hw_version;
78 	int lane_min_kbps;
79 	int lane_max_kbps;
80 	struct regulator *vdd_supply;
81 };
82 
83 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
84 {
85 	writel(val, dsi->base + reg);
86 }
87 
88 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
89 {
90 	return readl(dsi->base + reg);
91 }
92 
93 static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
94 {
95 	dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
96 }
97 
98 static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
99 {
100 	dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
101 }
102 
103 static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
104 				   u32 mask, u32 val)
105 {
106 	dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
107 }
108 
109 static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
110 {
111 	switch (fmt) {
112 	case MIPI_DSI_FMT_RGB888:
113 		return DSI_RGB888;
114 	case MIPI_DSI_FMT_RGB666:
115 		return DSI_RGB666_CONF2;
116 	case MIPI_DSI_FMT_RGB666_PACKED:
117 		return DSI_RGB666_CONF1;
118 	case MIPI_DSI_FMT_RGB565:
119 		return DSI_RGB565_CONF1;
120 	default:
121 		DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
122 	}
123 	return DSI_RGB888;
124 }
125 
126 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
127 {
128 	int divisor = idf * odf;
129 
130 	/* prevent from division by 0 */
131 	if (!divisor)
132 		return 0;
133 
134 	return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
135 }
136 
137 static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi,
138 			      int clkin_khz, int clkout_khz,
139 			      int *idf, int *ndiv, int *odf)
140 {
141 	int i, o, n, n_min, n_max;
142 	int fvco_min, fvco_max, delta, best_delta; /* all in khz */
143 
144 	/* Early checks preventing division by 0 & odd results */
145 	if (clkin_khz <= 0 || clkout_khz <= 0)
146 		return -EINVAL;
147 
148 	fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
149 	fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
150 
151 	best_delta = 1000000; /* big started value (1000000khz) */
152 
153 	for (i = IDF_MIN; i <= IDF_MAX; i++) {
154 		/* Compute ndiv range according to Fvco */
155 		n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
156 		n_max = (fvco_max * i) / (2 * clkin_khz);
157 
158 		/* No need to continue idf loop if we reach ndiv max */
159 		if (n_min >= NDIV_MAX)
160 			break;
161 
162 		/* Clamp ndiv to valid values */
163 		if (n_min < NDIV_MIN)
164 			n_min = NDIV_MIN;
165 		if (n_max > NDIV_MAX)
166 			n_max = NDIV_MAX;
167 
168 		for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
169 			n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
170 			/* Check ndiv according to vco range */
171 			if (n < n_min || n > n_max)
172 				continue;
173 			/* Check if new delta is better & saves parameters */
174 			delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
175 				clkout_khz;
176 			if (delta < 0)
177 				delta = -delta;
178 			if (delta < best_delta) {
179 				*idf = i;
180 				*ndiv = n;
181 				*odf = o;
182 				best_delta = delta;
183 			}
184 			/* fast return in case of "perfect result" */
185 			if (!delta)
186 				return 0;
187 		}
188 	}
189 
190 	return 0;
191 }
192 
193 static int dw_mipi_dsi_phy_init(void *priv_data)
194 {
195 	struct dw_mipi_dsi_stm *dsi = priv_data;
196 	u32 val;
197 	int ret;
198 
199 	/* Enable the regulator */
200 	dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
201 	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
202 				 SLEEP_US, TIMEOUT_US);
203 	if (ret)
204 		DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
205 
206 	/* Enable the DSI PLL & wait for its lock */
207 	dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
208 	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
209 				 SLEEP_US, TIMEOUT_US);
210 	if (ret)
211 		DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
212 
213 	/* Enable the DSI wrapper */
214 	dsi_set(dsi, DSI_WCR, WCR_DSIEN);
215 
216 	return 0;
217 }
218 
219 static int
220 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
221 			  unsigned long mode_flags, u32 lanes, u32 format,
222 			  unsigned int *lane_mbps)
223 {
224 	struct dw_mipi_dsi_stm *dsi = priv_data;
225 	unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
226 	int ret, bpp;
227 	u32 val;
228 
229 	/* Update lane capabilities according to hw version */
230 	dsi->lane_min_kbps = LANE_MIN_KBPS;
231 	dsi->lane_max_kbps = LANE_MAX_KBPS;
232 	if (dsi->hw_version == HWVER_131) {
233 		dsi->lane_min_kbps *= 2;
234 		dsi->lane_max_kbps *= 2;
235 	}
236 
237 	pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
238 
239 	/* Compute requested pll out */
240 	bpp = mipi_dsi_pixel_format_to_bpp(format);
241 	pll_out_khz = mode->clock * bpp / lanes;
242 	/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
243 	pll_out_khz = (pll_out_khz * 12) / 10;
244 	if (pll_out_khz > dsi->lane_max_kbps) {
245 		pll_out_khz = dsi->lane_max_kbps;
246 		DRM_WARN("Warning max phy mbps is used\n");
247 	}
248 	if (pll_out_khz < dsi->lane_min_kbps) {
249 		pll_out_khz = dsi->lane_min_kbps;
250 		DRM_WARN("Warning min phy mbps is used\n");
251 	}
252 
253 	/* Compute best pll parameters */
254 	idf = 0;
255 	ndiv = 0;
256 	odf = 0;
257 	ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
258 				 &idf, &ndiv, &odf);
259 	if (ret)
260 		DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
261 
262 	/* Get the adjusted pll out value */
263 	pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
264 
265 	/* Set the PLL division factors */
266 	dsi_update_bits(dsi, DSI_WRPCR,	WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
267 			(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
268 
269 	/* Compute uix4 & set the bit period in high-speed mode */
270 	val = 4000000 / pll_out_khz;
271 	dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
272 
273 	/* Select video mode by resetting DSIM bit */
274 	dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
275 
276 	/* Select the color coding */
277 	dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
278 			dsi_color_from_mipi(format) << 1);
279 
280 	*lane_mbps = pll_out_khz / 1000;
281 
282 	DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
283 			 pll_in_khz, pll_out_khz, *lane_mbps);
284 
285 	return 0;
286 }
287 
288 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
289 	.init = dw_mipi_dsi_phy_init,
290 	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
291 };
292 
293 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
294 	.max_data_lanes = 2,
295 	.phy_ops = &dw_mipi_dsi_stm_phy_ops,
296 };
297 
298 static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = {
299 	{ .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
300 	{ },
301 };
302 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
303 
304 static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
305 {
306 	struct device *dev = &pdev->dev;
307 	struct dw_mipi_dsi_stm *dsi;
308 	struct clk *pclk;
309 	struct resource *res;
310 	int ret;
311 
312 	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
313 	if (!dsi)
314 		return -ENOMEM;
315 
316 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
317 	dsi->base = devm_ioremap_resource(dev, res);
318 	if (IS_ERR(dsi->base)) {
319 		ret = PTR_ERR(dsi->base);
320 		DRM_ERROR("Unable to get dsi registers %d\n", ret);
321 		return ret;
322 	}
323 
324 	dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi");
325 	if (IS_ERR(dsi->vdd_supply)) {
326 		ret = PTR_ERR(dsi->vdd_supply);
327 		if (ret != -EPROBE_DEFER)
328 			DRM_ERROR("Failed to request regulator: %d\n", ret);
329 		return ret;
330 	}
331 
332 	ret = regulator_enable(dsi->vdd_supply);
333 	if (ret) {
334 		DRM_ERROR("Failed to enable regulator: %d\n", ret);
335 		return ret;
336 	}
337 
338 	dsi->pllref_clk = devm_clk_get(dev, "ref");
339 	if (IS_ERR(dsi->pllref_clk)) {
340 		ret = PTR_ERR(dsi->pllref_clk);
341 		DRM_ERROR("Unable to get pll reference clock: %d\n", ret);
342 		goto err_clk_get;
343 	}
344 
345 	ret = clk_prepare_enable(dsi->pllref_clk);
346 	if (ret) {
347 		DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
348 		goto err_clk_get;
349 	}
350 
351 	pclk = devm_clk_get(dev, "pclk");
352 	if (IS_ERR(pclk)) {
353 		ret = PTR_ERR(pclk);
354 		DRM_ERROR("Unable to get peripheral clock: %d\n", ret);
355 		goto err_dsi_probe;
356 	}
357 
358 	ret = clk_prepare_enable(pclk);
359 	if (ret) {
360 		DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
361 		goto err_dsi_probe;
362 	}
363 
364 	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
365 	clk_disable_unprepare(pclk);
366 
367 	if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
368 		ret = -ENODEV;
369 		DRM_ERROR("bad dsi hardware version\n");
370 		goto err_dsi_probe;
371 	}
372 
373 	dw_mipi_dsi_stm_plat_data.base = dsi->base;
374 	dw_mipi_dsi_stm_plat_data.priv_data = dsi;
375 
376 	platform_set_drvdata(pdev, dsi);
377 
378 	dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
379 	if (IS_ERR(dsi->dsi)) {
380 		ret = PTR_ERR(dsi->dsi);
381 		DRM_ERROR("Failed to initialize mipi dsi host: %d\n", ret);
382 		goto err_dsi_probe;
383 	}
384 
385 	return 0;
386 
387 err_dsi_probe:
388 	clk_disable_unprepare(dsi->pllref_clk);
389 err_clk_get:
390 	regulator_disable(dsi->vdd_supply);
391 
392 	return ret;
393 }
394 
395 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
396 {
397 	struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev);
398 
399 	dw_mipi_dsi_remove(dsi->dsi);
400 	clk_disable_unprepare(dsi->pllref_clk);
401 	regulator_disable(dsi->vdd_supply);
402 
403 	return 0;
404 }
405 
406 static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev)
407 {
408 	struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
409 
410 	DRM_DEBUG_DRIVER("\n");
411 
412 	clk_disable_unprepare(dsi->pllref_clk);
413 	regulator_disable(dsi->vdd_supply);
414 
415 	return 0;
416 }
417 
418 static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev)
419 {
420 	struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
421 	int ret;
422 
423 	DRM_DEBUG_DRIVER("\n");
424 
425 	ret = regulator_enable(dsi->vdd_supply);
426 	if (ret) {
427 		DRM_ERROR("Failed to enable regulator: %d\n", ret);
428 		return ret;
429 	}
430 
431 	ret = clk_prepare_enable(dsi->pllref_clk);
432 	if (ret) {
433 		regulator_disable(dsi->vdd_supply);
434 		DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
435 		return ret;
436 	}
437 
438 	return 0;
439 }
440 
441 static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
442 	SET_SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
443 				dw_mipi_dsi_stm_resume)
444 };
445 
446 static struct platform_driver dw_mipi_dsi_stm_driver = {
447 	.probe		= dw_mipi_dsi_stm_probe,
448 	.remove		= dw_mipi_dsi_stm_remove,
449 	.driver		= {
450 		.of_match_table = dw_mipi_dsi_stm_dt_ids,
451 		.name	= "stm32-display-dsi",
452 		.pm = &dw_mipi_dsi_stm_pm_ops,
453 	},
454 };
455 
456 module_platform_driver(dw_mipi_dsi_stm_driver);
457 
458 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
459 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
460 MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver");
461 MODULE_LICENSE("GPL v2");
462