1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * Vincent Abriou <vincent.abriou@st.com> 6 * for STMicroelectronics. 7 * License terms: GNU General Public License (GPL), version 2 8 */ 9 10 #include <linux/module.h> 11 #include <linux/notifier.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 15 #include <drm/drmP.h> 16 17 #include "sti_drv.h" 18 #include "sti_vtg.h" 19 20 #define VTG_MODE_MASTER 0 21 22 /* registers offset */ 23 #define VTG_MODE 0x0000 24 #define VTG_CLKLN 0x0008 25 #define VTG_HLFLN 0x000C 26 #define VTG_DRST_AUTOC 0x0010 27 #define VTG_VID_TFO 0x0040 28 #define VTG_VID_TFS 0x0044 29 #define VTG_VID_BFO 0x0048 30 #define VTG_VID_BFS 0x004C 31 32 #define VTG_HOST_ITS 0x0078 33 #define VTG_HOST_ITS_BCLR 0x007C 34 #define VTG_HOST_ITM_BCLR 0x0088 35 #define VTG_HOST_ITM_BSET 0x008C 36 37 #define VTG_H_HD_1 0x00C0 38 #define VTG_TOP_V_VD_1 0x00C4 39 #define VTG_BOT_V_VD_1 0x00C8 40 #define VTG_TOP_V_HD_1 0x00CC 41 #define VTG_BOT_V_HD_1 0x00D0 42 43 #define VTG_H_HD_2 0x00E0 44 #define VTG_TOP_V_VD_2 0x00E4 45 #define VTG_BOT_V_VD_2 0x00E8 46 #define VTG_TOP_V_HD_2 0x00EC 47 #define VTG_BOT_V_HD_2 0x00F0 48 49 #define VTG_H_HD_3 0x0100 50 #define VTG_TOP_V_VD_3 0x0104 51 #define VTG_BOT_V_VD_3 0x0108 52 #define VTG_TOP_V_HD_3 0x010C 53 #define VTG_BOT_V_HD_3 0x0110 54 55 #define VTG_H_HD_4 0x0120 56 #define VTG_TOP_V_VD_4 0x0124 57 #define VTG_BOT_V_VD_4 0x0128 58 #define VTG_TOP_V_HD_4 0x012c 59 #define VTG_BOT_V_HD_4 0x0130 60 61 #define VTG_IRQ_BOTTOM BIT(0) 62 #define VTG_IRQ_TOP BIT(1) 63 #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) 64 65 /* Delay introduced by the HDMI in nb of pixel */ 66 #define HDMI_DELAY (5) 67 68 /* Delay introduced by the DVO in nb of pixel */ 69 #define DVO_DELAY (7) 70 71 /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ 72 #define AWG_DELAY_HD (-9) 73 #define AWG_DELAY_ED (-8) 74 #define AWG_DELAY_SD (-7) 75 76 /* 77 * STI VTG register offset structure 78 * 79 *@h_hd: stores the VTG_H_HD_x register offset 80 *@top_v_vd: stores the VTG_TOP_V_VD_x register offset 81 *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset 82 *@top_v_hd: stores the VTG_TOP_V_HD_x register offset 83 *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset 84 */ 85 struct sti_vtg_regs_offs { 86 u32 h_hd; 87 u32 top_v_vd; 88 u32 bot_v_vd; 89 u32 top_v_hd; 90 u32 bot_v_hd; 91 }; 92 93 #define VTG_MAX_SYNC_OUTPUT 4 94 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = { 95 { VTG_H_HD_1, 96 VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 }, 97 { VTG_H_HD_2, 98 VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 }, 99 { VTG_H_HD_3, 100 VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 }, 101 { VTG_H_HD_4, 102 VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 } 103 }; 104 105 /* 106 * STI VTG synchronisation parameters structure 107 * 108 *@hsync: sample number falling and rising edge 109 *@vsync_line_top: vertical top field line number falling and rising edge 110 *@vsync_line_bot: vertical bottom field line number falling and rising edge 111 *@vsync_off_top: vertical top field sample number rising and falling edge 112 *@vsync_off_bot: vertical bottom field sample number rising and falling edge 113 */ 114 struct sti_vtg_sync_params { 115 u32 hsync; 116 u32 vsync_line_top; 117 u32 vsync_line_bot; 118 u32 vsync_off_top; 119 u32 vsync_off_bot; 120 }; 121 122 /** 123 * STI VTG structure 124 * 125 * @regs: register mapping 126 * @sync_params: synchronisation parameters used to generate timings 127 * @irq: VTG irq 128 * @irq_status: store the IRQ status value 129 * @notifier_list: notifier callback 130 * @crtc: the CRTC for vblank event 131 */ 132 struct sti_vtg { 133 void __iomem *regs; 134 struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT]; 135 int irq; 136 u32 irq_status; 137 struct raw_notifier_head notifier_list; 138 struct drm_crtc *crtc; 139 }; 140 141 struct sti_vtg *of_vtg_find(struct device_node *np) 142 { 143 struct platform_device *pdev; 144 145 pdev = of_find_device_by_node(np); 146 if (!pdev) 147 return NULL; 148 149 return (struct sti_vtg *)platform_get_drvdata(pdev); 150 } 151 152 static void vtg_reset(struct sti_vtg *vtg) 153 { 154 writel(1, vtg->regs + VTG_DRST_AUTOC); 155 } 156 157 static void vtg_set_output_window(void __iomem *regs, 158 const struct drm_display_mode *mode) 159 { 160 u32 video_top_field_start; 161 u32 video_top_field_stop; 162 u32 video_bottom_field_start; 163 u32 video_bottom_field_stop; 164 u32 xstart = sti_vtg_get_pixel_number(*mode, 0); 165 u32 ystart = sti_vtg_get_line_number(*mode, 0); 166 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 167 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 168 169 /* Set output window to fit the display mode selected */ 170 video_top_field_start = (ystart << 16) | xstart; 171 video_top_field_stop = (ystop << 16) | xstop; 172 173 /* Only progressive supported for now */ 174 video_bottom_field_start = video_top_field_start; 175 video_bottom_field_stop = video_top_field_stop; 176 177 writel(video_top_field_start, regs + VTG_VID_TFO); 178 writel(video_top_field_stop, regs + VTG_VID_TFS); 179 writel(video_bottom_field_start, regs + VTG_VID_BFO); 180 writel(video_bottom_field_stop, regs + VTG_VID_BFS); 181 } 182 183 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync, 184 int delay, 185 const struct drm_display_mode *mode) 186 { 187 long clocksperline, start, stop; 188 u32 risesync_top, fallsync_top; 189 u32 risesync_offs_top, fallsync_offs_top; 190 191 clocksperline = mode->htotal; 192 193 /* Get the hsync position */ 194 start = 0; 195 stop = mode->hsync_end - mode->hsync_start; 196 197 start += delay; 198 stop += delay; 199 200 if (start < 0) 201 start += clocksperline; 202 else if (start >= clocksperline) 203 start -= clocksperline; 204 205 if (stop < 0) 206 stop += clocksperline; 207 else if (stop >= clocksperline) 208 stop -= clocksperline; 209 210 sync->hsync = (stop << 16) | start; 211 212 /* Get the vsync position */ 213 if (delay >= 0) { 214 risesync_top = 1; 215 fallsync_top = risesync_top; 216 fallsync_top += mode->vsync_end - mode->vsync_start; 217 218 fallsync_offs_top = (u32)delay; 219 risesync_offs_top = (u32)delay; 220 } else { 221 risesync_top = mode->vtotal; 222 fallsync_top = mode->vsync_end - mode->vsync_start; 223 224 fallsync_offs_top = clocksperline + delay; 225 risesync_offs_top = clocksperline + delay; 226 } 227 228 sync->vsync_line_top = (fallsync_top << 16) | risesync_top; 229 sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top; 230 231 /* Only progressive supported for now */ 232 sync->vsync_line_bot = sync->vsync_line_top; 233 sync->vsync_off_bot = sync->vsync_off_top; 234 } 235 236 static void vtg_set_mode(struct sti_vtg *vtg, 237 int type, 238 struct sti_vtg_sync_params *sync, 239 const struct drm_display_mode *mode) 240 { 241 unsigned int i; 242 243 /* Set the number of clock cycles per line */ 244 writel(mode->htotal, vtg->regs + VTG_CLKLN); 245 246 /* Set Half Line Per Field (only progressive supported for now) */ 247 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); 248 249 /* Program output window */ 250 vtg_set_output_window(vtg->regs, mode); 251 252 /* Set hsync and vsync position for HDMI */ 253 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode); 254 255 /* Set hsync and vsync position for HD DCS */ 256 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode); 257 258 /* Set hsync and vsync position for HDF */ 259 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode); 260 261 /* Set hsync and vsync position for DVO */ 262 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode); 263 264 /* Progam the syncs outputs */ 265 for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) { 266 writel(sync[i].hsync, 267 vtg->regs + vtg_regs_offs[i].h_hd); 268 writel(sync[i].vsync_line_top, 269 vtg->regs + vtg_regs_offs[i].top_v_vd); 270 writel(sync[i].vsync_line_bot, 271 vtg->regs + vtg_regs_offs[i].bot_v_vd); 272 writel(sync[i].vsync_off_top, 273 vtg->regs + vtg_regs_offs[i].top_v_hd); 274 writel(sync[i].vsync_off_bot, 275 vtg->regs + vtg_regs_offs[i].bot_v_hd); 276 } 277 278 /* mode */ 279 writel(type, vtg->regs + VTG_MODE); 280 } 281 282 static void vtg_enable_irq(struct sti_vtg *vtg) 283 { 284 /* clear interrupt status and mask */ 285 writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR); 286 writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR); 287 writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET); 288 } 289 290 void sti_vtg_set_config(struct sti_vtg *vtg, 291 const struct drm_display_mode *mode) 292 { 293 /* write configuration */ 294 vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode); 295 296 vtg_reset(vtg); 297 298 vtg_enable_irq(vtg); 299 } 300 301 /** 302 * sti_vtg_get_line_number 303 * 304 * @mode: display mode to be used 305 * @y: line 306 * 307 * Return the line number according to the display mode taking 308 * into account the Sync and Back Porch information. 309 * Video frame line numbers start at 1, y starts at 0. 310 * In interlaced modes the start line is the field line number of the odd 311 * field, but y is still defined as a progressive frame. 312 */ 313 u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y) 314 { 315 u32 start_line = mode.vtotal - mode.vsync_start + 1; 316 317 if (mode.flags & DRM_MODE_FLAG_INTERLACE) 318 start_line *= 2; 319 320 return start_line + y; 321 } 322 323 /** 324 * sti_vtg_get_pixel_number 325 * 326 * @mode: display mode to be used 327 * @x: row 328 * 329 * Return the pixel number according to the display mode taking 330 * into account the Sync and Back Porch information. 331 * Pixels are counted from 0. 332 */ 333 u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x) 334 { 335 return mode.htotal - mode.hsync_start + x; 336 } 337 338 int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb, 339 struct drm_crtc *crtc) 340 { 341 vtg->crtc = crtc; 342 return raw_notifier_chain_register(&vtg->notifier_list, nb); 343 } 344 345 int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb) 346 { 347 return raw_notifier_chain_unregister(&vtg->notifier_list, nb); 348 } 349 350 static irqreturn_t vtg_irq_thread(int irq, void *arg) 351 { 352 struct sti_vtg *vtg = arg; 353 u32 event; 354 355 event = (vtg->irq_status & VTG_IRQ_TOP) ? 356 VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT; 357 358 raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc); 359 360 return IRQ_HANDLED; 361 } 362 363 static irqreturn_t vtg_irq(int irq, void *arg) 364 { 365 struct sti_vtg *vtg = arg; 366 367 vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS); 368 369 writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR); 370 371 /* force sync bus write */ 372 readl(vtg->regs + VTG_HOST_ITS); 373 374 return IRQ_WAKE_THREAD; 375 } 376 377 static int vtg_probe(struct platform_device *pdev) 378 { 379 struct device *dev = &pdev->dev; 380 struct sti_vtg *vtg; 381 struct resource *res; 382 int ret; 383 384 vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL); 385 if (!vtg) 386 return -ENOMEM; 387 388 /* Get Memory ressources */ 389 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 390 if (!res) { 391 DRM_ERROR("Get memory resource failed\n"); 392 return -ENOMEM; 393 } 394 vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); 395 if (!vtg->regs) { 396 DRM_ERROR("failed to remap I/O memory\n"); 397 return -ENOMEM; 398 } 399 400 vtg->irq = platform_get_irq(pdev, 0); 401 if (vtg->irq < 0) { 402 DRM_ERROR("Failed to get VTG interrupt\n"); 403 return vtg->irq; 404 } 405 406 RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list); 407 408 ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq, 409 vtg_irq_thread, IRQF_ONESHOT, 410 dev_name(dev), vtg); 411 if (ret < 0) { 412 DRM_ERROR("Failed to register VTG interrupt\n"); 413 return ret; 414 } 415 416 platform_set_drvdata(pdev, vtg); 417 418 DRM_INFO("%s %s\n", __func__, dev_name(dev)); 419 420 return 0; 421 } 422 423 static const struct of_device_id vtg_of_match[] = { 424 { .compatible = "st,vtg", }, 425 { /* sentinel */ } 426 }; 427 MODULE_DEVICE_TABLE(of, vtg_of_match); 428 429 struct platform_driver sti_vtg_driver = { 430 .driver = { 431 .name = "sti-vtg", 432 .owner = THIS_MODULE, 433 .of_match_table = vtg_of_match, 434 }, 435 .probe = vtg_probe, 436 }; 437 438 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 439 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 440 MODULE_LICENSE("GPL"); 441