1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * Vincent Abriou <vincent.abriou@st.com> 6 * for STMicroelectronics. 7 * License terms: GNU General Public License (GPL), version 2 8 */ 9 10 #include <linux/module.h> 11 #include <linux/notifier.h> 12 #include <linux/platform_device.h> 13 14 #include <drm/drmP.h> 15 16 #include "sti_vtg.h" 17 18 #define VTG_MODE_MASTER 0 19 #define VTG_MODE_SLAVE_BY_EXT0 1 20 21 /* registers offset */ 22 #define VTG_MODE 0x0000 23 #define VTG_CLKLN 0x0008 24 #define VTG_HLFLN 0x000C 25 #define VTG_DRST_AUTOC 0x0010 26 #define VTG_VID_TFO 0x0040 27 #define VTG_VID_TFS 0x0044 28 #define VTG_VID_BFO 0x0048 29 #define VTG_VID_BFS 0x004C 30 31 #define VTG_HOST_ITS 0x0078 32 #define VTG_HOST_ITS_BCLR 0x007C 33 #define VTG_HOST_ITM_BCLR 0x0088 34 #define VTG_HOST_ITM_BSET 0x008C 35 36 #define VTG_H_HD_1 0x00C0 37 #define VTG_TOP_V_VD_1 0x00C4 38 #define VTG_BOT_V_VD_1 0x00C8 39 #define VTG_TOP_V_HD_1 0x00CC 40 #define VTG_BOT_V_HD_1 0x00D0 41 42 #define VTG_H_HD_2 0x00E0 43 #define VTG_TOP_V_VD_2 0x00E4 44 #define VTG_BOT_V_VD_2 0x00E8 45 #define VTG_TOP_V_HD_2 0x00EC 46 #define VTG_BOT_V_HD_2 0x00F0 47 48 #define VTG_H_HD_3 0x0100 49 #define VTG_TOP_V_VD_3 0x0104 50 #define VTG_BOT_V_VD_3 0x0108 51 #define VTG_TOP_V_HD_3 0x010C 52 #define VTG_BOT_V_HD_3 0x0110 53 54 #define VTG_H_HD_4 0x0120 55 #define VTG_TOP_V_VD_4 0x0124 56 #define VTG_BOT_V_VD_4 0x0128 57 #define VTG_TOP_V_HD_4 0x012c 58 #define VTG_BOT_V_HD_4 0x0130 59 60 #define VTG_IRQ_BOTTOM BIT(0) 61 #define VTG_IRQ_TOP BIT(1) 62 #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) 63 64 /* Delay introduced by the HDMI in nb of pixel */ 65 #define HDMI_DELAY (5) 66 67 /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ 68 #define AWG_DELAY_HD (-9) 69 #define AWG_DELAY_ED (-8) 70 #define AWG_DELAY_SD (-7) 71 72 LIST_HEAD(vtg_lookup); 73 74 /* 75 * STI VTG register offset structure 76 * 77 *@h_hd: stores the VTG_H_HD_x register offset 78 *@top_v_vd: stores the VTG_TOP_V_VD_x register offset 79 *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset 80 *@top_v_hd: stores the VTG_TOP_V_HD_x register offset 81 *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset 82 */ 83 struct sti_vtg_regs_offs { 84 u32 h_hd; 85 u32 top_v_vd; 86 u32 bot_v_vd; 87 u32 top_v_hd; 88 u32 bot_v_hd; 89 }; 90 91 #define VTG_MAX_SYNC_OUTPUT 4 92 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = { 93 { VTG_H_HD_1, 94 VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 }, 95 { VTG_H_HD_2, 96 VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 }, 97 { VTG_H_HD_3, 98 VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 }, 99 { VTG_H_HD_4, 100 VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 } 101 }; 102 103 /* 104 * STI VTG synchronisation parameters structure 105 * 106 *@hsync: sample number falling and rising edge 107 *@vsync_line_top: vertical top field line number falling and rising edge 108 *@vsync_line_bot: vertical bottom field line number falling and rising edge 109 *@vsync_off_top: vertical top field sample number rising and falling edge 110 *@vsync_off_bot: vertical bottom field sample number rising and falling edge 111 */ 112 struct sti_vtg_sync_params { 113 u32 hsync; 114 u32 vsync_line_top; 115 u32 vsync_line_bot; 116 u32 vsync_off_top; 117 u32 vsync_off_bot; 118 }; 119 120 /** 121 * STI VTG structure 122 * 123 * @dev: pointer to device driver 124 * @np: device node 125 * @regs: register mapping 126 * @sync_params: synchronisation parameters used to generate timings 127 * @irq: VTG irq 128 * @irq_status: store the IRQ status value 129 * @notifier_list: notifier callback 130 * @crtc: the CRTC for vblank event 131 * @slave: slave vtg 132 * @link: List node to link the structure in lookup list 133 */ 134 struct sti_vtg { 135 struct device *dev; 136 struct device_node *np; 137 void __iomem *regs; 138 struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT]; 139 int irq; 140 u32 irq_status; 141 struct raw_notifier_head notifier_list; 142 struct drm_crtc *crtc; 143 struct sti_vtg *slave; 144 struct list_head link; 145 }; 146 147 static void vtg_register(struct sti_vtg *vtg) 148 { 149 list_add_tail(&vtg->link, &vtg_lookup); 150 } 151 152 struct sti_vtg *of_vtg_find(struct device_node *np) 153 { 154 struct sti_vtg *vtg; 155 156 list_for_each_entry(vtg, &vtg_lookup, link) { 157 if (vtg->np == np) 158 return vtg; 159 } 160 return NULL; 161 } 162 163 static void vtg_reset(struct sti_vtg *vtg) 164 { 165 /* reset slave and then master */ 166 if (vtg->slave) 167 vtg_reset(vtg->slave); 168 169 writel(1, vtg->regs + VTG_DRST_AUTOC); 170 } 171 172 static void vtg_set_output_window(void __iomem *regs, 173 const struct drm_display_mode *mode) 174 { 175 u32 video_top_field_start; 176 u32 video_top_field_stop; 177 u32 video_bottom_field_start; 178 u32 video_bottom_field_stop; 179 u32 xstart = sti_vtg_get_pixel_number(*mode, 0); 180 u32 ystart = sti_vtg_get_line_number(*mode, 0); 181 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 182 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 183 184 /* Set output window to fit the display mode selected */ 185 video_top_field_start = (ystart << 16) | xstart; 186 video_top_field_stop = (ystop << 16) | xstop; 187 188 /* Only progressive supported for now */ 189 video_bottom_field_start = video_top_field_start; 190 video_bottom_field_stop = video_top_field_stop; 191 192 writel(video_top_field_start, regs + VTG_VID_TFO); 193 writel(video_top_field_stop, regs + VTG_VID_TFS); 194 writel(video_bottom_field_start, regs + VTG_VID_BFO); 195 writel(video_bottom_field_stop, regs + VTG_VID_BFS); 196 } 197 198 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync, 199 int delay, 200 const struct drm_display_mode *mode) 201 { 202 long clocksperline, start, stop; 203 u32 risesync_top, fallsync_top; 204 u32 risesync_offs_top, fallsync_offs_top; 205 206 clocksperline = mode->htotal; 207 208 /* Get the hsync position */ 209 start = 0; 210 stop = mode->hsync_end - mode->hsync_start; 211 212 start += delay; 213 stop += delay; 214 215 if (start < 0) 216 start += clocksperline; 217 else if (start >= clocksperline) 218 start -= clocksperline; 219 220 if (stop < 0) 221 stop += clocksperline; 222 else if (stop >= clocksperline) 223 stop -= clocksperline; 224 225 sync->hsync = (stop << 16) | start; 226 227 /* Get the vsync position */ 228 if (delay >= 0) { 229 risesync_top = 1; 230 fallsync_top = risesync_top; 231 fallsync_top += mode->vsync_end - mode->vsync_start; 232 233 fallsync_offs_top = (u32)delay; 234 risesync_offs_top = (u32)delay; 235 } else { 236 risesync_top = mode->vtotal; 237 fallsync_top = mode->vsync_end - mode->vsync_start; 238 239 fallsync_offs_top = clocksperline + delay; 240 risesync_offs_top = clocksperline + delay; 241 } 242 243 sync->vsync_line_top = (fallsync_top << 16) | risesync_top; 244 sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top; 245 246 /* Only progressive supported for now */ 247 sync->vsync_line_bot = sync->vsync_line_top; 248 sync->vsync_off_bot = sync->vsync_off_top; 249 } 250 251 static void vtg_set_mode(struct sti_vtg *vtg, 252 int type, 253 struct sti_vtg_sync_params *sync, 254 const struct drm_display_mode *mode) 255 { 256 unsigned int i; 257 258 if (vtg->slave) 259 vtg_set_mode(vtg->slave, VTG_MODE_SLAVE_BY_EXT0, 260 vtg->sync_params, mode); 261 262 /* Set the number of clock cycles per line */ 263 writel(mode->htotal, vtg->regs + VTG_CLKLN); 264 265 /* Set Half Line Per Field (only progressive supported for now) */ 266 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); 267 268 /* Program output window */ 269 vtg_set_output_window(vtg->regs, mode); 270 271 /* Set hsync and vsync position for HDMI */ 272 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode); 273 274 /* Set hsync and vsync position for HD DCS */ 275 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode); 276 277 /* Set hsync and vsync position for HDF */ 278 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode); 279 280 /* Set hsync and vsync position for DVO */ 281 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], 0, mode); 282 283 /* Progam the syncs outputs */ 284 for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) { 285 writel(sync[i].hsync, 286 vtg->regs + vtg_regs_offs[i].h_hd); 287 writel(sync[i].vsync_line_top, 288 vtg->regs + vtg_regs_offs[i].top_v_vd); 289 writel(sync[i].vsync_line_bot, 290 vtg->regs + vtg_regs_offs[i].bot_v_vd); 291 writel(sync[i].vsync_off_top, 292 vtg->regs + vtg_regs_offs[i].top_v_hd); 293 writel(sync[i].vsync_off_bot, 294 vtg->regs + vtg_regs_offs[i].bot_v_hd); 295 } 296 297 /* mode */ 298 writel(type, vtg->regs + VTG_MODE); 299 } 300 301 static void vtg_enable_irq(struct sti_vtg *vtg) 302 { 303 /* clear interrupt status and mask */ 304 writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR); 305 writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR); 306 writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET); 307 } 308 309 void sti_vtg_set_config(struct sti_vtg *vtg, 310 const struct drm_display_mode *mode) 311 { 312 /* write configuration */ 313 vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode); 314 315 vtg_reset(vtg); 316 317 /* enable irq for the vtg vblank synchro */ 318 if (vtg->slave) 319 vtg_enable_irq(vtg->slave); 320 else 321 vtg_enable_irq(vtg); 322 } 323 324 /** 325 * sti_vtg_get_line_number 326 * 327 * @mode: display mode to be used 328 * @y: line 329 * 330 * Return the line number according to the display mode taking 331 * into account the Sync and Back Porch information. 332 * Video frame line numbers start at 1, y starts at 0. 333 * In interlaced modes the start line is the field line number of the odd 334 * field, but y is still defined as a progressive frame. 335 */ 336 u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y) 337 { 338 u32 start_line = mode.vtotal - mode.vsync_start + 1; 339 340 if (mode.flags & DRM_MODE_FLAG_INTERLACE) 341 start_line *= 2; 342 343 return start_line + y; 344 } 345 346 /** 347 * sti_vtg_get_pixel_number 348 * 349 * @mode: display mode to be used 350 * @x: row 351 * 352 * Return the pixel number according to the display mode taking 353 * into account the Sync and Back Porch information. 354 * Pixels are counted from 0. 355 */ 356 u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x) 357 { 358 return mode.htotal - mode.hsync_start + x; 359 } 360 361 int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb, 362 struct drm_crtc *crtc) 363 { 364 if (vtg->slave) 365 return sti_vtg_register_client(vtg->slave, nb, crtc); 366 367 vtg->crtc = crtc; 368 return raw_notifier_chain_register(&vtg->notifier_list, nb); 369 } 370 371 int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb) 372 { 373 if (vtg->slave) 374 return sti_vtg_unregister_client(vtg->slave, nb); 375 376 return raw_notifier_chain_unregister(&vtg->notifier_list, nb); 377 } 378 379 static irqreturn_t vtg_irq_thread(int irq, void *arg) 380 { 381 struct sti_vtg *vtg = arg; 382 u32 event; 383 384 event = (vtg->irq_status & VTG_IRQ_TOP) ? 385 VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT; 386 387 raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc); 388 389 return IRQ_HANDLED; 390 } 391 392 static irqreturn_t vtg_irq(int irq, void *arg) 393 { 394 struct sti_vtg *vtg = arg; 395 396 vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS); 397 398 writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR); 399 400 /* force sync bus write */ 401 readl(vtg->regs + VTG_HOST_ITS); 402 403 return IRQ_WAKE_THREAD; 404 } 405 406 static int vtg_probe(struct platform_device *pdev) 407 { 408 struct device *dev = &pdev->dev; 409 struct device_node *np; 410 struct sti_vtg *vtg; 411 struct resource *res; 412 int ret; 413 414 vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL); 415 if (!vtg) 416 return -ENOMEM; 417 418 vtg->dev = dev; 419 vtg->np = pdev->dev.of_node; 420 421 /* Get Memory ressources */ 422 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 423 if (!res) { 424 DRM_ERROR("Get memory resource failed\n"); 425 return -ENOMEM; 426 } 427 vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); 428 429 np = of_parse_phandle(pdev->dev.of_node, "st,slave", 0); 430 if (np) { 431 vtg->slave = of_vtg_find(np); 432 433 if (!vtg->slave) 434 return -EPROBE_DEFER; 435 } else { 436 vtg->irq = platform_get_irq(pdev, 0); 437 if (IS_ERR_VALUE(vtg->irq)) { 438 DRM_ERROR("Failed to get VTG interrupt\n"); 439 return vtg->irq; 440 } 441 442 RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list); 443 444 ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq, 445 vtg_irq_thread, IRQF_ONESHOT, 446 dev_name(dev), vtg); 447 if (IS_ERR_VALUE(ret)) { 448 DRM_ERROR("Failed to register VTG interrupt\n"); 449 return ret; 450 } 451 } 452 453 vtg_register(vtg); 454 platform_set_drvdata(pdev, vtg); 455 456 DRM_INFO("%s %s\n", __func__, dev_name(vtg->dev)); 457 458 return 0; 459 } 460 461 static int vtg_remove(struct platform_device *pdev) 462 { 463 return 0; 464 } 465 466 static const struct of_device_id vtg_of_match[] = { 467 { .compatible = "st,vtg", }, 468 { /* sentinel */ } 469 }; 470 MODULE_DEVICE_TABLE(of, vtg_of_match); 471 472 struct platform_driver sti_vtg_driver = { 473 .driver = { 474 .name = "sti-vtg", 475 .owner = THIS_MODULE, 476 .of_match_table = vtg_of_match, 477 }, 478 .probe = vtg_probe, 479 .remove = vtg_remove, 480 }; 481 482 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 483 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 484 MODULE_LICENSE("GPL"); 485