1f2cb3148SBenjamin Gaignard /* 2f2cb3148SBenjamin Gaignard * Copyright (C) STMicroelectronics SA 2014 3f2cb3148SBenjamin Gaignard * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4f2cb3148SBenjamin Gaignard * Fabien Dessenne <fabien.dessenne@st.com> 5f2cb3148SBenjamin Gaignard * Vincent Abriou <vincent.abriou@st.com> 6f2cb3148SBenjamin Gaignard * for STMicroelectronics. 7f2cb3148SBenjamin Gaignard * License terms: GNU General Public License (GPL), version 2 8f2cb3148SBenjamin Gaignard */ 9f2cb3148SBenjamin Gaignard 10f2cb3148SBenjamin Gaignard #include <linux/module.h> 11f2cb3148SBenjamin Gaignard #include <linux/notifier.h> 12f2cb3148SBenjamin Gaignard #include <linux/platform_device.h> 13f2cb3148SBenjamin Gaignard 14f2cb3148SBenjamin Gaignard #include <drm/drmP.h> 15f2cb3148SBenjamin Gaignard 16f2cb3148SBenjamin Gaignard #include "sti_vtg.h" 17f2cb3148SBenjamin Gaignard 18f2cb3148SBenjamin Gaignard #define VTG_TYPE_MASTER 0 19f2cb3148SBenjamin Gaignard #define VTG_TYPE_SLAVE_BY_EXT0 1 20f2cb3148SBenjamin Gaignard 21f2cb3148SBenjamin Gaignard /* registers offset */ 22f2cb3148SBenjamin Gaignard #define VTG_MODE 0x0000 23f2cb3148SBenjamin Gaignard #define VTG_CLKLN 0x0008 24f2cb3148SBenjamin Gaignard #define VTG_HLFLN 0x000C 25f2cb3148SBenjamin Gaignard #define VTG_DRST_AUTOC 0x0010 26f2cb3148SBenjamin Gaignard #define VTG_VID_TFO 0x0040 27f2cb3148SBenjamin Gaignard #define VTG_VID_TFS 0x0044 28f2cb3148SBenjamin Gaignard #define VTG_VID_BFO 0x0048 29f2cb3148SBenjamin Gaignard #define VTG_VID_BFS 0x004C 30f2cb3148SBenjamin Gaignard 31f2cb3148SBenjamin Gaignard #define VTG_HOST_ITS 0x0078 32f2cb3148SBenjamin Gaignard #define VTG_HOST_ITS_BCLR 0x007C 33f2cb3148SBenjamin Gaignard #define VTG_HOST_ITM_BCLR 0x0088 34f2cb3148SBenjamin Gaignard #define VTG_HOST_ITM_BSET 0x008C 35f2cb3148SBenjamin Gaignard 36f2cb3148SBenjamin Gaignard #define VTG_H_HD_1 0x00C0 37f2cb3148SBenjamin Gaignard #define VTG_TOP_V_VD_1 0x00C4 38f2cb3148SBenjamin Gaignard #define VTG_BOT_V_VD_1 0x00C8 39f2cb3148SBenjamin Gaignard #define VTG_TOP_V_HD_1 0x00CC 40f2cb3148SBenjamin Gaignard #define VTG_BOT_V_HD_1 0x00D0 41f2cb3148SBenjamin Gaignard 42f2cb3148SBenjamin Gaignard #define VTG_H_HD_2 0x00E0 43f2cb3148SBenjamin Gaignard #define VTG_TOP_V_VD_2 0x00E4 44f2cb3148SBenjamin Gaignard #define VTG_BOT_V_VD_2 0x00E8 45f2cb3148SBenjamin Gaignard #define VTG_TOP_V_HD_2 0x00EC 46f2cb3148SBenjamin Gaignard #define VTG_BOT_V_HD_2 0x00F0 47f2cb3148SBenjamin Gaignard 48f2cb3148SBenjamin Gaignard #define VTG_H_HD_3 0x0100 49f2cb3148SBenjamin Gaignard #define VTG_TOP_V_VD_3 0x0104 50f2cb3148SBenjamin Gaignard #define VTG_BOT_V_VD_3 0x0108 51f2cb3148SBenjamin Gaignard #define VTG_TOP_V_HD_3 0x010C 52f2cb3148SBenjamin Gaignard #define VTG_BOT_V_HD_3 0x0110 53f2cb3148SBenjamin Gaignard 54f2cb3148SBenjamin Gaignard #define VTG_IRQ_BOTTOM BIT(0) 55f2cb3148SBenjamin Gaignard #define VTG_IRQ_TOP BIT(1) 56f2cb3148SBenjamin Gaignard #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) 57f2cb3148SBenjamin Gaignard 58f2cb3148SBenjamin Gaignard /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ 59f2cb3148SBenjamin Gaignard #define AWG_DELAY_HD (-9) 60f2cb3148SBenjamin Gaignard #define AWG_DELAY_ED (-8) 61f2cb3148SBenjamin Gaignard #define AWG_DELAY_SD (-7) 62f2cb3148SBenjamin Gaignard 63f2cb3148SBenjamin Gaignard LIST_HEAD(vtg_lookup); 64f2cb3148SBenjamin Gaignard 65f2cb3148SBenjamin Gaignard /** 66f2cb3148SBenjamin Gaignard * STI VTG structure 67f2cb3148SBenjamin Gaignard * 68f2cb3148SBenjamin Gaignard * @dev: pointer to device driver 69f2cb3148SBenjamin Gaignard * @data: data associated to the device 70f2cb3148SBenjamin Gaignard * @irq: VTG irq 71f2cb3148SBenjamin Gaignard * @type: VTG type (main or aux) 72f2cb3148SBenjamin Gaignard * @notifier_list: notifier callback 73f2cb3148SBenjamin Gaignard * @crtc_id: the crtc id for vblank event 74f2cb3148SBenjamin Gaignard * @slave: slave vtg 75f2cb3148SBenjamin Gaignard * @link: List node to link the structure in lookup list 76f2cb3148SBenjamin Gaignard */ 77f2cb3148SBenjamin Gaignard struct sti_vtg { 78f2cb3148SBenjamin Gaignard struct device *dev; 79f2cb3148SBenjamin Gaignard struct device_node *np; 80f2cb3148SBenjamin Gaignard void __iomem *regs; 81f2cb3148SBenjamin Gaignard int irq; 82f2cb3148SBenjamin Gaignard u32 irq_status; 83f2cb3148SBenjamin Gaignard struct raw_notifier_head notifier_list; 84f2cb3148SBenjamin Gaignard int crtc_id; 85f2cb3148SBenjamin Gaignard struct sti_vtg *slave; 86f2cb3148SBenjamin Gaignard struct list_head link; 87f2cb3148SBenjamin Gaignard }; 88f2cb3148SBenjamin Gaignard 89f2cb3148SBenjamin Gaignard static void vtg_register(struct sti_vtg *vtg) 90f2cb3148SBenjamin Gaignard { 91f2cb3148SBenjamin Gaignard list_add_tail(&vtg->link, &vtg_lookup); 92f2cb3148SBenjamin Gaignard } 93f2cb3148SBenjamin Gaignard 94f2cb3148SBenjamin Gaignard struct sti_vtg *of_vtg_find(struct device_node *np) 95f2cb3148SBenjamin Gaignard { 96f2cb3148SBenjamin Gaignard struct sti_vtg *vtg; 97f2cb3148SBenjamin Gaignard 98f2cb3148SBenjamin Gaignard list_for_each_entry(vtg, &vtg_lookup, link) { 99f2cb3148SBenjamin Gaignard if (vtg->np == np) 100f2cb3148SBenjamin Gaignard return vtg; 101f2cb3148SBenjamin Gaignard } 102f2cb3148SBenjamin Gaignard return NULL; 103f2cb3148SBenjamin Gaignard } 104f2cb3148SBenjamin Gaignard EXPORT_SYMBOL(of_vtg_find); 105f2cb3148SBenjamin Gaignard 106f2cb3148SBenjamin Gaignard static void vtg_reset(struct sti_vtg *vtg) 107f2cb3148SBenjamin Gaignard { 108f2cb3148SBenjamin Gaignard /* reset slave and then master */ 109f2cb3148SBenjamin Gaignard if (vtg->slave) 110f2cb3148SBenjamin Gaignard vtg_reset(vtg->slave); 111f2cb3148SBenjamin Gaignard 112f2cb3148SBenjamin Gaignard writel(1, vtg->regs + VTG_DRST_AUTOC); 113f2cb3148SBenjamin Gaignard } 114f2cb3148SBenjamin Gaignard 115f2cb3148SBenjamin Gaignard static void vtg_set_mode(struct sti_vtg *vtg, 116f2cb3148SBenjamin Gaignard int type, const struct drm_display_mode *mode) 117f2cb3148SBenjamin Gaignard { 118f2cb3148SBenjamin Gaignard u32 tmp; 119f2cb3148SBenjamin Gaignard 120f2cb3148SBenjamin Gaignard if (vtg->slave) 121f2cb3148SBenjamin Gaignard vtg_set_mode(vtg->slave, VTG_TYPE_SLAVE_BY_EXT0, mode); 122f2cb3148SBenjamin Gaignard 123f2cb3148SBenjamin Gaignard writel(mode->htotal, vtg->regs + VTG_CLKLN); 124f2cb3148SBenjamin Gaignard writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); 125f2cb3148SBenjamin Gaignard 126f2cb3148SBenjamin Gaignard tmp = (mode->vtotal - mode->vsync_start + 1) << 16; 127f2cb3148SBenjamin Gaignard tmp |= mode->htotal - mode->hsync_start; 128f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_VID_TFO); 129f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_VID_BFO); 130f2cb3148SBenjamin Gaignard 131f2cb3148SBenjamin Gaignard tmp = (mode->vdisplay + mode->vtotal - mode->vsync_start + 1) << 16; 132f2cb3148SBenjamin Gaignard tmp |= mode->hdisplay + mode->htotal - mode->hsync_start; 133f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_VID_TFS); 134f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_VID_BFS); 135f2cb3148SBenjamin Gaignard 136f2cb3148SBenjamin Gaignard /* prepare VTG set 1 and 2 for HDMI and VTG set 3 for HD DAC */ 137f2cb3148SBenjamin Gaignard tmp = (mode->hsync_end - mode->hsync_start) << 16; 138f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_H_HD_1); 139f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_H_HD_2); 140f2cb3148SBenjamin Gaignard 141f2cb3148SBenjamin Gaignard tmp = (mode->vsync_end - mode->vsync_start + 1) << 16; 142f2cb3148SBenjamin Gaignard tmp |= 1; 143f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_TOP_V_VD_1); 144f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_BOT_V_VD_1); 145f2cb3148SBenjamin Gaignard writel(0, vtg->regs + VTG_TOP_V_HD_1); 146f2cb3148SBenjamin Gaignard writel(0, vtg->regs + VTG_BOT_V_HD_1); 147f2cb3148SBenjamin Gaignard 148f2cb3148SBenjamin Gaignard /* prepare VTG set 2 for for HD DCS */ 149f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_TOP_V_VD_2); 150f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_BOT_V_VD_2); 151f2cb3148SBenjamin Gaignard writel(0, vtg->regs + VTG_TOP_V_HD_2); 152f2cb3148SBenjamin Gaignard writel(0, vtg->regs + VTG_BOT_V_HD_2); 153f2cb3148SBenjamin Gaignard 154f2cb3148SBenjamin Gaignard /* prepare VTG set 3 for HD Analog in HD mode */ 155f2cb3148SBenjamin Gaignard tmp = (mode->hsync_end - mode->hsync_start + AWG_DELAY_HD) << 16; 156f2cb3148SBenjamin Gaignard tmp |= mode->htotal + AWG_DELAY_HD; 157f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_H_HD_3); 158f2cb3148SBenjamin Gaignard 159f2cb3148SBenjamin Gaignard tmp = (mode->vsync_end - mode->vsync_start) << 16; 160f2cb3148SBenjamin Gaignard tmp |= mode->vtotal; 161f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_TOP_V_VD_3); 162f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_BOT_V_VD_3); 163f2cb3148SBenjamin Gaignard 164f2cb3148SBenjamin Gaignard tmp = (mode->htotal + AWG_DELAY_HD) << 16; 165f2cb3148SBenjamin Gaignard tmp |= mode->htotal + AWG_DELAY_HD; 166f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_TOP_V_HD_3); 167f2cb3148SBenjamin Gaignard writel(tmp, vtg->regs + VTG_BOT_V_HD_3); 168f2cb3148SBenjamin Gaignard 169f2cb3148SBenjamin Gaignard /* mode */ 170f2cb3148SBenjamin Gaignard writel(type, vtg->regs + VTG_MODE); 171f2cb3148SBenjamin Gaignard } 172f2cb3148SBenjamin Gaignard 173f2cb3148SBenjamin Gaignard static void vtg_enable_irq(struct sti_vtg *vtg) 174f2cb3148SBenjamin Gaignard { 175f2cb3148SBenjamin Gaignard /* clear interrupt status and mask */ 176f2cb3148SBenjamin Gaignard writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR); 177f2cb3148SBenjamin Gaignard writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR); 178f2cb3148SBenjamin Gaignard writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET); 179f2cb3148SBenjamin Gaignard } 180f2cb3148SBenjamin Gaignard 181f2cb3148SBenjamin Gaignard void sti_vtg_set_config(struct sti_vtg *vtg, 182f2cb3148SBenjamin Gaignard const struct drm_display_mode *mode) 183f2cb3148SBenjamin Gaignard { 184f2cb3148SBenjamin Gaignard /* write configuration */ 185f2cb3148SBenjamin Gaignard vtg_set_mode(vtg, VTG_TYPE_MASTER, mode); 186f2cb3148SBenjamin Gaignard 187f2cb3148SBenjamin Gaignard vtg_reset(vtg); 188f2cb3148SBenjamin Gaignard 189f2cb3148SBenjamin Gaignard /* enable irq for the vtg vblank synchro */ 190f2cb3148SBenjamin Gaignard if (vtg->slave) 191f2cb3148SBenjamin Gaignard vtg_enable_irq(vtg->slave); 192f2cb3148SBenjamin Gaignard else 193f2cb3148SBenjamin Gaignard vtg_enable_irq(vtg); 194f2cb3148SBenjamin Gaignard } 195f2cb3148SBenjamin Gaignard EXPORT_SYMBOL(sti_vtg_set_config); 196f2cb3148SBenjamin Gaignard 197f2cb3148SBenjamin Gaignard /** 198f2cb3148SBenjamin Gaignard * sti_vtg_get_line_number 199f2cb3148SBenjamin Gaignard * 200f2cb3148SBenjamin Gaignard * @mode: display mode to be used 201f2cb3148SBenjamin Gaignard * @y: line 202f2cb3148SBenjamin Gaignard * 203f2cb3148SBenjamin Gaignard * Return the line number according to the display mode taking 204f2cb3148SBenjamin Gaignard * into account the Sync and Back Porch information. 205f2cb3148SBenjamin Gaignard * Video frame line numbers start at 1, y starts at 0. 206f2cb3148SBenjamin Gaignard * In interlaced modes the start line is the field line number of the odd 207f2cb3148SBenjamin Gaignard * field, but y is still defined as a progressive frame. 208f2cb3148SBenjamin Gaignard */ 209f2cb3148SBenjamin Gaignard u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y) 210f2cb3148SBenjamin Gaignard { 211f2cb3148SBenjamin Gaignard u32 start_line = mode.vtotal - mode.vsync_start + 1; 212f2cb3148SBenjamin Gaignard 213f2cb3148SBenjamin Gaignard if (mode.flags & DRM_MODE_FLAG_INTERLACE) 214f2cb3148SBenjamin Gaignard start_line *= 2; 215f2cb3148SBenjamin Gaignard 216f2cb3148SBenjamin Gaignard return start_line + y; 217f2cb3148SBenjamin Gaignard } 218f2cb3148SBenjamin Gaignard EXPORT_SYMBOL(sti_vtg_get_line_number); 219f2cb3148SBenjamin Gaignard 220f2cb3148SBenjamin Gaignard /** 221f2cb3148SBenjamin Gaignard * sti_vtg_get_pixel_number 222f2cb3148SBenjamin Gaignard * 223f2cb3148SBenjamin Gaignard * @mode: display mode to be used 224f2cb3148SBenjamin Gaignard * @x: row 225f2cb3148SBenjamin Gaignard * 226f2cb3148SBenjamin Gaignard * Return the pixel number according to the display mode taking 227f2cb3148SBenjamin Gaignard * into account the Sync and Back Porch information. 228f2cb3148SBenjamin Gaignard * Pixels are counted from 0. 229f2cb3148SBenjamin Gaignard */ 230f2cb3148SBenjamin Gaignard u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x) 231f2cb3148SBenjamin Gaignard { 232f2cb3148SBenjamin Gaignard return mode.htotal - mode.hsync_start + x; 233f2cb3148SBenjamin Gaignard } 234f2cb3148SBenjamin Gaignard EXPORT_SYMBOL(sti_vtg_get_pixel_number); 235f2cb3148SBenjamin Gaignard 236f2cb3148SBenjamin Gaignard int sti_vtg_register_client(struct sti_vtg *vtg, 237f2cb3148SBenjamin Gaignard struct notifier_block *nb, int crtc_id) 238f2cb3148SBenjamin Gaignard { 239f2cb3148SBenjamin Gaignard if (vtg->slave) 240f2cb3148SBenjamin Gaignard return sti_vtg_register_client(vtg->slave, nb, crtc_id); 241f2cb3148SBenjamin Gaignard 242f2cb3148SBenjamin Gaignard vtg->crtc_id = crtc_id; 243f2cb3148SBenjamin Gaignard return raw_notifier_chain_register(&vtg->notifier_list, nb); 244f2cb3148SBenjamin Gaignard } 245f2cb3148SBenjamin Gaignard EXPORT_SYMBOL(sti_vtg_register_client); 246f2cb3148SBenjamin Gaignard 247f2cb3148SBenjamin Gaignard int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb) 248f2cb3148SBenjamin Gaignard { 249f2cb3148SBenjamin Gaignard if (vtg->slave) 250f2cb3148SBenjamin Gaignard return sti_vtg_unregister_client(vtg->slave, nb); 251f2cb3148SBenjamin Gaignard 252f2cb3148SBenjamin Gaignard return raw_notifier_chain_unregister(&vtg->notifier_list, nb); 253f2cb3148SBenjamin Gaignard } 254f2cb3148SBenjamin Gaignard EXPORT_SYMBOL(sti_vtg_unregister_client); 255f2cb3148SBenjamin Gaignard 256f2cb3148SBenjamin Gaignard static irqreturn_t vtg_irq_thread(int irq, void *arg) 257f2cb3148SBenjamin Gaignard { 258f2cb3148SBenjamin Gaignard struct sti_vtg *vtg = arg; 259f2cb3148SBenjamin Gaignard u32 event; 260f2cb3148SBenjamin Gaignard 261f2cb3148SBenjamin Gaignard event = (vtg->irq_status & VTG_IRQ_TOP) ? 262f2cb3148SBenjamin Gaignard VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT; 263f2cb3148SBenjamin Gaignard 264f2cb3148SBenjamin Gaignard raw_notifier_call_chain(&vtg->notifier_list, event, &vtg->crtc_id); 265f2cb3148SBenjamin Gaignard 266f2cb3148SBenjamin Gaignard return IRQ_HANDLED; 267f2cb3148SBenjamin Gaignard } 268f2cb3148SBenjamin Gaignard 269f2cb3148SBenjamin Gaignard static irqreturn_t vtg_irq(int irq, void *arg) 270f2cb3148SBenjamin Gaignard { 271f2cb3148SBenjamin Gaignard struct sti_vtg *vtg = arg; 272f2cb3148SBenjamin Gaignard 273f2cb3148SBenjamin Gaignard vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS); 274f2cb3148SBenjamin Gaignard 275f2cb3148SBenjamin Gaignard writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR); 276f2cb3148SBenjamin Gaignard 277f2cb3148SBenjamin Gaignard /* force sync bus write */ 278f2cb3148SBenjamin Gaignard readl(vtg->regs + VTG_HOST_ITS); 279f2cb3148SBenjamin Gaignard 280f2cb3148SBenjamin Gaignard return IRQ_WAKE_THREAD; 281f2cb3148SBenjamin Gaignard } 282f2cb3148SBenjamin Gaignard 283f2cb3148SBenjamin Gaignard static int vtg_probe(struct platform_device *pdev) 284f2cb3148SBenjamin Gaignard { 285f2cb3148SBenjamin Gaignard struct device *dev = &pdev->dev; 286f2cb3148SBenjamin Gaignard struct device_node *np; 287f2cb3148SBenjamin Gaignard struct sti_vtg *vtg; 288f2cb3148SBenjamin Gaignard struct resource *res; 289f2cb3148SBenjamin Gaignard char irq_name[32]; 290f2cb3148SBenjamin Gaignard int ret; 291f2cb3148SBenjamin Gaignard 292f2cb3148SBenjamin Gaignard vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL); 293f2cb3148SBenjamin Gaignard if (!vtg) 294f2cb3148SBenjamin Gaignard return -ENOMEM; 295f2cb3148SBenjamin Gaignard 296f2cb3148SBenjamin Gaignard vtg->dev = dev; 297f2cb3148SBenjamin Gaignard vtg->np = pdev->dev.of_node; 298f2cb3148SBenjamin Gaignard 299f2cb3148SBenjamin Gaignard /* Get Memory ressources */ 300f2cb3148SBenjamin Gaignard res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 301f2cb3148SBenjamin Gaignard if (!res) { 302f2cb3148SBenjamin Gaignard DRM_ERROR("Get memory resource failed\n"); 303f2cb3148SBenjamin Gaignard return -ENOMEM; 304f2cb3148SBenjamin Gaignard } 305f2cb3148SBenjamin Gaignard vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); 306f2cb3148SBenjamin Gaignard 307f2cb3148SBenjamin Gaignard np = of_parse_phandle(pdev->dev.of_node, "st,slave", 0); 308f2cb3148SBenjamin Gaignard if (np) { 309f2cb3148SBenjamin Gaignard vtg->slave = of_vtg_find(np); 310f2cb3148SBenjamin Gaignard 311f2cb3148SBenjamin Gaignard if (!vtg->slave) 312f2cb3148SBenjamin Gaignard return -EPROBE_DEFER; 313f2cb3148SBenjamin Gaignard } else { 314f2cb3148SBenjamin Gaignard vtg->irq = platform_get_irq(pdev, 0); 315f2cb3148SBenjamin Gaignard if (IS_ERR_VALUE(vtg->irq)) { 316f2cb3148SBenjamin Gaignard DRM_ERROR("Failed to get VTG interrupt\n"); 317f2cb3148SBenjamin Gaignard return vtg->irq; 318f2cb3148SBenjamin Gaignard } 319f2cb3148SBenjamin Gaignard 320f2cb3148SBenjamin Gaignard snprintf(irq_name, sizeof(irq_name), "vsync-%s", 321f2cb3148SBenjamin Gaignard dev_name(vtg->dev)); 322f2cb3148SBenjamin Gaignard 323f2cb3148SBenjamin Gaignard RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list); 324f2cb3148SBenjamin Gaignard 325f2cb3148SBenjamin Gaignard ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq, 326f2cb3148SBenjamin Gaignard vtg_irq_thread, IRQF_ONESHOT, irq_name, vtg); 327f2cb3148SBenjamin Gaignard if (IS_ERR_VALUE(ret)) { 328f2cb3148SBenjamin Gaignard DRM_ERROR("Failed to register VTG interrupt\n"); 329f2cb3148SBenjamin Gaignard return ret; 330f2cb3148SBenjamin Gaignard } 331f2cb3148SBenjamin Gaignard } 332f2cb3148SBenjamin Gaignard 333f2cb3148SBenjamin Gaignard vtg_register(vtg); 334f2cb3148SBenjamin Gaignard platform_set_drvdata(pdev, vtg); 335f2cb3148SBenjamin Gaignard 336f2cb3148SBenjamin Gaignard DRM_INFO("%s %s\n", __func__, dev_name(vtg->dev)); 337f2cb3148SBenjamin Gaignard 338f2cb3148SBenjamin Gaignard return 0; 339f2cb3148SBenjamin Gaignard } 340f2cb3148SBenjamin Gaignard 341f2cb3148SBenjamin Gaignard static int vtg_remove(struct platform_device *pdev) 342f2cb3148SBenjamin Gaignard { 343f2cb3148SBenjamin Gaignard return 0; 344f2cb3148SBenjamin Gaignard } 345f2cb3148SBenjamin Gaignard 346f2cb3148SBenjamin Gaignard static const struct of_device_id vtg_of_match[] = { 347f2cb3148SBenjamin Gaignard { .compatible = "st,vtg", }, 348f2cb3148SBenjamin Gaignard { /* sentinel */ } 349f2cb3148SBenjamin Gaignard }; 350f2cb3148SBenjamin Gaignard MODULE_DEVICE_TABLE(of, vtg_of_match); 351f2cb3148SBenjamin Gaignard 352f2cb3148SBenjamin Gaignard struct platform_driver sti_vtg_driver = { 353f2cb3148SBenjamin Gaignard .driver = { 354f2cb3148SBenjamin Gaignard .name = "sti-vtg", 355f2cb3148SBenjamin Gaignard .owner = THIS_MODULE, 356f2cb3148SBenjamin Gaignard .of_match_table = vtg_of_match, 357f2cb3148SBenjamin Gaignard }, 358f2cb3148SBenjamin Gaignard .probe = vtg_probe, 359f2cb3148SBenjamin Gaignard .remove = vtg_remove, 360f2cb3148SBenjamin Gaignard }; 361f2cb3148SBenjamin Gaignard 362f2cb3148SBenjamin Gaignard module_platform_driver(sti_vtg_driver); 363f2cb3148SBenjamin Gaignard 364f2cb3148SBenjamin Gaignard MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 365f2cb3148SBenjamin Gaignard MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 366f2cb3148SBenjamin Gaignard MODULE_LICENSE("GPL"); 367