1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * for STMicroelectronics. 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include "sti_compositor.h" 10 #include "sti_mixer.h" 11 #include "sti_vtg.h" 12 13 /* Identity: G=Y , B=Cb , R=Cr */ 14 static const u32 mixerColorSpaceMatIdentity[] = { 15 0x10000000, 0x00000000, 0x10000000, 0x00001000, 16 0x00000000, 0x00000000, 0x00000000, 0x00000000 17 }; 18 19 /* regs offset */ 20 #define GAM_MIXER_CTL 0x00 21 #define GAM_MIXER_BKC 0x04 22 #define GAM_MIXER_BCO 0x0C 23 #define GAM_MIXER_BCS 0x10 24 #define GAM_MIXER_AVO 0x28 25 #define GAM_MIXER_AVS 0x2C 26 #define GAM_MIXER_CRB 0x34 27 #define GAM_MIXER_ACT 0x38 28 #define GAM_MIXER_MBP 0x3C 29 #define GAM_MIXER_MX0 0x80 30 31 /* id for depth of CRB reg */ 32 #define GAM_DEPTH_VID0_ID 1 33 #define GAM_DEPTH_VID1_ID 2 34 #define GAM_DEPTH_GDP0_ID 3 35 #define GAM_DEPTH_GDP1_ID 4 36 #define GAM_DEPTH_GDP2_ID 5 37 #define GAM_DEPTH_GDP3_ID 6 38 #define GAM_DEPTH_MASK_ID 7 39 40 /* mask in CTL reg */ 41 #define GAM_CTL_BACK_MASK BIT(0) 42 #define GAM_CTL_VID0_MASK BIT(1) 43 #define GAM_CTL_VID1_MASK BIT(2) 44 #define GAM_CTL_GDP0_MASK BIT(3) 45 #define GAM_CTL_GDP1_MASK BIT(4) 46 #define GAM_CTL_GDP2_MASK BIT(5) 47 #define GAM_CTL_GDP3_MASK BIT(6) 48 #define GAM_CTL_CURSOR_MASK BIT(9) 49 50 const char *sti_mixer_to_str(struct sti_mixer *mixer) 51 { 52 switch (mixer->id) { 53 case STI_MIXER_MAIN: 54 return "MAIN_MIXER"; 55 case STI_MIXER_AUX: 56 return "AUX_MIXER"; 57 default: 58 return "<UNKNOWN MIXER>"; 59 } 60 } 61 62 static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id) 63 { 64 return readl(mixer->regs + reg_id); 65 } 66 67 static inline void sti_mixer_reg_write(struct sti_mixer *mixer, 68 u32 reg_id, u32 val) 69 { 70 writel(val, mixer->regs + reg_id); 71 } 72 73 void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable) 74 { 75 u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL); 76 77 val &= ~GAM_CTL_BACK_MASK; 78 val |= enable; 79 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); 80 } 81 82 static void sti_mixer_set_background_color(struct sti_mixer *mixer, 83 u8 red, u8 green, u8 blue) 84 { 85 u32 val = (red << 16) | (green << 8) | blue; 86 87 sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val); 88 } 89 90 static void sti_mixer_set_background_area(struct sti_mixer *mixer, 91 struct drm_display_mode *mode) 92 { 93 u32 ydo, xdo, yds, xds; 94 95 ydo = sti_vtg_get_line_number(*mode, 0); 96 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 97 xdo = sti_vtg_get_pixel_number(*mode, 0); 98 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 99 100 sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo); 101 sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds); 102 } 103 104 int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer) 105 { 106 int layer_id, depth = layer->zorder; 107 unsigned int i; 108 u32 mask, val; 109 110 if ((depth < 1) || (depth > GAM_MIXER_NB_DEPTH_LEVEL)) 111 return 1; 112 113 switch (layer->desc) { 114 case STI_GDP_0: 115 layer_id = GAM_DEPTH_GDP0_ID; 116 break; 117 case STI_GDP_1: 118 layer_id = GAM_DEPTH_GDP1_ID; 119 break; 120 case STI_GDP_2: 121 layer_id = GAM_DEPTH_GDP2_ID; 122 break; 123 case STI_GDP_3: 124 layer_id = GAM_DEPTH_GDP3_ID; 125 break; 126 case STI_VID_0: 127 case STI_HQVDP_0: 128 layer_id = GAM_DEPTH_VID0_ID; 129 break; 130 case STI_VID_1: 131 layer_id = GAM_DEPTH_VID1_ID; 132 break; 133 case STI_CURSOR: 134 /* no need to set depth for cursor */ 135 return 0; 136 default: 137 DRM_ERROR("Unknown layer %d\n", layer->desc); 138 return 1; 139 } 140 141 /* Search if a previous depth was already assigned to the layer */ 142 val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); 143 for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { 144 mask = GAM_DEPTH_MASK_ID << (3 * i); 145 if ((val & mask) == layer_id << (3 * i)) 146 break; 147 } 148 149 mask |= GAM_DEPTH_MASK_ID << (3 * (depth - 1)); 150 layer_id = layer_id << (3 * (depth - 1)); 151 152 DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer), 153 sti_layer_to_str(layer), depth); 154 dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n", 155 layer_id, mask); 156 157 val &= ~mask; 158 val |= layer_id; 159 sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val); 160 161 dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n", 162 sti_mixer_reg_read(mixer, GAM_MIXER_CRB)); 163 return 0; 164 } 165 166 int sti_mixer_active_video_area(struct sti_mixer *mixer, 167 struct drm_display_mode *mode) 168 { 169 u32 ydo, xdo, yds, xds; 170 171 ydo = sti_vtg_get_line_number(*mode, 0); 172 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 173 xdo = sti_vtg_get_pixel_number(*mode, 0); 174 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 175 176 DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n", 177 sti_mixer_to_str(mixer), xdo, ydo, xds, yds); 178 sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo); 179 sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds); 180 181 sti_mixer_set_background_color(mixer, 0xFF, 0, 0); 182 183 sti_mixer_set_background_area(mixer, mode); 184 sti_mixer_set_background_status(mixer, true); 185 return 0; 186 } 187 188 static u32 sti_mixer_get_layer_mask(struct sti_layer *layer) 189 { 190 switch (layer->desc) { 191 case STI_BACK: 192 return GAM_CTL_BACK_MASK; 193 case STI_GDP_0: 194 return GAM_CTL_GDP0_MASK; 195 case STI_GDP_1: 196 return GAM_CTL_GDP1_MASK; 197 case STI_GDP_2: 198 return GAM_CTL_GDP2_MASK; 199 case STI_GDP_3: 200 return GAM_CTL_GDP3_MASK; 201 case STI_VID_0: 202 case STI_HQVDP_0: 203 return GAM_CTL_VID0_MASK; 204 case STI_VID_1: 205 return GAM_CTL_VID1_MASK; 206 case STI_CURSOR: 207 return GAM_CTL_CURSOR_MASK; 208 default: 209 return 0; 210 } 211 } 212 213 int sti_mixer_set_layer_status(struct sti_mixer *mixer, 214 struct sti_layer *layer, bool status) 215 { 216 u32 mask, val; 217 218 DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable", 219 sti_mixer_to_str(mixer), sti_layer_to_str(layer)); 220 221 mask = sti_mixer_get_layer_mask(layer); 222 if (!mask) { 223 DRM_ERROR("Can not find layer mask\n"); 224 return -EINVAL; 225 } 226 227 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL); 228 val &= ~mask; 229 val |= status ? mask : 0; 230 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); 231 232 return 0; 233 } 234 235 void sti_mixer_clear_all_layers(struct sti_mixer *mixer) 236 { 237 u32 val; 238 239 DRM_DEBUG_DRIVER("%s clear all layer\n", sti_mixer_to_str(mixer)); 240 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL) & 0xFFFF0000; 241 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); 242 } 243 244 void sti_mixer_set_matrix(struct sti_mixer *mixer) 245 { 246 unsigned int i; 247 248 for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++) 249 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4), 250 mixerColorSpaceMatIdentity[i]); 251 } 252 253 struct sti_mixer *sti_mixer_create(struct device *dev, int id, 254 void __iomem *baseaddr) 255 { 256 struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL); 257 struct device_node *np = dev->of_node; 258 259 dev_dbg(dev, "%s\n", __func__); 260 if (!mixer) { 261 DRM_ERROR("Failed to allocated memory for mixer\n"); 262 return NULL; 263 } 264 mixer->regs = baseaddr; 265 mixer->dev = dev; 266 mixer->id = id; 267 268 if (of_device_is_compatible(np, "st,stih416-compositor")) 269 sti_mixer_set_matrix(mixer); 270 271 DRM_DEBUG_DRIVER("%s created. Regs=%p\n", 272 sti_mixer_to_str(mixer), mixer->regs); 273 274 return mixer; 275 } 276