1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * for STMicroelectronics. 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include "sti_compositor.h" 10 #include "sti_mixer.h" 11 #include "sti_vtg.h" 12 13 /* Identity: G=Y , B=Cb , R=Cr */ 14 static const u32 mixerColorSpaceMatIdentity[] = { 15 0x10000000, 0x00000000, 0x10000000, 0x00001000, 16 0x00000000, 0x00000000, 0x00000000, 0x00000000 17 }; 18 19 /* regs offset */ 20 #define GAM_MIXER_CTL 0x00 21 #define GAM_MIXER_BKC 0x04 22 #define GAM_MIXER_BCO 0x0C 23 #define GAM_MIXER_BCS 0x10 24 #define GAM_MIXER_AVO 0x28 25 #define GAM_MIXER_AVS 0x2C 26 #define GAM_MIXER_CRB 0x34 27 #define GAM_MIXER_ACT 0x38 28 #define GAM_MIXER_MBP 0x3C 29 #define GAM_MIXER_MX0 0x80 30 31 /* id for depth of CRB reg */ 32 #define GAM_DEPTH_VID0_ID 1 33 #define GAM_DEPTH_VID1_ID 2 34 #define GAM_DEPTH_GDP0_ID 3 35 #define GAM_DEPTH_GDP1_ID 4 36 #define GAM_DEPTH_GDP2_ID 5 37 #define GAM_DEPTH_GDP3_ID 6 38 #define GAM_DEPTH_MASK_ID 7 39 40 /* mask in CTL reg */ 41 #define GAM_CTL_BACK_MASK BIT(0) 42 #define GAM_CTL_VID0_MASK BIT(1) 43 #define GAM_CTL_VID1_MASK BIT(2) 44 #define GAM_CTL_GDP0_MASK BIT(3) 45 #define GAM_CTL_GDP1_MASK BIT(4) 46 #define GAM_CTL_GDP2_MASK BIT(5) 47 #define GAM_CTL_GDP3_MASK BIT(6) 48 #define GAM_CTL_CURSOR_MASK BIT(9) 49 50 const char *sti_mixer_to_str(struct sti_mixer *mixer) 51 { 52 switch (mixer->id) { 53 case STI_MIXER_MAIN: 54 return "MAIN_MIXER"; 55 case STI_MIXER_AUX: 56 return "AUX_MIXER"; 57 default: 58 return "<UNKNOWN MIXER>"; 59 } 60 } 61 EXPORT_SYMBOL(sti_mixer_to_str); 62 63 static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id) 64 { 65 return readl(mixer->regs + reg_id); 66 } 67 68 static inline void sti_mixer_reg_write(struct sti_mixer *mixer, 69 u32 reg_id, u32 val) 70 { 71 writel(val, mixer->regs + reg_id); 72 } 73 74 void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable) 75 { 76 u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL); 77 78 val &= ~GAM_CTL_BACK_MASK; 79 val |= enable; 80 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); 81 } 82 83 static void sti_mixer_set_background_color(struct sti_mixer *mixer, 84 u8 red, u8 green, u8 blue) 85 { 86 u32 val = (red << 16) | (green << 8) | blue; 87 88 sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val); 89 } 90 91 static void sti_mixer_set_background_area(struct sti_mixer *mixer, 92 struct drm_display_mode *mode) 93 { 94 u32 ydo, xdo, yds, xds; 95 96 ydo = sti_vtg_get_line_number(*mode, 0); 97 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 98 xdo = sti_vtg_get_pixel_number(*mode, 0); 99 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 100 101 sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo); 102 sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds); 103 } 104 105 int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) 106 { 107 int plane_id, depth = plane->zorder; 108 unsigned int i; 109 u32 mask, val; 110 111 if ((depth < 1) || (depth > GAM_MIXER_NB_DEPTH_LEVEL)) 112 return 1; 113 114 switch (plane->desc) { 115 case STI_GDP_0: 116 plane_id = GAM_DEPTH_GDP0_ID; 117 break; 118 case STI_GDP_1: 119 plane_id = GAM_DEPTH_GDP1_ID; 120 break; 121 case STI_GDP_2: 122 plane_id = GAM_DEPTH_GDP2_ID; 123 break; 124 case STI_GDP_3: 125 plane_id = GAM_DEPTH_GDP3_ID; 126 break; 127 case STI_HQVDP_0: 128 plane_id = GAM_DEPTH_VID0_ID; 129 break; 130 case STI_CURSOR: 131 /* no need to set depth for cursor */ 132 return 0; 133 default: 134 DRM_ERROR("Unknown plane %d\n", plane->desc); 135 return 1; 136 } 137 138 /* Search if a previous depth was already assigned to the plane */ 139 val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); 140 for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { 141 mask = GAM_DEPTH_MASK_ID << (3 * i); 142 if ((val & mask) == plane_id << (3 * i)) 143 break; 144 } 145 146 mask |= GAM_DEPTH_MASK_ID << (3 * (depth - 1)); 147 plane_id = plane_id << (3 * (depth - 1)); 148 149 DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer), 150 sti_plane_to_str(plane), depth); 151 dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n", 152 plane_id, mask); 153 154 val &= ~mask; 155 val |= plane_id; 156 sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val); 157 158 dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n", 159 sti_mixer_reg_read(mixer, GAM_MIXER_CRB)); 160 return 0; 161 } 162 163 int sti_mixer_active_video_area(struct sti_mixer *mixer, 164 struct drm_display_mode *mode) 165 { 166 u32 ydo, xdo, yds, xds; 167 168 ydo = sti_vtg_get_line_number(*mode, 0); 169 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); 170 xdo = sti_vtg_get_pixel_number(*mode, 0); 171 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); 172 173 DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n", 174 sti_mixer_to_str(mixer), xdo, ydo, xds, yds); 175 sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo); 176 sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds); 177 178 sti_mixer_set_background_color(mixer, 0xFF, 0, 0); 179 180 sti_mixer_set_background_area(mixer, mode); 181 sti_mixer_set_background_status(mixer, true); 182 return 0; 183 } 184 185 static u32 sti_mixer_get_plane_mask(struct sti_plane *plane) 186 { 187 switch (plane->desc) { 188 case STI_BACK: 189 return GAM_CTL_BACK_MASK; 190 case STI_GDP_0: 191 return GAM_CTL_GDP0_MASK; 192 case STI_GDP_1: 193 return GAM_CTL_GDP1_MASK; 194 case STI_GDP_2: 195 return GAM_CTL_GDP2_MASK; 196 case STI_GDP_3: 197 return GAM_CTL_GDP3_MASK; 198 case STI_HQVDP_0: 199 return GAM_CTL_VID0_MASK; 200 case STI_CURSOR: 201 return GAM_CTL_CURSOR_MASK; 202 default: 203 return 0; 204 } 205 } 206 207 int sti_mixer_set_plane_status(struct sti_mixer *mixer, 208 struct sti_plane *plane, bool status) 209 { 210 u32 mask, val; 211 212 DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable", 213 sti_mixer_to_str(mixer), sti_plane_to_str(plane)); 214 215 mask = sti_mixer_get_plane_mask(plane); 216 if (!mask) { 217 DRM_ERROR("Can't find layer mask\n"); 218 return -EINVAL; 219 } 220 221 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL); 222 val &= ~mask; 223 val |= status ? mask : 0; 224 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); 225 226 return 0; 227 } 228 229 void sti_mixer_set_matrix(struct sti_mixer *mixer) 230 { 231 unsigned int i; 232 233 for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++) 234 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4), 235 mixerColorSpaceMatIdentity[i]); 236 } 237 238 struct sti_mixer *sti_mixer_create(struct device *dev, int id, 239 void __iomem *baseaddr) 240 { 241 struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL); 242 struct device_node *np = dev->of_node; 243 244 dev_dbg(dev, "%s\n", __func__); 245 if (!mixer) { 246 DRM_ERROR("Failed to allocated memory for mixer\n"); 247 return NULL; 248 } 249 mixer->regs = baseaddr; 250 mixer->dev = dev; 251 mixer->id = id; 252 253 if (of_device_is_compatible(np, "st,stih416-compositor")) 254 sti_mixer_set_matrix(mixer); 255 256 DRM_DEBUG_DRIVER("%s created. Regs=%p\n", 257 sti_mixer_to_str(mixer), mixer->regs); 258 259 return mixer; 260 } 261