1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 7 #include <linux/component.h> 8 #include <linux/firmware.h> 9 #include <linux/reset.h> 10 #include <linux/seq_file.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_fb_cma_helper.h> 14 #include <drm/drm_gem_cma_helper.h> 15 16 #include "sti_compositor.h" 17 #include "sti_hqvdp_lut.h" 18 #include "sti_plane.h" 19 #include "sti_vtg.h" 20 #include "sti_drv.h" 21 22 /* Firmware name */ 23 #define HQVDP_FMW_NAME "hqvdp-stih407.bin" 24 25 /* Regs address */ 26 #define HQVDP_DMEM 0x00000000 /* 0x00000000 */ 27 #define HQVDP_PMEM 0x00040000 /* 0x00040000 */ 28 #define HQVDP_RD_PLUG 0x000E0000 /* 0x000E0000 */ 29 #define HQVDP_RD_PLUG_CONTROL (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */ 30 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */ 31 #define HQVDP_RD_PLUG_MIN_OPC (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */ 32 #define HQVDP_RD_PLUG_MAX_OPC (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */ 33 #define HQVDP_RD_PLUG_MAX_CHK (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */ 34 #define HQVDP_RD_PLUG_MAX_MSG (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */ 35 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */ 36 #define HQVDP_WR_PLUG 0x000E2000 /* 0x000E2000 */ 37 #define HQVDP_WR_PLUG_CONTROL (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */ 38 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */ 39 #define HQVDP_WR_PLUG_MIN_OPC (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */ 40 #define HQVDP_WR_PLUG_MAX_OPC (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */ 41 #define HQVDP_WR_PLUG_MAX_CHK (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */ 42 #define HQVDP_WR_PLUG_MAX_MSG (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */ 43 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */ 44 #define HQVDP_MBX 0x000E4000 /* 0x000E4000 */ 45 #define HQVDP_MBX_IRQ_TO_XP70 (HQVDP_MBX + 0x0000) /* 0x000E4000 */ 46 #define HQVDP_MBX_INFO_HOST (HQVDP_MBX + 0x0004) /* 0x000E4004 */ 47 #define HQVDP_MBX_IRQ_TO_HOST (HQVDP_MBX + 0x0008) /* 0x000E4008 */ 48 #define HQVDP_MBX_INFO_XP70 (HQVDP_MBX + 0x000C) /* 0x000E400C */ 49 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010) /* 0x000E4010 */ 50 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014) /* 0x000E4014 */ 51 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018) /* 0x000E4018 */ 52 #define HQVDP_MBX_GP_STATUS (HQVDP_MBX + 0x001C) /* 0x000E401C */ 53 #define HQVDP_MBX_NEXT_CMD (HQVDP_MBX + 0x0020) /* 0x000E4020 */ 54 #define HQVDP_MBX_CURRENT_CMD (HQVDP_MBX + 0x0024) /* 0x000E4024 */ 55 #define HQVDP_MBX_SOFT_VSYNC (HQVDP_MBX + 0x0028) /* 0x000E4028 */ 56 57 /* Plugs config */ 58 #define PLUG_CONTROL_ENABLE 0x00000001 59 #define PLUG_PAGE_SIZE_256 0x00000002 60 #define PLUG_MIN_OPC_8 0x00000003 61 #define PLUG_MAX_OPC_64 0x00000006 62 #define PLUG_MAX_CHK_2X 0x00000001 63 #define PLUG_MAX_MSG_1X 0x00000000 64 #define PLUG_MIN_SPACE_1 0x00000000 65 66 /* SW reset CTRL */ 67 #define SW_RESET_CTRL_FULL BIT(0) 68 #define SW_RESET_CTRL_CORE BIT(1) 69 70 /* Startup ctrl 1 */ 71 #define STARTUP_CTRL1_RST_DONE BIT(0) 72 #define STARTUP_CTRL1_AUTH_IDLE BIT(2) 73 74 /* Startup ctrl 2 */ 75 #define STARTUP_CTRL2_FETCH_EN BIT(1) 76 77 /* Info xP70 */ 78 #define INFO_XP70_FW_READY BIT(15) 79 #define INFO_XP70_FW_PROCESSING BIT(14) 80 #define INFO_XP70_FW_INITQUEUES BIT(13) 81 82 /* SOFT_VSYNC */ 83 #define SOFT_VSYNC_HW 0x00000000 84 #define SOFT_VSYNC_SW_CMD 0x00000001 85 #define SOFT_VSYNC_SW_CTRL_IRQ 0x00000003 86 87 /* Reset & boot poll config */ 88 #define POLL_MAX_ATTEMPT 50 89 #define POLL_DELAY_MS 20 90 91 #define SCALE_FACTOR 8192 92 #define SCALE_MAX_FOR_LEG_LUT_F 4096 93 #define SCALE_MAX_FOR_LEG_LUT_E 4915 94 #define SCALE_MAX_FOR_LEG_LUT_D 6654 95 #define SCALE_MAX_FOR_LEG_LUT_C 8192 96 97 enum sti_hvsrc_orient { 98 HVSRC_HORI, 99 HVSRC_VERT 100 }; 101 102 /* Command structures */ 103 struct sti_hqvdp_top { 104 u32 config; 105 u32 mem_format; 106 u32 current_luma; 107 u32 current_enh_luma; 108 u32 current_right_luma; 109 u32 current_enh_right_luma; 110 u32 current_chroma; 111 u32 current_enh_chroma; 112 u32 current_right_chroma; 113 u32 current_enh_right_chroma; 114 u32 output_luma; 115 u32 output_chroma; 116 u32 luma_src_pitch; 117 u32 luma_enh_src_pitch; 118 u32 luma_right_src_pitch; 119 u32 luma_enh_right_src_pitch; 120 u32 chroma_src_pitch; 121 u32 chroma_enh_src_pitch; 122 u32 chroma_right_src_pitch; 123 u32 chroma_enh_right_src_pitch; 124 u32 luma_processed_pitch; 125 u32 chroma_processed_pitch; 126 u32 input_frame_size; 127 u32 input_viewport_ori; 128 u32 input_viewport_ori_right; 129 u32 input_viewport_size; 130 u32 left_view_border_width; 131 u32 right_view_border_width; 132 u32 left_view_3d_offset_width; 133 u32 right_view_3d_offset_width; 134 u32 side_stripe_color; 135 u32 crc_reset_ctrl; 136 }; 137 138 /* Configs for interlaced : no IT, no pass thru, 3 fields */ 139 #define TOP_CONFIG_INTER_BTM 0x00000000 140 #define TOP_CONFIG_INTER_TOP 0x00000002 141 142 /* Config for progressive : no IT, no pass thru, 3 fields */ 143 #define TOP_CONFIG_PROGRESSIVE 0x00000001 144 145 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */ 146 #define TOP_MEM_FORMAT_DFLT 0x00018060 147 148 /* Min/Max size */ 149 #define MAX_WIDTH 0x1FFF 150 #define MAX_HEIGHT 0x0FFF 151 #define MIN_WIDTH 0x0030 152 #define MIN_HEIGHT 0x0010 153 154 struct sti_hqvdp_vc1re { 155 u32 ctrl_prv_csdi; 156 u32 ctrl_cur_csdi; 157 u32 ctrl_nxt_csdi; 158 u32 ctrl_cur_fmd; 159 u32 ctrl_nxt_fmd; 160 }; 161 162 struct sti_hqvdp_fmd { 163 u32 config; 164 u32 viewport_ori; 165 u32 viewport_size; 166 u32 next_next_luma; 167 u32 next_next_right_luma; 168 u32 next_next_next_luma; 169 u32 next_next_next_right_luma; 170 u32 threshold_scd; 171 u32 threshold_rfd; 172 u32 threshold_move; 173 u32 threshold_cfd; 174 }; 175 176 struct sti_hqvdp_csdi { 177 u32 config; 178 u32 config2; 179 u32 dcdi_config; 180 u32 prev_luma; 181 u32 prev_enh_luma; 182 u32 prev_right_luma; 183 u32 prev_enh_right_luma; 184 u32 next_luma; 185 u32 next_enh_luma; 186 u32 next_right_luma; 187 u32 next_enh_right_luma; 188 u32 prev_chroma; 189 u32 prev_enh_chroma; 190 u32 prev_right_chroma; 191 u32 prev_enh_right_chroma; 192 u32 next_chroma; 193 u32 next_enh_chroma; 194 u32 next_right_chroma; 195 u32 next_enh_right_chroma; 196 u32 prev_motion; 197 u32 prev_right_motion; 198 u32 cur_motion; 199 u32 cur_right_motion; 200 u32 next_motion; 201 u32 next_right_motion; 202 }; 203 204 /* Config for progressive: by pass */ 205 #define CSDI_CONFIG_PROG 0x00000000 206 /* Config for directional deinterlacing without motion */ 207 #define CSDI_CONFIG_INTER_DIR 0x00000016 208 /* Additional configs for fader, blender, motion,... deinterlace algorithms */ 209 #define CSDI_CONFIG2_DFLT 0x000001B3 210 #define CSDI_DCDI_CONFIG_DFLT 0x00203803 211 212 struct sti_hqvdp_hvsrc { 213 u32 hor_panoramic_ctrl; 214 u32 output_picture_size; 215 u32 init_horizontal; 216 u32 init_vertical; 217 u32 param_ctrl; 218 u32 yh_coef[NB_COEF]; 219 u32 ch_coef[NB_COEF]; 220 u32 yv_coef[NB_COEF]; 221 u32 cv_coef[NB_COEF]; 222 u32 hori_shift; 223 u32 vert_shift; 224 }; 225 226 /* Default ParamCtrl: all controls enabled */ 227 #define HVSRC_PARAM_CTRL_DFLT 0xFFFFFFFF 228 229 struct sti_hqvdp_iqi { 230 u32 config; 231 u32 demo_wind_size; 232 u32 pk_config; 233 u32 coeff0_coeff1; 234 u32 coeff2_coeff3; 235 u32 coeff4; 236 u32 pk_lut; 237 u32 pk_gain; 238 u32 pk_coring_level; 239 u32 cti_config; 240 u32 le_config; 241 u32 le_lut[64]; 242 u32 con_bri; 243 u32 sat_gain; 244 u32 pxf_conf; 245 u32 default_color; 246 }; 247 248 /* Default Config : IQI bypassed */ 249 #define IQI_CONFIG_DFLT 0x00000001 250 /* Default Contrast & Brightness gain = 256 */ 251 #define IQI_CON_BRI_DFLT 0x00000100 252 /* Default Saturation gain = 256 */ 253 #define IQI_SAT_GAIN_DFLT 0x00000100 254 /* Default PxfConf : P2I bypassed */ 255 #define IQI_PXF_CONF_DFLT 0x00000001 256 257 struct sti_hqvdp_top_status { 258 u32 processing_time; 259 u32 input_y_crc; 260 u32 input_uv_crc; 261 }; 262 263 struct sti_hqvdp_fmd_status { 264 u32 fmd_repeat_move_status; 265 u32 fmd_scene_count_status; 266 u32 cfd_sum; 267 u32 field_sum; 268 u32 next_y_fmd_crc; 269 u32 next_next_y_fmd_crc; 270 u32 next_next_next_y_fmd_crc; 271 }; 272 273 struct sti_hqvdp_csdi_status { 274 u32 prev_y_csdi_crc; 275 u32 cur_y_csdi_crc; 276 u32 next_y_csdi_crc; 277 u32 prev_uv_csdi_crc; 278 u32 cur_uv_csdi_crc; 279 u32 next_uv_csdi_crc; 280 u32 y_csdi_crc; 281 u32 uv_csdi_crc; 282 u32 uv_cup_crc; 283 u32 mot_csdi_crc; 284 u32 mot_cur_csdi_crc; 285 u32 mot_prev_csdi_crc; 286 }; 287 288 struct sti_hqvdp_hvsrc_status { 289 u32 y_hvsrc_crc; 290 u32 u_hvsrc_crc; 291 u32 v_hvsrc_crc; 292 }; 293 294 struct sti_hqvdp_iqi_status { 295 u32 pxf_it_status; 296 u32 y_iqi_crc; 297 u32 u_iqi_crc; 298 u32 v_iqi_crc; 299 }; 300 301 /* Main commands. We use 2 commands one being processed by the firmware, one 302 * ready to be fetched upon next Vsync*/ 303 #define NB_VDP_CMD 2 304 305 struct sti_hqvdp_cmd { 306 struct sti_hqvdp_top top; 307 struct sti_hqvdp_vc1re vc1re; 308 struct sti_hqvdp_fmd fmd; 309 struct sti_hqvdp_csdi csdi; 310 struct sti_hqvdp_hvsrc hvsrc; 311 struct sti_hqvdp_iqi iqi; 312 struct sti_hqvdp_top_status top_status; 313 struct sti_hqvdp_fmd_status fmd_status; 314 struct sti_hqvdp_csdi_status csdi_status; 315 struct sti_hqvdp_hvsrc_status hvsrc_status; 316 struct sti_hqvdp_iqi_status iqi_status; 317 }; 318 319 /* 320 * STI HQVDP structure 321 * 322 * @dev: driver device 323 * @drm_dev: the drm device 324 * @regs: registers 325 * @plane: plane structure for hqvdp it self 326 * @clk: IP clock 327 * @clk_pix_main: pix main clock 328 * @reset: reset control 329 * @vtg_nb: notifier to handle VTG Vsync 330 * @btm_field_pending: is there any bottom field (interlaced frame) to display 331 * @hqvdp_cmd: buffer of commands 332 * @hqvdp_cmd_paddr: physical address of hqvdp_cmd 333 * @vtg: vtg for main data path 334 * @xp70_initialized: true if xp70 is already initialized 335 */ 336 struct sti_hqvdp { 337 struct device *dev; 338 struct drm_device *drm_dev; 339 void __iomem *regs; 340 struct sti_plane plane; 341 struct clk *clk; 342 struct clk *clk_pix_main; 343 struct reset_control *reset; 344 struct notifier_block vtg_nb; 345 bool btm_field_pending; 346 void *hqvdp_cmd; 347 u32 hqvdp_cmd_paddr; 348 struct sti_vtg *vtg; 349 bool xp70_initialized; 350 }; 351 352 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane) 353 354 static const uint32_t hqvdp_supported_formats[] = { 355 DRM_FORMAT_NV12, 356 }; 357 358 /** 359 * sti_hqvdp_get_free_cmd 360 * @hqvdp: hqvdp structure 361 * 362 * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW. 363 * 364 * RETURNS: 365 * the offset of the command to be used. 366 * -1 in error cases 367 */ 368 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp) 369 { 370 u32 curr_cmd, next_cmd; 371 u32 cmd = hqvdp->hqvdp_cmd_paddr; 372 int i; 373 374 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 375 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 376 377 for (i = 0; i < NB_VDP_CMD; i++) { 378 if ((cmd != curr_cmd) && (cmd != next_cmd)) 379 return i * sizeof(struct sti_hqvdp_cmd); 380 cmd += sizeof(struct sti_hqvdp_cmd); 381 } 382 383 return -1; 384 } 385 386 /** 387 * sti_hqvdp_get_curr_cmd 388 * @hqvdp: hqvdp structure 389 * 390 * Look for the hqvdp_cmd that is being used by the FW. 391 * 392 * RETURNS: 393 * the offset of the command to be used. 394 * -1 in error cases 395 */ 396 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp) 397 { 398 u32 curr_cmd; 399 u32 cmd = hqvdp->hqvdp_cmd_paddr; 400 unsigned int i; 401 402 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 403 404 for (i = 0; i < NB_VDP_CMD; i++) { 405 if (cmd == curr_cmd) 406 return i * sizeof(struct sti_hqvdp_cmd); 407 408 cmd += sizeof(struct sti_hqvdp_cmd); 409 } 410 411 return -1; 412 } 413 414 /** 415 * sti_hqvdp_get_next_cmd 416 * @hqvdp: hqvdp structure 417 * 418 * Look for the next hqvdp_cmd that will be used by the FW. 419 * 420 * RETURNS: 421 * the offset of the next command that will be used. 422 * -1 in error cases 423 */ 424 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp *hqvdp) 425 { 426 int next_cmd; 427 dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr; 428 unsigned int i; 429 430 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 431 432 for (i = 0; i < NB_VDP_CMD; i++) { 433 if (cmd == next_cmd) 434 return i * sizeof(struct sti_hqvdp_cmd); 435 436 cmd += sizeof(struct sti_hqvdp_cmd); 437 } 438 439 return -1; 440 } 441 442 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 443 readl(hqvdp->regs + reg)) 444 445 static const char *hqvdp_dbg_get_lut(u32 *coef) 446 { 447 if (!memcmp(coef, coef_lut_a_legacy, 16)) 448 return "LUT A"; 449 if (!memcmp(coef, coef_lut_b, 16)) 450 return "LUT B"; 451 if (!memcmp(coef, coef_lut_c_y_legacy, 16)) 452 return "LUT C Y"; 453 if (!memcmp(coef, coef_lut_c_c_legacy, 16)) 454 return "LUT C C"; 455 if (!memcmp(coef, coef_lut_d_y_legacy, 16)) 456 return "LUT D Y"; 457 if (!memcmp(coef, coef_lut_d_c_legacy, 16)) 458 return "LUT D C"; 459 if (!memcmp(coef, coef_lut_e_y_legacy, 16)) 460 return "LUT E Y"; 461 if (!memcmp(coef, coef_lut_e_c_legacy, 16)) 462 return "LUT E C"; 463 if (!memcmp(coef, coef_lut_f_y_legacy, 16)) 464 return "LUT F Y"; 465 if (!memcmp(coef, coef_lut_f_c_legacy, 16)) 466 return "LUT F C"; 467 return "<UNKNOWN>"; 468 } 469 470 static void hqvdp_dbg_dump_cmd(struct seq_file *s, struct sti_hqvdp_cmd *c) 471 { 472 int src_w, src_h, dst_w, dst_h; 473 474 seq_puts(s, "\n\tTOP:"); 475 seq_printf(s, "\n\t %-20s 0x%08X", "Config", c->top.config); 476 switch (c->top.config) { 477 case TOP_CONFIG_PROGRESSIVE: 478 seq_puts(s, "\tProgressive"); 479 break; 480 case TOP_CONFIG_INTER_TOP: 481 seq_puts(s, "\tInterlaced, top field"); 482 break; 483 case TOP_CONFIG_INTER_BTM: 484 seq_puts(s, "\tInterlaced, bottom field"); 485 break; 486 default: 487 seq_puts(s, "\t<UNKNOWN>"); 488 break; 489 } 490 491 seq_printf(s, "\n\t %-20s 0x%08X", "MemFormat", c->top.mem_format); 492 seq_printf(s, "\n\t %-20s 0x%08X", "CurrentY", c->top.current_luma); 493 seq_printf(s, "\n\t %-20s 0x%08X", "CurrentC", c->top.current_chroma); 494 seq_printf(s, "\n\t %-20s 0x%08X", "YSrcPitch", c->top.luma_src_pitch); 495 seq_printf(s, "\n\t %-20s 0x%08X", "CSrcPitch", 496 c->top.chroma_src_pitch); 497 seq_printf(s, "\n\t %-20s 0x%08X", "InputFrameSize", 498 c->top.input_frame_size); 499 seq_printf(s, "\t%dx%d", 500 c->top.input_frame_size & 0x0000FFFF, 501 c->top.input_frame_size >> 16); 502 seq_printf(s, "\n\t %-20s 0x%08X", "InputViewportSize", 503 c->top.input_viewport_size); 504 src_w = c->top.input_viewport_size & 0x0000FFFF; 505 src_h = c->top.input_viewport_size >> 16; 506 seq_printf(s, "\t%dx%d", src_w, src_h); 507 508 seq_puts(s, "\n\tHVSRC:"); 509 seq_printf(s, "\n\t %-20s 0x%08X", "OutputPictureSize", 510 c->hvsrc.output_picture_size); 511 dst_w = c->hvsrc.output_picture_size & 0x0000FFFF; 512 dst_h = c->hvsrc.output_picture_size >> 16; 513 seq_printf(s, "\t%dx%d", dst_w, dst_h); 514 seq_printf(s, "\n\t %-20s 0x%08X", "ParamCtrl", c->hvsrc.param_ctrl); 515 516 seq_printf(s, "\n\t %-20s %s", "yh_coef", 517 hqvdp_dbg_get_lut(c->hvsrc.yh_coef)); 518 seq_printf(s, "\n\t %-20s %s", "ch_coef", 519 hqvdp_dbg_get_lut(c->hvsrc.ch_coef)); 520 seq_printf(s, "\n\t %-20s %s", "yv_coef", 521 hqvdp_dbg_get_lut(c->hvsrc.yv_coef)); 522 seq_printf(s, "\n\t %-20s %s", "cv_coef", 523 hqvdp_dbg_get_lut(c->hvsrc.cv_coef)); 524 525 seq_printf(s, "\n\t %-20s", "ScaleH"); 526 if (dst_w > src_w) 527 seq_printf(s, " %d/1", dst_w / src_w); 528 else 529 seq_printf(s, " 1/%d", src_w / dst_w); 530 531 seq_printf(s, "\n\t %-20s", "tScaleV"); 532 if (dst_h > src_h) 533 seq_printf(s, " %d/1", dst_h / src_h); 534 else 535 seq_printf(s, " 1/%d", src_h / dst_h); 536 537 seq_puts(s, "\n\tCSDI:"); 538 seq_printf(s, "\n\t %-20s 0x%08X\t", "Config", c->csdi.config); 539 switch (c->csdi.config) { 540 case CSDI_CONFIG_PROG: 541 seq_puts(s, "Bypass"); 542 break; 543 case CSDI_CONFIG_INTER_DIR: 544 seq_puts(s, "Deinterlace, directional"); 545 break; 546 default: 547 seq_puts(s, "<UNKNOWN>"); 548 break; 549 } 550 551 seq_printf(s, "\n\t %-20s 0x%08X", "Config2", c->csdi.config2); 552 seq_printf(s, "\n\t %-20s 0x%08X", "DcdiConfig", c->csdi.dcdi_config); 553 } 554 555 static int hqvdp_dbg_show(struct seq_file *s, void *data) 556 { 557 struct drm_info_node *node = s->private; 558 struct sti_hqvdp *hqvdp = (struct sti_hqvdp *)node->info_ent->data; 559 int cmd, cmd_offset, infoxp70; 560 void *virt; 561 562 seq_printf(s, "%s: (vaddr = 0x%p)", 563 sti_plane_to_str(&hqvdp->plane), hqvdp->regs); 564 565 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70); 566 DBGFS_DUMP(HQVDP_MBX_INFO_HOST); 567 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST); 568 DBGFS_DUMP(HQVDP_MBX_INFO_XP70); 569 infoxp70 = readl(hqvdp->regs + HQVDP_MBX_INFO_XP70); 570 seq_puts(s, "\tFirmware state: "); 571 if (infoxp70 & INFO_XP70_FW_READY) 572 seq_puts(s, "idle and ready"); 573 else if (infoxp70 & INFO_XP70_FW_PROCESSING) 574 seq_puts(s, "processing a picture"); 575 else if (infoxp70 & INFO_XP70_FW_INITQUEUES) 576 seq_puts(s, "programming queues"); 577 else 578 seq_puts(s, "NOT READY"); 579 580 DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL); 581 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1); 582 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1) 583 & STARTUP_CTRL1_RST_DONE) 584 seq_puts(s, "\tReset is done"); 585 else 586 seq_puts(s, "\tReset is NOT done"); 587 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2); 588 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2) 589 & STARTUP_CTRL2_FETCH_EN) 590 seq_puts(s, "\tFetch is enabled"); 591 else 592 seq_puts(s, "\tFetch is NOT enabled"); 593 DBGFS_DUMP(HQVDP_MBX_GP_STATUS); 594 DBGFS_DUMP(HQVDP_MBX_NEXT_CMD); 595 DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD); 596 DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC); 597 if (!(readl(hqvdp->regs + HQVDP_MBX_SOFT_VSYNC) & 3)) 598 seq_puts(s, "\tHW Vsync"); 599 else 600 seq_puts(s, "\tSW Vsync ?!?!"); 601 602 /* Last command */ 603 cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 604 cmd_offset = sti_hqvdp_get_curr_cmd(hqvdp); 605 if (cmd_offset == -1) { 606 seq_puts(s, "\n\n Last command: unknown"); 607 } else { 608 virt = hqvdp->hqvdp_cmd + cmd_offset; 609 seq_printf(s, "\n\n Last command: address @ 0x%x (0x%p)", 610 cmd, virt); 611 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt); 612 } 613 614 /* Next command */ 615 cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 616 cmd_offset = sti_hqvdp_get_next_cmd(hqvdp); 617 if (cmd_offset == -1) { 618 seq_puts(s, "\n\n Next command: unknown"); 619 } else { 620 virt = hqvdp->hqvdp_cmd + cmd_offset; 621 seq_printf(s, "\n\n Next command address: @ 0x%x (0x%p)", 622 cmd, virt); 623 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt); 624 } 625 626 seq_puts(s, "\n"); 627 628 return 0; 629 } 630 631 static struct drm_info_list hqvdp_debugfs_files[] = { 632 { "hqvdp", hqvdp_dbg_show, 0, NULL }, 633 }; 634 635 static int hqvdp_debugfs_init(struct sti_hqvdp *hqvdp, struct drm_minor *minor) 636 { 637 unsigned int i; 638 639 for (i = 0; i < ARRAY_SIZE(hqvdp_debugfs_files); i++) 640 hqvdp_debugfs_files[i].data = hqvdp; 641 642 return drm_debugfs_create_files(hqvdp_debugfs_files, 643 ARRAY_SIZE(hqvdp_debugfs_files), 644 minor->debugfs_root, minor); 645 } 646 647 /** 648 * sti_hqvdp_update_hvsrc 649 * @orient: horizontal or vertical 650 * @scale: scaling/zoom factor 651 * @hvsrc: the structure containing the LUT coef 652 * 653 * Update the Y and C Lut coef, as well as the shift param 654 * 655 * RETURNS: 656 * None. 657 */ 658 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale, 659 struct sti_hqvdp_hvsrc *hvsrc) 660 { 661 const int *coef_c, *coef_y; 662 int shift_c, shift_y; 663 664 /* Get the appropriate coef tables */ 665 if (scale < SCALE_MAX_FOR_LEG_LUT_F) { 666 coef_y = coef_lut_f_y_legacy; 667 coef_c = coef_lut_f_c_legacy; 668 shift_y = SHIFT_LUT_F_Y_LEGACY; 669 shift_c = SHIFT_LUT_F_C_LEGACY; 670 } else if (scale < SCALE_MAX_FOR_LEG_LUT_E) { 671 coef_y = coef_lut_e_y_legacy; 672 coef_c = coef_lut_e_c_legacy; 673 shift_y = SHIFT_LUT_E_Y_LEGACY; 674 shift_c = SHIFT_LUT_E_C_LEGACY; 675 } else if (scale < SCALE_MAX_FOR_LEG_LUT_D) { 676 coef_y = coef_lut_d_y_legacy; 677 coef_c = coef_lut_d_c_legacy; 678 shift_y = SHIFT_LUT_D_Y_LEGACY; 679 shift_c = SHIFT_LUT_D_C_LEGACY; 680 } else if (scale < SCALE_MAX_FOR_LEG_LUT_C) { 681 coef_y = coef_lut_c_y_legacy; 682 coef_c = coef_lut_c_c_legacy; 683 shift_y = SHIFT_LUT_C_Y_LEGACY; 684 shift_c = SHIFT_LUT_C_C_LEGACY; 685 } else if (scale == SCALE_MAX_FOR_LEG_LUT_C) { 686 coef_y = coef_c = coef_lut_b; 687 shift_y = shift_c = SHIFT_LUT_B; 688 } else { 689 coef_y = coef_c = coef_lut_a_legacy; 690 shift_y = shift_c = SHIFT_LUT_A_LEGACY; 691 } 692 693 if (orient == HVSRC_HORI) { 694 hvsrc->hori_shift = (shift_c << 16) | shift_y; 695 memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef)); 696 memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef)); 697 } else { 698 hvsrc->vert_shift = (shift_c << 16) | shift_y; 699 memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef)); 700 memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef)); 701 } 702 } 703 704 /** 705 * sti_hqvdp_check_hw_scaling 706 * @hqvdp: hqvdp pointer 707 * @mode: display mode with timing constraints 708 * @src_w: source width 709 * @src_h: source height 710 * @dst_w: destination width 711 * @dst_h: destination height 712 * 713 * Check if the HW is able to perform the scaling request 714 * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where: 715 * Zy = OutputHeight / InputHeight 716 * LFW = (Tx * IPClock) / (MaxNbCycles * Cp) 717 * Tx : Total video mode horizontal resolution 718 * IPClock : HQVDP IP clock (Mhz) 719 * MaxNbCycles: max(InputWidth, OutputWidth) 720 * Cp: Video mode pixel clock (Mhz) 721 * 722 * RETURNS: 723 * True if the HW can scale. 724 */ 725 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp *hqvdp, 726 struct drm_display_mode *mode, 727 int src_w, int src_h, 728 int dst_w, int dst_h) 729 { 730 unsigned long lfw; 731 unsigned int inv_zy; 732 733 lfw = mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000); 734 lfw /= max(src_w, dst_w) * mode->clock / 1000; 735 736 inv_zy = DIV_ROUND_UP(src_h, dst_h); 737 738 return (inv_zy <= lfw) ? true : false; 739 } 740 741 /** 742 * sti_hqvdp_disable 743 * @hqvdp: hqvdp pointer 744 * 745 * Disables the HQVDP plane 746 */ 747 static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp) 748 { 749 int i; 750 751 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp->plane)); 752 753 /* Unregister VTG Vsync callback */ 754 if (sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb)) 755 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 756 757 /* Set next cmd to NULL */ 758 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); 759 760 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 761 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70) 762 & INFO_XP70_FW_READY) 763 break; 764 msleep(POLL_DELAY_MS); 765 } 766 767 /* VTG can stop now */ 768 clk_disable_unprepare(hqvdp->clk_pix_main); 769 770 if (i == POLL_MAX_ATTEMPT) 771 DRM_ERROR("XP70 could not revert to idle\n"); 772 773 hqvdp->plane.status = STI_PLANE_DISABLED; 774 hqvdp->xp70_initialized = false; 775 } 776 777 /** 778 * sti_vdp_vtg_cb 779 * @nb: notifier block 780 * @evt: event message 781 * @data: private data 782 * 783 * Handle VTG Vsync event, display pending bottom field 784 * 785 * RETURNS: 786 * 0 on success. 787 */ 788 static int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data) 789 { 790 struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb); 791 int btm_cmd_offset, top_cmd_offest; 792 struct sti_hqvdp_cmd *btm_cmd, *top_cmd; 793 794 if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) { 795 DRM_DEBUG_DRIVER("Unknown event\n"); 796 return 0; 797 } 798 799 if (hqvdp->plane.status == STI_PLANE_FLUSHING) { 800 /* disable need to be synchronize on vsync event */ 801 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 802 sti_plane_to_str(&hqvdp->plane)); 803 804 sti_hqvdp_disable(hqvdp); 805 } 806 807 if (hqvdp->btm_field_pending) { 808 /* Create the btm field command from the current one */ 809 btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp); 810 top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp); 811 if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) { 812 DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n"); 813 return -EBUSY; 814 } 815 816 btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset; 817 top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest; 818 819 memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd)); 820 821 btm_cmd->top.config = TOP_CONFIG_INTER_BTM; 822 btm_cmd->top.current_luma += 823 btm_cmd->top.luma_src_pitch / 2; 824 btm_cmd->top.current_chroma += 825 btm_cmd->top.chroma_src_pitch / 2; 826 827 /* Post the command to mailbox */ 828 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset, 829 hqvdp->regs + HQVDP_MBX_NEXT_CMD); 830 831 hqvdp->btm_field_pending = false; 832 833 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n", 834 __func__, hqvdp->hqvdp_cmd_paddr); 835 836 sti_plane_update_fps(&hqvdp->plane, false, true); 837 } 838 839 return 0; 840 } 841 842 static void sti_hqvdp_init(struct sti_hqvdp *hqvdp) 843 { 844 int size; 845 dma_addr_t dma_addr; 846 847 hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb; 848 849 /* Allocate memory for the VDP commands */ 850 size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd); 851 hqvdp->hqvdp_cmd = dma_alloc_wc(hqvdp->dev, size, 852 &dma_addr, 853 GFP_KERNEL | GFP_DMA); 854 if (!hqvdp->hqvdp_cmd) { 855 DRM_ERROR("Failed to allocate memory for VDP cmd\n"); 856 return; 857 } 858 859 hqvdp->hqvdp_cmd_paddr = (u32)dma_addr; 860 memset(hqvdp->hqvdp_cmd, 0, size); 861 } 862 863 static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp) 864 { 865 /* Configure Plugs (same for RD & WR) */ 866 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE); 867 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC); 868 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC); 869 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK); 870 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG); 871 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE); 872 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL); 873 874 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE); 875 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC); 876 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC); 877 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK); 878 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG); 879 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE); 880 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL); 881 } 882 883 /** 884 * sti_hqvdp_start_xp70 885 * @hqvdp: hqvdp pointer 886 * 887 * Run the xP70 initialization sequence 888 */ 889 static void sti_hqvdp_start_xp70(struct sti_hqvdp *hqvdp) 890 { 891 const struct firmware *firmware; 892 u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem; 893 u8 *data; 894 int i; 895 struct fw_header { 896 int rd_size; 897 int wr_size; 898 int pmem_size; 899 int dmem_size; 900 } *header; 901 902 DRM_DEBUG_DRIVER("\n"); 903 904 if (hqvdp->xp70_initialized) { 905 DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n"); 906 return; 907 } 908 909 /* Request firmware */ 910 if (request_firmware(&firmware, HQVDP_FMW_NAME, hqvdp->dev)) { 911 DRM_ERROR("Can't get HQVDP firmware\n"); 912 return; 913 } 914 915 /* Check firmware parts */ 916 if (!firmware) { 917 DRM_ERROR("Firmware not available\n"); 918 return; 919 } 920 921 header = (struct fw_header *)firmware->data; 922 if (firmware->size < sizeof(*header)) { 923 DRM_ERROR("Invalid firmware size (%d)\n", firmware->size); 924 goto out; 925 } 926 if ((sizeof(*header) + header->rd_size + header->wr_size + 927 header->pmem_size + header->dmem_size) != firmware->size) { 928 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n", 929 sizeof(*header), header->rd_size, header->wr_size, 930 header->pmem_size, header->dmem_size, 931 firmware->size); 932 goto out; 933 } 934 935 data = (u8 *)firmware->data; 936 data += sizeof(*header); 937 fw_rd_plug = (void *)data; 938 data += header->rd_size; 939 fw_wr_plug = (void *)data; 940 data += header->wr_size; 941 fw_pmem = (void *)data; 942 data += header->pmem_size; 943 fw_dmem = (void *)data; 944 945 /* Enable clock */ 946 if (clk_prepare_enable(hqvdp->clk)) 947 DRM_ERROR("Failed to prepare/enable HQVDP clk\n"); 948 949 /* Reset */ 950 writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL); 951 952 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 953 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1) 954 & STARTUP_CTRL1_RST_DONE) 955 break; 956 msleep(POLL_DELAY_MS); 957 } 958 if (i == POLL_MAX_ATTEMPT) { 959 DRM_ERROR("Could not reset\n"); 960 goto out; 961 } 962 963 /* Init Read & Write plugs */ 964 for (i = 0; i < header->rd_size / 4; i++) 965 writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4); 966 for (i = 0; i < header->wr_size / 4; i++) 967 writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4); 968 969 sti_hqvdp_init_plugs(hqvdp); 970 971 /* Authorize Idle Mode */ 972 writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1); 973 974 /* Prevent VTG interruption during the boot */ 975 writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC); 976 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); 977 978 /* Download PMEM & DMEM */ 979 for (i = 0; i < header->pmem_size / 4; i++) 980 writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4); 981 for (i = 0; i < header->dmem_size / 4; i++) 982 writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4); 983 984 /* Enable fetch */ 985 writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2); 986 987 /* Wait end of boot */ 988 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 989 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70) 990 & INFO_XP70_FW_READY) 991 break; 992 msleep(POLL_DELAY_MS); 993 } 994 if (i == POLL_MAX_ATTEMPT) { 995 DRM_ERROR("Could not boot\n"); 996 goto out; 997 } 998 999 /* Launch Vsync */ 1000 writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC); 1001 1002 DRM_INFO("HQVDP XP70 initialized\n"); 1003 1004 hqvdp->xp70_initialized = true; 1005 1006 out: 1007 release_firmware(firmware); 1008 } 1009 1010 static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane, 1011 struct drm_plane_state *state) 1012 { 1013 struct sti_plane *plane = to_sti_plane(drm_plane); 1014 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1015 struct drm_crtc *crtc = state->crtc; 1016 struct drm_framebuffer *fb = state->fb; 1017 struct drm_crtc_state *crtc_state; 1018 struct drm_display_mode *mode; 1019 int dst_x, dst_y, dst_w, dst_h; 1020 int src_x, src_y, src_w, src_h; 1021 1022 /* no need for further checks if the plane is being disabled */ 1023 if (!crtc || !fb) 1024 return 0; 1025 1026 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 1027 mode = &crtc_state->mode; 1028 dst_x = state->crtc_x; 1029 dst_y = state->crtc_y; 1030 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 1031 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 1032 /* src_x are in 16.16 format */ 1033 src_x = state->src_x >> 16; 1034 src_y = state->src_y >> 16; 1035 src_w = state->src_w >> 16; 1036 src_h = state->src_h >> 16; 1037 1038 if (!sti_hqvdp_check_hw_scaling(hqvdp, mode, 1039 src_w, src_h, 1040 dst_w, dst_h)) { 1041 DRM_ERROR("Scaling beyond HW capabilities\n"); 1042 return -EINVAL; 1043 } 1044 1045 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 1046 DRM_ERROR("Can't get CMA GEM object for fb\n"); 1047 return -EINVAL; 1048 } 1049 1050 /* 1051 * Input / output size 1052 * Align to upper even value 1053 */ 1054 dst_w = ALIGN(dst_w, 2); 1055 dst_h = ALIGN(dst_h, 2); 1056 1057 if ((src_w > MAX_WIDTH) || (src_w < MIN_WIDTH) || 1058 (src_h > MAX_HEIGHT) || (src_h < MIN_HEIGHT) || 1059 (dst_w > MAX_WIDTH) || (dst_w < MIN_WIDTH) || 1060 (dst_h > MAX_HEIGHT) || (dst_h < MIN_HEIGHT)) { 1061 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n", 1062 src_w, src_h, 1063 dst_w, dst_h); 1064 return -EINVAL; 1065 } 1066 1067 if (!hqvdp->xp70_initialized) { 1068 /* Start HQVDP XP70 coprocessor */ 1069 sti_hqvdp_start_xp70(hqvdp); 1070 1071 /* Prevent VTG shutdown */ 1072 if (clk_prepare_enable(hqvdp->clk_pix_main)) { 1073 DRM_ERROR("Failed to prepare/enable pix main clk\n"); 1074 return -EINVAL; 1075 } 1076 1077 /* Register VTG Vsync callback to handle bottom fields */ 1078 if (sti_vtg_register_client(hqvdp->vtg, 1079 &hqvdp->vtg_nb, 1080 crtc)) { 1081 DRM_ERROR("Cannot register VTG notifier\n"); 1082 return -EINVAL; 1083 } 1084 } 1085 1086 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 1087 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)), 1088 drm_plane->base.id, sti_plane_to_str(plane)); 1089 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 1090 sti_plane_to_str(plane), 1091 dst_w, dst_h, dst_x, dst_y, 1092 src_w, src_h, src_x, src_y); 1093 1094 return 0; 1095 } 1096 1097 static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane, 1098 struct drm_plane_state *oldstate) 1099 { 1100 struct drm_plane_state *state = drm_plane->state; 1101 struct sti_plane *plane = to_sti_plane(drm_plane); 1102 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1103 struct drm_crtc *crtc = state->crtc; 1104 struct drm_framebuffer *fb = state->fb; 1105 struct drm_display_mode *mode; 1106 int dst_x, dst_y, dst_w, dst_h; 1107 int src_x, src_y, src_w, src_h; 1108 struct drm_gem_cma_object *cma_obj; 1109 struct sti_hqvdp_cmd *cmd; 1110 int scale_h, scale_v; 1111 int cmd_offset; 1112 1113 if (!crtc || !fb) 1114 return; 1115 1116 mode = &crtc->mode; 1117 dst_x = state->crtc_x; 1118 dst_y = state->crtc_y; 1119 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 1120 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 1121 /* src_x are in 16.16 format */ 1122 src_x = state->src_x >> 16; 1123 src_y = state->src_y >> 16; 1124 src_w = state->src_w >> 16; 1125 src_h = state->src_h >> 16; 1126 1127 cmd_offset = sti_hqvdp_get_free_cmd(hqvdp); 1128 if (cmd_offset == -1) { 1129 DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n"); 1130 return; 1131 } 1132 cmd = hqvdp->hqvdp_cmd + cmd_offset; 1133 1134 /* Static parameters, defaulting to progressive mode */ 1135 cmd->top.config = TOP_CONFIG_PROGRESSIVE; 1136 cmd->top.mem_format = TOP_MEM_FORMAT_DFLT; 1137 cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT; 1138 cmd->csdi.config = CSDI_CONFIG_PROG; 1139 1140 /* VC1RE, FMD bypassed : keep everything set to 0 1141 * IQI/P2I bypassed */ 1142 cmd->iqi.config = IQI_CONFIG_DFLT; 1143 cmd->iqi.con_bri = IQI_CON_BRI_DFLT; 1144 cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT; 1145 cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT; 1146 1147 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 1148 1149 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 1150 (char *)&fb->pixel_format, 1151 (unsigned long)cma_obj->paddr); 1152 1153 /* Buffer planes address */ 1154 cmd->top.current_luma = (u32)cma_obj->paddr + fb->offsets[0]; 1155 cmd->top.current_chroma = (u32)cma_obj->paddr + fb->offsets[1]; 1156 1157 /* Pitches */ 1158 cmd->top.luma_processed_pitch = fb->pitches[0]; 1159 cmd->top.luma_src_pitch = fb->pitches[0]; 1160 cmd->top.chroma_processed_pitch = fb->pitches[1]; 1161 cmd->top.chroma_src_pitch = fb->pitches[1]; 1162 1163 /* Input / output size 1164 * Align to upper even value */ 1165 dst_w = ALIGN(dst_w, 2); 1166 dst_h = ALIGN(dst_h, 2); 1167 1168 cmd->top.input_viewport_size = src_h << 16 | src_w; 1169 cmd->top.input_frame_size = src_h << 16 | src_w; 1170 cmd->hvsrc.output_picture_size = dst_h << 16 | dst_w; 1171 cmd->top.input_viewport_ori = src_y << 16 | src_x; 1172 1173 /* Handle interlaced */ 1174 if (fb->flags & DRM_MODE_FB_INTERLACED) { 1175 /* Top field to display */ 1176 cmd->top.config = TOP_CONFIG_INTER_TOP; 1177 1178 /* Update pitches and vert size */ 1179 cmd->top.input_frame_size = (src_h / 2) << 16 | src_w; 1180 cmd->top.luma_processed_pitch *= 2; 1181 cmd->top.luma_src_pitch *= 2; 1182 cmd->top.chroma_processed_pitch *= 2; 1183 cmd->top.chroma_src_pitch *= 2; 1184 1185 /* Enable directional deinterlacing processing */ 1186 cmd->csdi.config = CSDI_CONFIG_INTER_DIR; 1187 cmd->csdi.config2 = CSDI_CONFIG2_DFLT; 1188 cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT; 1189 } 1190 1191 /* Update hvsrc lut coef */ 1192 scale_h = SCALE_FACTOR * dst_w / src_w; 1193 sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc); 1194 1195 scale_v = SCALE_FACTOR * dst_h / src_h; 1196 sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc); 1197 1198 writel(hqvdp->hqvdp_cmd_paddr + cmd_offset, 1199 hqvdp->regs + HQVDP_MBX_NEXT_CMD); 1200 1201 /* Interlaced : get ready to display the bottom field at next Vsync */ 1202 if (fb->flags & DRM_MODE_FB_INTERLACED) 1203 hqvdp->btm_field_pending = true; 1204 1205 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n", 1206 __func__, hqvdp->hqvdp_cmd_paddr + cmd_offset); 1207 1208 sti_plane_update_fps(plane, true, true); 1209 1210 plane->status = STI_PLANE_UPDATED; 1211 } 1212 1213 static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane, 1214 struct drm_plane_state *oldstate) 1215 { 1216 struct sti_plane *plane = to_sti_plane(drm_plane); 1217 1218 if (!oldstate->crtc) { 1219 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 1220 drm_plane->base.id); 1221 return; 1222 } 1223 1224 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 1225 oldstate->crtc->base.id, 1226 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 1227 drm_plane->base.id, sti_plane_to_str(plane)); 1228 1229 plane->status = STI_PLANE_DISABLING; 1230 } 1231 1232 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs = { 1233 .atomic_check = sti_hqvdp_atomic_check, 1234 .atomic_update = sti_hqvdp_atomic_update, 1235 .atomic_disable = sti_hqvdp_atomic_disable, 1236 }; 1237 1238 static void sti_hqvdp_destroy(struct drm_plane *drm_plane) 1239 { 1240 DRM_DEBUG_DRIVER("\n"); 1241 1242 drm_plane_helper_disable(drm_plane); 1243 drm_plane_cleanup(drm_plane); 1244 } 1245 1246 static int sti_hqvdp_late_register(struct drm_plane *drm_plane) 1247 { 1248 struct sti_plane *plane = to_sti_plane(drm_plane); 1249 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1250 1251 return hqvdp_debugfs_init(hqvdp, drm_plane->dev->primary); 1252 } 1253 1254 static const struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs = { 1255 .update_plane = drm_atomic_helper_update_plane, 1256 .disable_plane = drm_atomic_helper_disable_plane, 1257 .destroy = sti_hqvdp_destroy, 1258 .set_property = drm_atomic_helper_plane_set_property, 1259 .reset = sti_plane_reset, 1260 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1261 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1262 .late_register = sti_hqvdp_late_register, 1263 }; 1264 1265 static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev, 1266 struct device *dev, int desc) 1267 { 1268 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev); 1269 int res; 1270 1271 hqvdp->plane.desc = desc; 1272 hqvdp->plane.status = STI_PLANE_DISABLED; 1273 1274 sti_hqvdp_init(hqvdp); 1275 1276 res = drm_universal_plane_init(drm_dev, &hqvdp->plane.drm_plane, 1, 1277 &sti_hqvdp_plane_helpers_funcs, 1278 hqvdp_supported_formats, 1279 ARRAY_SIZE(hqvdp_supported_formats), 1280 DRM_PLANE_TYPE_OVERLAY, NULL); 1281 if (res) { 1282 DRM_ERROR("Failed to initialize universal plane\n"); 1283 return NULL; 1284 } 1285 1286 drm_plane_helper_add(&hqvdp->plane.drm_plane, &sti_hqvdp_helpers_funcs); 1287 1288 sti_plane_init_property(&hqvdp->plane, DRM_PLANE_TYPE_OVERLAY); 1289 1290 return &hqvdp->plane.drm_plane; 1291 } 1292 1293 static int sti_hqvdp_bind(struct device *dev, struct device *master, void *data) 1294 { 1295 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev); 1296 struct drm_device *drm_dev = data; 1297 struct drm_plane *plane; 1298 1299 DRM_DEBUG_DRIVER("\n"); 1300 1301 hqvdp->drm_dev = drm_dev; 1302 1303 /* Create HQVDP plane once xp70 is initialized */ 1304 plane = sti_hqvdp_create(drm_dev, hqvdp->dev, STI_HQVDP_0); 1305 if (!plane) 1306 DRM_ERROR("Can't create HQVDP plane\n"); 1307 1308 return 0; 1309 } 1310 1311 static void sti_hqvdp_unbind(struct device *dev, 1312 struct device *master, void *data) 1313 { 1314 /* do nothing */ 1315 } 1316 1317 static const struct component_ops sti_hqvdp_ops = { 1318 .bind = sti_hqvdp_bind, 1319 .unbind = sti_hqvdp_unbind, 1320 }; 1321 1322 static int sti_hqvdp_probe(struct platform_device *pdev) 1323 { 1324 struct device *dev = &pdev->dev; 1325 struct device_node *vtg_np; 1326 struct sti_hqvdp *hqvdp; 1327 struct resource *res; 1328 1329 DRM_DEBUG_DRIVER("\n"); 1330 1331 hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL); 1332 if (!hqvdp) { 1333 DRM_ERROR("Failed to allocate HQVDP context\n"); 1334 return -ENOMEM; 1335 } 1336 1337 hqvdp->dev = dev; 1338 1339 /* Get Memory resources */ 1340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1341 if (res == NULL) { 1342 DRM_ERROR("Get memory resource failed\n"); 1343 return -ENXIO; 1344 } 1345 hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res)); 1346 if (hqvdp->regs == NULL) { 1347 DRM_ERROR("Register mapping failed\n"); 1348 return -ENXIO; 1349 } 1350 1351 /* Get clock resources */ 1352 hqvdp->clk = devm_clk_get(dev, "hqvdp"); 1353 hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main"); 1354 if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) { 1355 DRM_ERROR("Cannot get clocks\n"); 1356 return -ENXIO; 1357 } 1358 1359 /* Get reset resources */ 1360 hqvdp->reset = devm_reset_control_get(dev, "hqvdp"); 1361 if (!IS_ERR(hqvdp->reset)) 1362 reset_control_deassert(hqvdp->reset); 1363 1364 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0); 1365 if (vtg_np) 1366 hqvdp->vtg = of_vtg_find(vtg_np); 1367 of_node_put(vtg_np); 1368 1369 platform_set_drvdata(pdev, hqvdp); 1370 1371 return component_add(&pdev->dev, &sti_hqvdp_ops); 1372 } 1373 1374 static int sti_hqvdp_remove(struct platform_device *pdev) 1375 { 1376 component_del(&pdev->dev, &sti_hqvdp_ops); 1377 return 0; 1378 } 1379 1380 static struct of_device_id hqvdp_of_match[] = { 1381 { .compatible = "st,stih407-hqvdp", }, 1382 { /* end node */ } 1383 }; 1384 MODULE_DEVICE_TABLE(of, hqvdp_of_match); 1385 1386 struct platform_driver sti_hqvdp_driver = { 1387 .driver = { 1388 .name = "sti-hqvdp", 1389 .owner = THIS_MODULE, 1390 .of_match_table = hqvdp_of_match, 1391 }, 1392 .probe = sti_hqvdp_probe, 1393 .remove = sti_hqvdp_remove, 1394 }; 1395 1396 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 1397 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 1398 MODULE_LICENSE("GPL"); 1399