xref: /openbmc/linux/drivers/gpu/drm/sti/sti_hqvdp.c (revision 0edbfea5)
1 /*
2  * Copyright (C) STMicroelectronics SA 2014
3  * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
4  * License terms:  GNU General Public License (GPL), version 2
5  */
6 
7 #include <linux/component.h>
8 #include <linux/firmware.h>
9 #include <linux/reset.h>
10 #include <linux/seq_file.h>
11 
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_fb_cma_helper.h>
14 #include <drm/drm_gem_cma_helper.h>
15 
16 #include "sti_compositor.h"
17 #include "sti_hqvdp_lut.h"
18 #include "sti_plane.h"
19 #include "sti_vtg.h"
20 
21 /* Firmware name */
22 #define HQVDP_FMW_NAME          "hqvdp-stih407.bin"
23 
24 /* Regs address */
25 #define HQVDP_DMEM              0x00000000               /* 0x00000000 */
26 #define HQVDP_PMEM              0x00040000               /* 0x00040000 */
27 #define HQVDP_RD_PLUG           0x000E0000               /* 0x000E0000 */
28 #define HQVDP_RD_PLUG_CONTROL   (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */
29 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */
30 #define HQVDP_RD_PLUG_MIN_OPC   (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */
31 #define HQVDP_RD_PLUG_MAX_OPC   (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */
32 #define HQVDP_RD_PLUG_MAX_CHK   (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */
33 #define HQVDP_RD_PLUG_MAX_MSG   (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */
34 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */
35 #define HQVDP_WR_PLUG           0x000E2000               /* 0x000E2000 */
36 #define HQVDP_WR_PLUG_CONTROL   (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */
37 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */
38 #define HQVDP_WR_PLUG_MIN_OPC   (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */
39 #define HQVDP_WR_PLUG_MAX_OPC   (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */
40 #define HQVDP_WR_PLUG_MAX_CHK   (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */
41 #define HQVDP_WR_PLUG_MAX_MSG   (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */
42 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */
43 #define HQVDP_MBX               0x000E4000               /* 0x000E4000 */
44 #define HQVDP_MBX_IRQ_TO_XP70   (HQVDP_MBX + 0x0000)     /* 0x000E4000 */
45 #define HQVDP_MBX_INFO_HOST     (HQVDP_MBX + 0x0004)     /* 0x000E4004 */
46 #define HQVDP_MBX_IRQ_TO_HOST   (HQVDP_MBX + 0x0008)     /* 0x000E4008 */
47 #define HQVDP_MBX_INFO_XP70     (HQVDP_MBX + 0x000C)     /* 0x000E400C */
48 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010)     /* 0x000E4010 */
49 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014)     /* 0x000E4014 */
50 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018)     /* 0x000E4018 */
51 #define HQVDP_MBX_GP_STATUS     (HQVDP_MBX + 0x001C)     /* 0x000E401C */
52 #define HQVDP_MBX_NEXT_CMD      (HQVDP_MBX + 0x0020)     /* 0x000E4020 */
53 #define HQVDP_MBX_CURRENT_CMD   (HQVDP_MBX + 0x0024)     /* 0x000E4024 */
54 #define HQVDP_MBX_SOFT_VSYNC    (HQVDP_MBX + 0x0028)     /* 0x000E4028 */
55 
56 /* Plugs config */
57 #define PLUG_CONTROL_ENABLE     0x00000001
58 #define PLUG_PAGE_SIZE_256      0x00000002
59 #define PLUG_MIN_OPC_8          0x00000003
60 #define PLUG_MAX_OPC_64         0x00000006
61 #define PLUG_MAX_CHK_2X         0x00000001
62 #define PLUG_MAX_MSG_1X         0x00000000
63 #define PLUG_MIN_SPACE_1        0x00000000
64 
65 /* SW reset CTRL */
66 #define SW_RESET_CTRL_FULL      BIT(0)
67 #define SW_RESET_CTRL_CORE      BIT(1)
68 
69 /* Startup ctrl 1 */
70 #define STARTUP_CTRL1_RST_DONE  BIT(0)
71 #define STARTUP_CTRL1_AUTH_IDLE BIT(2)
72 
73 /* Startup ctrl 2 */
74 #define STARTUP_CTRL2_FETCH_EN  BIT(1)
75 
76 /* Info xP70 */
77 #define INFO_XP70_FW_READY      BIT(15)
78 #define INFO_XP70_FW_PROCESSING BIT(14)
79 #define INFO_XP70_FW_INITQUEUES BIT(13)
80 
81 /* SOFT_VSYNC */
82 #define SOFT_VSYNC_HW           0x00000000
83 #define SOFT_VSYNC_SW_CMD       0x00000001
84 #define SOFT_VSYNC_SW_CTRL_IRQ  0x00000003
85 
86 /* Reset & boot poll config */
87 #define POLL_MAX_ATTEMPT        50
88 #define POLL_DELAY_MS           20
89 
90 #define SCALE_FACTOR            8192
91 #define SCALE_MAX_FOR_LEG_LUT_F 4096
92 #define SCALE_MAX_FOR_LEG_LUT_E 4915
93 #define SCALE_MAX_FOR_LEG_LUT_D 6654
94 #define SCALE_MAX_FOR_LEG_LUT_C 8192
95 
96 enum sti_hvsrc_orient {
97 	HVSRC_HORI,
98 	HVSRC_VERT
99 };
100 
101 /* Command structures */
102 struct sti_hqvdp_top {
103 	u32 config;
104 	u32 mem_format;
105 	u32 current_luma;
106 	u32 current_enh_luma;
107 	u32 current_right_luma;
108 	u32 current_enh_right_luma;
109 	u32 current_chroma;
110 	u32 current_enh_chroma;
111 	u32 current_right_chroma;
112 	u32 current_enh_right_chroma;
113 	u32 output_luma;
114 	u32 output_chroma;
115 	u32 luma_src_pitch;
116 	u32 luma_enh_src_pitch;
117 	u32 luma_right_src_pitch;
118 	u32 luma_enh_right_src_pitch;
119 	u32 chroma_src_pitch;
120 	u32 chroma_enh_src_pitch;
121 	u32 chroma_right_src_pitch;
122 	u32 chroma_enh_right_src_pitch;
123 	u32 luma_processed_pitch;
124 	u32 chroma_processed_pitch;
125 	u32 input_frame_size;
126 	u32 input_viewport_ori;
127 	u32 input_viewport_ori_right;
128 	u32 input_viewport_size;
129 	u32 left_view_border_width;
130 	u32 right_view_border_width;
131 	u32 left_view_3d_offset_width;
132 	u32 right_view_3d_offset_width;
133 	u32 side_stripe_color;
134 	u32 crc_reset_ctrl;
135 };
136 
137 /* Configs for interlaced : no IT, no pass thru, 3 fields */
138 #define TOP_CONFIG_INTER_BTM            0x00000000
139 #define TOP_CONFIG_INTER_TOP            0x00000002
140 
141 /* Config for progressive : no IT, no pass thru, 3 fields */
142 #define TOP_CONFIG_PROGRESSIVE          0x00000001
143 
144 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */
145 #define TOP_MEM_FORMAT_DFLT             0x00018060
146 
147 /* Min/Max size */
148 #define MAX_WIDTH                       0x1FFF
149 #define MAX_HEIGHT                      0x0FFF
150 #define MIN_WIDTH                       0x0030
151 #define MIN_HEIGHT                      0x0010
152 
153 struct sti_hqvdp_vc1re {
154 	u32 ctrl_prv_csdi;
155 	u32 ctrl_cur_csdi;
156 	u32 ctrl_nxt_csdi;
157 	u32 ctrl_cur_fmd;
158 	u32 ctrl_nxt_fmd;
159 };
160 
161 struct sti_hqvdp_fmd {
162 	u32 config;
163 	u32 viewport_ori;
164 	u32 viewport_size;
165 	u32 next_next_luma;
166 	u32 next_next_right_luma;
167 	u32 next_next_next_luma;
168 	u32 next_next_next_right_luma;
169 	u32 threshold_scd;
170 	u32 threshold_rfd;
171 	u32 threshold_move;
172 	u32 threshold_cfd;
173 };
174 
175 struct sti_hqvdp_csdi {
176 	u32 config;
177 	u32 config2;
178 	u32 dcdi_config;
179 	u32 prev_luma;
180 	u32 prev_enh_luma;
181 	u32 prev_right_luma;
182 	u32 prev_enh_right_luma;
183 	u32 next_luma;
184 	u32 next_enh_luma;
185 	u32 next_right_luma;
186 	u32 next_enh_right_luma;
187 	u32 prev_chroma;
188 	u32 prev_enh_chroma;
189 	u32 prev_right_chroma;
190 	u32 prev_enh_right_chroma;
191 	u32 next_chroma;
192 	u32 next_enh_chroma;
193 	u32 next_right_chroma;
194 	u32 next_enh_right_chroma;
195 	u32 prev_motion;
196 	u32 prev_right_motion;
197 	u32 cur_motion;
198 	u32 cur_right_motion;
199 	u32 next_motion;
200 	u32 next_right_motion;
201 };
202 
203 /* Config for progressive: by pass */
204 #define CSDI_CONFIG_PROG                0x00000000
205 /* Config for directional deinterlacing without motion */
206 #define CSDI_CONFIG_INTER_DIR           0x00000016
207 /* Additional configs for fader, blender, motion,... deinterlace algorithms */
208 #define CSDI_CONFIG2_DFLT               0x000001B3
209 #define CSDI_DCDI_CONFIG_DFLT           0x00203803
210 
211 struct sti_hqvdp_hvsrc {
212 	u32 hor_panoramic_ctrl;
213 	u32 output_picture_size;
214 	u32 init_horizontal;
215 	u32 init_vertical;
216 	u32 param_ctrl;
217 	u32 yh_coef[NB_COEF];
218 	u32 ch_coef[NB_COEF];
219 	u32 yv_coef[NB_COEF];
220 	u32 cv_coef[NB_COEF];
221 	u32 hori_shift;
222 	u32 vert_shift;
223 };
224 
225 /* Default ParamCtrl: all controls enabled */
226 #define HVSRC_PARAM_CTRL_DFLT           0xFFFFFFFF
227 
228 struct sti_hqvdp_iqi {
229 	u32 config;
230 	u32 demo_wind_size;
231 	u32 pk_config;
232 	u32 coeff0_coeff1;
233 	u32 coeff2_coeff3;
234 	u32 coeff4;
235 	u32 pk_lut;
236 	u32 pk_gain;
237 	u32 pk_coring_level;
238 	u32 cti_config;
239 	u32 le_config;
240 	u32 le_lut[64];
241 	u32 con_bri;
242 	u32 sat_gain;
243 	u32 pxf_conf;
244 	u32 default_color;
245 };
246 
247 /* Default Config : IQI bypassed */
248 #define IQI_CONFIG_DFLT                 0x00000001
249 /* Default Contrast & Brightness gain = 256 */
250 #define IQI_CON_BRI_DFLT                0x00000100
251 /* Default Saturation gain = 256 */
252 #define IQI_SAT_GAIN_DFLT               0x00000100
253 /* Default PxfConf : P2I bypassed */
254 #define IQI_PXF_CONF_DFLT               0x00000001
255 
256 struct sti_hqvdp_top_status {
257 	u32 processing_time;
258 	u32 input_y_crc;
259 	u32 input_uv_crc;
260 };
261 
262 struct sti_hqvdp_fmd_status {
263 	u32 fmd_repeat_move_status;
264 	u32 fmd_scene_count_status;
265 	u32 cfd_sum;
266 	u32 field_sum;
267 	u32 next_y_fmd_crc;
268 	u32 next_next_y_fmd_crc;
269 	u32 next_next_next_y_fmd_crc;
270 };
271 
272 struct sti_hqvdp_csdi_status {
273 	u32 prev_y_csdi_crc;
274 	u32 cur_y_csdi_crc;
275 	u32 next_y_csdi_crc;
276 	u32 prev_uv_csdi_crc;
277 	u32 cur_uv_csdi_crc;
278 	u32 next_uv_csdi_crc;
279 	u32 y_csdi_crc;
280 	u32 uv_csdi_crc;
281 	u32 uv_cup_crc;
282 	u32 mot_csdi_crc;
283 	u32 mot_cur_csdi_crc;
284 	u32 mot_prev_csdi_crc;
285 };
286 
287 struct sti_hqvdp_hvsrc_status {
288 	u32 y_hvsrc_crc;
289 	u32 u_hvsrc_crc;
290 	u32 v_hvsrc_crc;
291 };
292 
293 struct sti_hqvdp_iqi_status {
294 	u32 pxf_it_status;
295 	u32 y_iqi_crc;
296 	u32 u_iqi_crc;
297 	u32 v_iqi_crc;
298 };
299 
300 /* Main commands. We use 2 commands one being processed by the firmware, one
301  * ready to be fetched upon next Vsync*/
302 #define NB_VDP_CMD	2
303 
304 struct sti_hqvdp_cmd {
305 	struct sti_hqvdp_top top;
306 	struct sti_hqvdp_vc1re vc1re;
307 	struct sti_hqvdp_fmd fmd;
308 	struct sti_hqvdp_csdi csdi;
309 	struct sti_hqvdp_hvsrc hvsrc;
310 	struct sti_hqvdp_iqi iqi;
311 	struct sti_hqvdp_top_status top_status;
312 	struct sti_hqvdp_fmd_status fmd_status;
313 	struct sti_hqvdp_csdi_status csdi_status;
314 	struct sti_hqvdp_hvsrc_status hvsrc_status;
315 	struct sti_hqvdp_iqi_status iqi_status;
316 };
317 
318 /*
319  * STI HQVDP structure
320  *
321  * @dev:               driver device
322  * @drm_dev:           the drm device
323  * @regs:              registers
324  * @plane:             plane structure for hqvdp it self
325  * @clk:               IP clock
326  * @clk_pix_main:      pix main clock
327  * @reset:             reset control
328  * @vtg_nb:            notifier to handle VTG Vsync
329  * @btm_field_pending: is there any bottom field (interlaced frame) to display
330  * @hqvdp_cmd:         buffer of commands
331  * @hqvdp_cmd_paddr:   physical address of hqvdp_cmd
332  * @vtg:               vtg for main data path
333  * @xp70_initialized:  true if xp70 is already initialized
334  */
335 struct sti_hqvdp {
336 	struct device *dev;
337 	struct drm_device *drm_dev;
338 	void __iomem *regs;
339 	struct sti_plane plane;
340 	struct clk *clk;
341 	struct clk *clk_pix_main;
342 	struct reset_control *reset;
343 	struct notifier_block vtg_nb;
344 	bool btm_field_pending;
345 	void *hqvdp_cmd;
346 	u32 hqvdp_cmd_paddr;
347 	struct sti_vtg *vtg;
348 	bool xp70_initialized;
349 };
350 
351 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane)
352 
353 static const uint32_t hqvdp_supported_formats[] = {
354 	DRM_FORMAT_NV12,
355 };
356 
357 /**
358  * sti_hqvdp_get_free_cmd
359  * @hqvdp: hqvdp structure
360  *
361  * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW.
362  *
363  * RETURNS:
364  * the offset of the command to be used.
365  * -1 in error cases
366  */
367 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp)
368 {
369 	u32 curr_cmd, next_cmd;
370 	u32 cmd = hqvdp->hqvdp_cmd_paddr;
371 	int i;
372 
373 	curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
374 	next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
375 
376 	for (i = 0; i < NB_VDP_CMD; i++) {
377 		if ((cmd != curr_cmd) && (cmd != next_cmd))
378 			return i * sizeof(struct sti_hqvdp_cmd);
379 		cmd += sizeof(struct sti_hqvdp_cmd);
380 	}
381 
382 	return -1;
383 }
384 
385 /**
386  * sti_hqvdp_get_curr_cmd
387  * @hqvdp: hqvdp structure
388  *
389  * Look for the hqvdp_cmd that is being used by the FW.
390  *
391  * RETURNS:
392  *  the offset of the command to be used.
393  * -1 in error cases
394  */
395 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp)
396 {
397 	u32 curr_cmd;
398 	u32 cmd = hqvdp->hqvdp_cmd_paddr;
399 	unsigned int i;
400 
401 	curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
402 
403 	for (i = 0; i < NB_VDP_CMD; i++) {
404 		if (cmd == curr_cmd)
405 			return i * sizeof(struct sti_hqvdp_cmd);
406 
407 		cmd += sizeof(struct sti_hqvdp_cmd);
408 	}
409 
410 	return -1;
411 }
412 
413 /**
414  * sti_hqvdp_get_next_cmd
415  * @hqvdp: hqvdp structure
416  *
417  * Look for the next hqvdp_cmd that will be used by the FW.
418  *
419  * RETURNS:
420  *  the offset of the next command that will be used.
421  * -1 in error cases
422  */
423 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp *hqvdp)
424 {
425 	int next_cmd;
426 	dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr;
427 	unsigned int i;
428 
429 	next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
430 
431 	for (i = 0; i < NB_VDP_CMD; i++) {
432 		if (cmd == next_cmd)
433 			return i * sizeof(struct sti_hqvdp_cmd);
434 
435 		cmd += sizeof(struct sti_hqvdp_cmd);
436 	}
437 
438 	return -1;
439 }
440 
441 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
442 				   readl(hqvdp->regs + reg))
443 
444 static const char *hqvdp_dbg_get_lut(u32 *coef)
445 {
446 	if (!memcmp(coef, coef_lut_a_legacy, 16))
447 		return "LUT A";
448 	if (!memcmp(coef, coef_lut_b, 16))
449 		return "LUT B";
450 	if (!memcmp(coef, coef_lut_c_y_legacy, 16))
451 		return "LUT C Y";
452 	if (!memcmp(coef, coef_lut_c_c_legacy, 16))
453 		return "LUT C C";
454 	if (!memcmp(coef, coef_lut_d_y_legacy, 16))
455 		return "LUT D Y";
456 	if (!memcmp(coef, coef_lut_d_c_legacy, 16))
457 		return "LUT D C";
458 	if (!memcmp(coef, coef_lut_e_y_legacy, 16))
459 		return "LUT E Y";
460 	if (!memcmp(coef, coef_lut_e_c_legacy, 16))
461 		return "LUT E C";
462 	if (!memcmp(coef, coef_lut_f_y_legacy, 16))
463 		return "LUT F Y";
464 	if (!memcmp(coef, coef_lut_f_c_legacy, 16))
465 		return "LUT F C";
466 	return "<UNKNOWN>";
467 }
468 
469 static void hqvdp_dbg_dump_cmd(struct seq_file *s, struct sti_hqvdp_cmd *c)
470 {
471 	int src_w, src_h, dst_w, dst_h;
472 
473 	seq_puts(s, "\n\tTOP:");
474 	seq_printf(s, "\n\t %-20s 0x%08X", "Config", c->top.config);
475 	switch (c->top.config) {
476 	case TOP_CONFIG_PROGRESSIVE:
477 		seq_puts(s, "\tProgressive");
478 		break;
479 	case TOP_CONFIG_INTER_TOP:
480 		seq_puts(s, "\tInterlaced, top field");
481 		break;
482 	case TOP_CONFIG_INTER_BTM:
483 		seq_puts(s, "\tInterlaced, bottom field");
484 		break;
485 	default:
486 		seq_puts(s, "\t<UNKNOWN>");
487 		break;
488 	}
489 
490 	seq_printf(s, "\n\t %-20s 0x%08X", "MemFormat", c->top.mem_format);
491 	seq_printf(s, "\n\t %-20s 0x%08X", "CurrentY", c->top.current_luma);
492 	seq_printf(s, "\n\t %-20s 0x%08X", "CurrentC", c->top.current_chroma);
493 	seq_printf(s, "\n\t %-20s 0x%08X", "YSrcPitch", c->top.luma_src_pitch);
494 	seq_printf(s, "\n\t %-20s 0x%08X", "CSrcPitch",
495 		   c->top.chroma_src_pitch);
496 	seq_printf(s, "\n\t %-20s 0x%08X", "InputFrameSize",
497 		   c->top.input_frame_size);
498 	seq_printf(s, "\t%dx%d",
499 		   c->top.input_frame_size & 0x0000FFFF,
500 		   c->top.input_frame_size >> 16);
501 	seq_printf(s, "\n\t %-20s 0x%08X", "InputViewportSize",
502 		   c->top.input_viewport_size);
503 	src_w = c->top.input_viewport_size & 0x0000FFFF;
504 	src_h = c->top.input_viewport_size >> 16;
505 	seq_printf(s, "\t%dx%d", src_w, src_h);
506 
507 	seq_puts(s, "\n\tHVSRC:");
508 	seq_printf(s, "\n\t %-20s 0x%08X", "OutputPictureSize",
509 		   c->hvsrc.output_picture_size);
510 	dst_w = c->hvsrc.output_picture_size & 0x0000FFFF;
511 	dst_h = c->hvsrc.output_picture_size >> 16;
512 	seq_printf(s, "\t%dx%d", dst_w, dst_h);
513 	seq_printf(s, "\n\t %-20s 0x%08X", "ParamCtrl", c->hvsrc.param_ctrl);
514 
515 	seq_printf(s, "\n\t %-20s %s", "yh_coef",
516 		   hqvdp_dbg_get_lut(c->hvsrc.yh_coef));
517 	seq_printf(s, "\n\t %-20s %s", "ch_coef",
518 		   hqvdp_dbg_get_lut(c->hvsrc.ch_coef));
519 	seq_printf(s, "\n\t %-20s %s", "yv_coef",
520 		   hqvdp_dbg_get_lut(c->hvsrc.yv_coef));
521 	seq_printf(s, "\n\t %-20s %s", "cv_coef",
522 		   hqvdp_dbg_get_lut(c->hvsrc.cv_coef));
523 
524 	seq_printf(s, "\n\t %-20s", "ScaleH");
525 	if (dst_w > src_w)
526 		seq_printf(s, " %d/1", dst_w / src_w);
527 	else
528 		seq_printf(s, " 1/%d", src_w / dst_w);
529 
530 	seq_printf(s, "\n\t %-20s", "tScaleV");
531 	if (dst_h > src_h)
532 		seq_printf(s, " %d/1", dst_h / src_h);
533 	else
534 		seq_printf(s, " 1/%d", src_h / dst_h);
535 
536 	seq_puts(s, "\n\tCSDI:");
537 	seq_printf(s, "\n\t %-20s 0x%08X\t", "Config", c->csdi.config);
538 	switch (c->csdi.config) {
539 	case CSDI_CONFIG_PROG:
540 		seq_puts(s, "Bypass");
541 		break;
542 	case CSDI_CONFIG_INTER_DIR:
543 		seq_puts(s, "Deinterlace, directional");
544 		break;
545 	default:
546 		seq_puts(s, "<UNKNOWN>");
547 		break;
548 	}
549 
550 	seq_printf(s, "\n\t %-20s 0x%08X", "Config2", c->csdi.config2);
551 	seq_printf(s, "\n\t %-20s 0x%08X", "DcdiConfig", c->csdi.dcdi_config);
552 }
553 
554 static int hqvdp_dbg_show(struct seq_file *s, void *data)
555 {
556 	struct drm_info_node *node = s->private;
557 	struct sti_hqvdp *hqvdp = (struct sti_hqvdp *)node->info_ent->data;
558 	struct drm_device *dev = node->minor->dev;
559 	int cmd, cmd_offset, infoxp70;
560 	void *virt;
561 	int ret;
562 
563 	ret = mutex_lock_interruptible(&dev->struct_mutex);
564 	if (ret)
565 		return ret;
566 
567 	seq_printf(s, "%s: (vaddr = 0x%p)",
568 		   sti_plane_to_str(&hqvdp->plane), hqvdp->regs);
569 
570 	DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70);
571 	DBGFS_DUMP(HQVDP_MBX_INFO_HOST);
572 	DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST);
573 	DBGFS_DUMP(HQVDP_MBX_INFO_XP70);
574 	infoxp70 = readl(hqvdp->regs + HQVDP_MBX_INFO_XP70);
575 	seq_puts(s, "\tFirmware state: ");
576 	if (infoxp70 & INFO_XP70_FW_READY)
577 		seq_puts(s, "idle and ready");
578 	else if (infoxp70 & INFO_XP70_FW_PROCESSING)
579 		seq_puts(s, "processing a picture");
580 	else if (infoxp70 & INFO_XP70_FW_INITQUEUES)
581 		seq_puts(s, "programming queues");
582 	else
583 		seq_puts(s, "NOT READY");
584 
585 	DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL);
586 	DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1);
587 	if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
588 					& STARTUP_CTRL1_RST_DONE)
589 		seq_puts(s, "\tReset is done");
590 	else
591 		seq_puts(s, "\tReset is NOT done");
592 	DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2);
593 	if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2)
594 					& STARTUP_CTRL2_FETCH_EN)
595 		seq_puts(s, "\tFetch is enabled");
596 	else
597 		seq_puts(s, "\tFetch is NOT enabled");
598 	DBGFS_DUMP(HQVDP_MBX_GP_STATUS);
599 	DBGFS_DUMP(HQVDP_MBX_NEXT_CMD);
600 	DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD);
601 	DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC);
602 	if (!(readl(hqvdp->regs + HQVDP_MBX_SOFT_VSYNC) & 3))
603 		seq_puts(s, "\tHW Vsync");
604 	else
605 		seq_puts(s, "\tSW Vsync ?!?!");
606 
607 	/* Last command */
608 	cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
609 	cmd_offset = sti_hqvdp_get_curr_cmd(hqvdp);
610 	if (cmd_offset == -1) {
611 		seq_puts(s, "\n\n  Last command: unknown");
612 	} else {
613 		virt = hqvdp->hqvdp_cmd + cmd_offset;
614 		seq_printf(s, "\n\n  Last command: address @ 0x%x (0x%p)",
615 			   cmd, virt);
616 		hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt);
617 	}
618 
619 	/* Next command */
620 	cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
621 	cmd_offset = sti_hqvdp_get_next_cmd(hqvdp);
622 	if (cmd_offset == -1) {
623 		seq_puts(s, "\n\n  Next command: unknown");
624 	} else {
625 		virt = hqvdp->hqvdp_cmd + cmd_offset;
626 		seq_printf(s, "\n\n  Next command address: @ 0x%x (0x%p)",
627 			   cmd, virt);
628 		hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt);
629 	}
630 
631 	seq_puts(s, "\n");
632 
633 	mutex_unlock(&dev->struct_mutex);
634 	return 0;
635 }
636 
637 static struct drm_info_list hqvdp_debugfs_files[] = {
638 	{ "hqvdp", hqvdp_dbg_show, 0, NULL },
639 };
640 
641 static int hqvdp_debugfs_init(struct sti_hqvdp *hqvdp, struct drm_minor *minor)
642 {
643 	unsigned int i;
644 
645 	for (i = 0; i < ARRAY_SIZE(hqvdp_debugfs_files); i++)
646 		hqvdp_debugfs_files[i].data = hqvdp;
647 
648 	return drm_debugfs_create_files(hqvdp_debugfs_files,
649 					ARRAY_SIZE(hqvdp_debugfs_files),
650 					minor->debugfs_root, minor);
651 }
652 
653 /**
654  * sti_hqvdp_update_hvsrc
655  * @orient: horizontal or vertical
656  * @scale:  scaling/zoom factor
657  * @hvsrc:  the structure containing the LUT coef
658  *
659  * Update the Y and C Lut coef, as well as the shift param
660  *
661  * RETURNS:
662  * None.
663  */
664 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale,
665 		struct sti_hqvdp_hvsrc *hvsrc)
666 {
667 	const int *coef_c, *coef_y;
668 	int shift_c, shift_y;
669 
670 	/* Get the appropriate coef tables */
671 	if (scale < SCALE_MAX_FOR_LEG_LUT_F) {
672 		coef_y = coef_lut_f_y_legacy;
673 		coef_c = coef_lut_f_c_legacy;
674 		shift_y = SHIFT_LUT_F_Y_LEGACY;
675 		shift_c = SHIFT_LUT_F_C_LEGACY;
676 	} else if (scale < SCALE_MAX_FOR_LEG_LUT_E) {
677 		coef_y = coef_lut_e_y_legacy;
678 		coef_c = coef_lut_e_c_legacy;
679 		shift_y = SHIFT_LUT_E_Y_LEGACY;
680 		shift_c = SHIFT_LUT_E_C_LEGACY;
681 	} else if (scale < SCALE_MAX_FOR_LEG_LUT_D) {
682 		coef_y = coef_lut_d_y_legacy;
683 		coef_c = coef_lut_d_c_legacy;
684 		shift_y = SHIFT_LUT_D_Y_LEGACY;
685 		shift_c = SHIFT_LUT_D_C_LEGACY;
686 	} else if (scale < SCALE_MAX_FOR_LEG_LUT_C) {
687 		coef_y = coef_lut_c_y_legacy;
688 		coef_c = coef_lut_c_c_legacy;
689 		shift_y = SHIFT_LUT_C_Y_LEGACY;
690 		shift_c = SHIFT_LUT_C_C_LEGACY;
691 	} else if (scale == SCALE_MAX_FOR_LEG_LUT_C) {
692 		coef_y = coef_c = coef_lut_b;
693 		shift_y = shift_c = SHIFT_LUT_B;
694 	} else {
695 		coef_y = coef_c = coef_lut_a_legacy;
696 		shift_y = shift_c = SHIFT_LUT_A_LEGACY;
697 	}
698 
699 	if (orient == HVSRC_HORI) {
700 		hvsrc->hori_shift = (shift_c << 16) | shift_y;
701 		memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef));
702 		memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef));
703 	} else {
704 		hvsrc->vert_shift = (shift_c << 16) | shift_y;
705 		memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef));
706 		memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef));
707 	}
708 }
709 
710 /**
711  * sti_hqvdp_check_hw_scaling
712  * @hqvdp: hqvdp pointer
713  * @mode: display mode with timing constraints
714  * @src_w: source width
715  * @src_h: source height
716  * @dst_w: destination width
717  * @dst_h: destination height
718  *
719  * Check if the HW is able to perform the scaling request
720  * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where:
721  *   Zy = OutputHeight / InputHeight
722  *   LFW = (Tx * IPClock) / (MaxNbCycles * Cp)
723  *     Tx : Total video mode horizontal resolution
724  *     IPClock : HQVDP IP clock (Mhz)
725  *     MaxNbCycles: max(InputWidth, OutputWidth)
726  *     Cp: Video mode pixel clock (Mhz)
727  *
728  * RETURNS:
729  * True if the HW can scale.
730  */
731 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp *hqvdp,
732 				       struct drm_display_mode *mode,
733 				       int src_w, int src_h,
734 				       int dst_w, int dst_h)
735 {
736 	unsigned long lfw;
737 	unsigned int inv_zy;
738 
739 	lfw = mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000);
740 	lfw /= max(src_w, dst_w) * mode->clock / 1000;
741 
742 	inv_zy = DIV_ROUND_UP(src_h, dst_h);
743 
744 	return (inv_zy <= lfw) ? true : false;
745 }
746 
747 /**
748  * sti_hqvdp_disable
749  * @hqvdp: hqvdp pointer
750  *
751  * Disables the HQVDP plane
752  */
753 static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp)
754 {
755 	int i;
756 
757 	DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp->plane));
758 
759 	/* Unregister VTG Vsync callback */
760 	if (sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb))
761 		DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
762 
763 	/* Set next cmd to NULL */
764 	writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
765 
766 	for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
767 		if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
768 				& INFO_XP70_FW_READY)
769 			break;
770 		msleep(POLL_DELAY_MS);
771 	}
772 
773 	/* VTG can stop now */
774 	clk_disable_unprepare(hqvdp->clk_pix_main);
775 
776 	if (i == POLL_MAX_ATTEMPT)
777 		DRM_ERROR("XP70 could not revert to idle\n");
778 
779 	hqvdp->plane.status = STI_PLANE_DISABLED;
780 }
781 
782 /**
783  * sti_vdp_vtg_cb
784  * @nb: notifier block
785  * @evt: event message
786  * @data: private data
787  *
788  * Handle VTG Vsync event, display pending bottom field
789  *
790  * RETURNS:
791  * 0 on success.
792  */
793 int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data)
794 {
795 	struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb);
796 	int btm_cmd_offset, top_cmd_offest;
797 	struct sti_hqvdp_cmd *btm_cmd, *top_cmd;
798 
799 	if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) {
800 		DRM_DEBUG_DRIVER("Unknown event\n");
801 		return 0;
802 	}
803 
804 	if (hqvdp->plane.status == STI_PLANE_FLUSHING) {
805 		/* disable need to be synchronize on vsync event */
806 		DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
807 				 sti_plane_to_str(&hqvdp->plane));
808 
809 		sti_hqvdp_disable(hqvdp);
810 	}
811 
812 	if (hqvdp->btm_field_pending) {
813 		/* Create the btm field command from the current one */
814 		btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
815 		top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp);
816 		if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) {
817 			DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n");
818 			return -EBUSY;
819 		}
820 
821 		btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset;
822 		top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest;
823 
824 		memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd));
825 
826 		btm_cmd->top.config = TOP_CONFIG_INTER_BTM;
827 		btm_cmd->top.current_luma +=
828 				btm_cmd->top.luma_src_pitch / 2;
829 		btm_cmd->top.current_chroma +=
830 				btm_cmd->top.chroma_src_pitch / 2;
831 
832 		/* Post the command to mailbox */
833 		writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset,
834 				hqvdp->regs + HQVDP_MBX_NEXT_CMD);
835 
836 		hqvdp->btm_field_pending = false;
837 
838 		dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
839 				__func__, hqvdp->hqvdp_cmd_paddr);
840 
841 		sti_plane_update_fps(&hqvdp->plane, false, true);
842 	}
843 
844 	return 0;
845 }
846 
847 static void sti_hqvdp_init(struct sti_hqvdp *hqvdp)
848 {
849 	int size;
850 	dma_addr_t dma_addr;
851 
852 	hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb;
853 
854 	/* Allocate memory for the VDP commands */
855 	size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd);
856 	hqvdp->hqvdp_cmd = dma_alloc_wc(hqvdp->dev, size,
857 					&dma_addr,
858 					GFP_KERNEL | GFP_DMA);
859 	if (!hqvdp->hqvdp_cmd) {
860 		DRM_ERROR("Failed to allocate memory for VDP cmd\n");
861 		return;
862 	}
863 
864 	hqvdp->hqvdp_cmd_paddr = (u32)dma_addr;
865 	memset(hqvdp->hqvdp_cmd, 0, size);
866 }
867 
868 static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp)
869 {
870 	/* Configure Plugs (same for RD & WR) */
871 	writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE);
872 	writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC);
873 	writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC);
874 	writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK);
875 	writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG);
876 	writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE);
877 	writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL);
878 
879 	writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE);
880 	writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC);
881 	writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC);
882 	writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK);
883 	writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG);
884 	writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE);
885 	writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL);
886 }
887 
888 /**
889  * sti_hqvdp_start_xp70
890  * @hqvdp: hqvdp pointer
891  *
892  * Run the xP70 initialization sequence
893  */
894 static void sti_hqvdp_start_xp70(struct sti_hqvdp *hqvdp)
895 {
896 	const struct firmware *firmware;
897 	u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem;
898 	u8 *data;
899 	int i;
900 	struct fw_header {
901 		int rd_size;
902 		int wr_size;
903 		int pmem_size;
904 		int dmem_size;
905 	} *header;
906 
907 	DRM_DEBUG_DRIVER("\n");
908 
909 	if (hqvdp->xp70_initialized) {
910 		DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n");
911 		return;
912 	}
913 
914 	/* Request firmware */
915 	if (request_firmware(&firmware, HQVDP_FMW_NAME, hqvdp->dev)) {
916 		DRM_ERROR("Can't get HQVDP firmware\n");
917 		return;
918 	}
919 
920 	/* Check firmware parts */
921 	if (!firmware) {
922 		DRM_ERROR("Firmware not available\n");
923 		return;
924 	}
925 
926 	header = (struct fw_header *)firmware->data;
927 	if (firmware->size < sizeof(*header)) {
928 		DRM_ERROR("Invalid firmware size (%d)\n", firmware->size);
929 		goto out;
930 	}
931 	if ((sizeof(*header) + header->rd_size + header->wr_size +
932 		header->pmem_size + header->dmem_size) != firmware->size) {
933 		DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n",
934 			  sizeof(*header), header->rd_size, header->wr_size,
935 			  header->pmem_size, header->dmem_size,
936 			  firmware->size);
937 		goto out;
938 	}
939 
940 	data = (u8 *)firmware->data;
941 	data += sizeof(*header);
942 	fw_rd_plug = (void *)data;
943 	data += header->rd_size;
944 	fw_wr_plug = (void *)data;
945 	data += header->wr_size;
946 	fw_pmem = (void *)data;
947 	data += header->pmem_size;
948 	fw_dmem = (void *)data;
949 
950 	/* Enable clock */
951 	if (clk_prepare_enable(hqvdp->clk))
952 		DRM_ERROR("Failed to prepare/enable HQVDP clk\n");
953 
954 	/* Reset */
955 	writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL);
956 
957 	for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
958 		if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
959 				& STARTUP_CTRL1_RST_DONE)
960 			break;
961 		msleep(POLL_DELAY_MS);
962 	}
963 	if (i == POLL_MAX_ATTEMPT) {
964 		DRM_ERROR("Could not reset\n");
965 		goto out;
966 	}
967 
968 	/* Init Read & Write plugs */
969 	for (i = 0; i < header->rd_size / 4; i++)
970 		writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4);
971 	for (i = 0; i < header->wr_size / 4; i++)
972 		writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4);
973 
974 	sti_hqvdp_init_plugs(hqvdp);
975 
976 	/* Authorize Idle Mode */
977 	writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1);
978 
979 	/* Prevent VTG interruption during the boot */
980 	writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
981 	writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
982 
983 	/* Download PMEM & DMEM */
984 	for (i = 0; i < header->pmem_size / 4; i++)
985 		writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4);
986 	for (i = 0; i < header->dmem_size / 4; i++)
987 		writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4);
988 
989 	/* Enable fetch */
990 	writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2);
991 
992 	/* Wait end of boot */
993 	for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
994 		if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
995 				& INFO_XP70_FW_READY)
996 			break;
997 		msleep(POLL_DELAY_MS);
998 	}
999 	if (i == POLL_MAX_ATTEMPT) {
1000 		DRM_ERROR("Could not boot\n");
1001 		goto out;
1002 	}
1003 
1004 	/* Launch Vsync */
1005 	writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
1006 
1007 	DRM_INFO("HQVDP XP70 initialized\n");
1008 
1009 	hqvdp->xp70_initialized = true;
1010 
1011 out:
1012 	release_firmware(firmware);
1013 }
1014 
1015 static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane,
1016 				  struct drm_plane_state *state)
1017 {
1018 	struct sti_plane *plane = to_sti_plane(drm_plane);
1019 	struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1020 	struct drm_crtc *crtc = state->crtc;
1021 	struct drm_framebuffer *fb = state->fb;
1022 	bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false;
1023 	struct drm_crtc_state *crtc_state;
1024 	struct drm_display_mode *mode;
1025 	int dst_x, dst_y, dst_w, dst_h;
1026 	int src_x, src_y, src_w, src_h;
1027 
1028 	/* no need for further checks if the plane is being disabled */
1029 	if (!crtc || !fb)
1030 		return 0;
1031 
1032 	crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1033 	mode = &crtc_state->mode;
1034 	dst_x = state->crtc_x;
1035 	dst_y = state->crtc_y;
1036 	dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
1037 	dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
1038 	/* src_x are in 16.16 format */
1039 	src_x = state->src_x >> 16;
1040 	src_y = state->src_y >> 16;
1041 	src_w = state->src_w >> 16;
1042 	src_h = state->src_h >> 16;
1043 
1044 	if (!sti_hqvdp_check_hw_scaling(hqvdp, mode,
1045 					src_w, src_h,
1046 					dst_w, dst_h)) {
1047 		DRM_ERROR("Scaling beyond HW capabilities\n");
1048 		return -EINVAL;
1049 	}
1050 
1051 	if (!drm_fb_cma_get_gem_obj(fb, 0)) {
1052 		DRM_ERROR("Can't get CMA GEM object for fb\n");
1053 		return -EINVAL;
1054 	}
1055 
1056 	/*
1057 	 * Input / output size
1058 	 * Align to upper even value
1059 	 */
1060 	dst_w = ALIGN(dst_w, 2);
1061 	dst_h = ALIGN(dst_h, 2);
1062 
1063 	if ((src_w > MAX_WIDTH) || (src_w < MIN_WIDTH) ||
1064 	    (src_h > MAX_HEIGHT) || (src_h < MIN_HEIGHT) ||
1065 	    (dst_w > MAX_WIDTH) || (dst_w < MIN_WIDTH) ||
1066 	    (dst_h > MAX_HEIGHT) || (dst_h < MIN_HEIGHT)) {
1067 		DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n",
1068 			  src_w, src_h,
1069 			  dst_w, dst_h);
1070 		return -EINVAL;
1071 	}
1072 
1073 	if (first_prepare) {
1074 		/* Start HQVDP XP70 coprocessor */
1075 		sti_hqvdp_start_xp70(hqvdp);
1076 
1077 		/* Prevent VTG shutdown */
1078 		if (clk_prepare_enable(hqvdp->clk_pix_main)) {
1079 			DRM_ERROR("Failed to prepare/enable pix main clk\n");
1080 			return -EINVAL;
1081 		}
1082 
1083 		/* Register VTG Vsync callback to handle bottom fields */
1084 		if (sti_vtg_register_client(hqvdp->vtg,
1085 					    &hqvdp->vtg_nb,
1086 					    crtc)) {
1087 			DRM_ERROR("Cannot register VTG notifier\n");
1088 			return -EINVAL;
1089 		}
1090 	}
1091 
1092 	DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
1093 		      crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)),
1094 		      drm_plane->base.id, sti_plane_to_str(plane));
1095 	DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
1096 		      sti_plane_to_str(plane),
1097 		      dst_w, dst_h, dst_x, dst_y,
1098 		      src_w, src_h, src_x, src_y);
1099 
1100 	return 0;
1101 }
1102 
1103 static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane,
1104 				    struct drm_plane_state *oldstate)
1105 {
1106 	struct drm_plane_state *state = drm_plane->state;
1107 	struct sti_plane *plane = to_sti_plane(drm_plane);
1108 	struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1109 	struct drm_crtc *crtc = state->crtc;
1110 	struct drm_framebuffer *fb = state->fb;
1111 	struct drm_display_mode *mode;
1112 	int dst_x, dst_y, dst_w, dst_h;
1113 	int src_x, src_y, src_w, src_h;
1114 	struct drm_gem_cma_object *cma_obj;
1115 	struct sti_hqvdp_cmd *cmd;
1116 	int scale_h, scale_v;
1117 	int cmd_offset;
1118 
1119 	if (!crtc || !fb)
1120 		return;
1121 
1122 	mode = &crtc->mode;
1123 	dst_x = state->crtc_x;
1124 	dst_y = state->crtc_y;
1125 	dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
1126 	dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
1127 	/* src_x are in 16.16 format */
1128 	src_x = state->src_x >> 16;
1129 	src_y = state->src_y >> 16;
1130 	src_w = state->src_w >> 16;
1131 	src_h = state->src_h >> 16;
1132 
1133 	cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
1134 	if (cmd_offset == -1) {
1135 		DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n");
1136 		return;
1137 	}
1138 	cmd = hqvdp->hqvdp_cmd + cmd_offset;
1139 
1140 	/* Static parameters, defaulting to progressive mode */
1141 	cmd->top.config = TOP_CONFIG_PROGRESSIVE;
1142 	cmd->top.mem_format = TOP_MEM_FORMAT_DFLT;
1143 	cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT;
1144 	cmd->csdi.config = CSDI_CONFIG_PROG;
1145 
1146 	/* VC1RE, FMD bypassed : keep everything set to 0
1147 	 * IQI/P2I bypassed */
1148 	cmd->iqi.config = IQI_CONFIG_DFLT;
1149 	cmd->iqi.con_bri = IQI_CON_BRI_DFLT;
1150 	cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT;
1151 	cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT;
1152 
1153 	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
1154 
1155 	DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
1156 			 (char *)&fb->pixel_format,
1157 			 (unsigned long)cma_obj->paddr);
1158 
1159 	/* Buffer planes address */
1160 	cmd->top.current_luma = (u32)cma_obj->paddr + fb->offsets[0];
1161 	cmd->top.current_chroma = (u32)cma_obj->paddr + fb->offsets[1];
1162 
1163 	/* Pitches */
1164 	cmd->top.luma_processed_pitch = fb->pitches[0];
1165 	cmd->top.luma_src_pitch = fb->pitches[0];
1166 	cmd->top.chroma_processed_pitch = fb->pitches[1];
1167 	cmd->top.chroma_src_pitch = fb->pitches[1];
1168 
1169 	/* Input / output size
1170 	 * Align to upper even value */
1171 	dst_w = ALIGN(dst_w, 2);
1172 	dst_h = ALIGN(dst_h, 2);
1173 
1174 	cmd->top.input_viewport_size = src_h << 16 | src_w;
1175 	cmd->top.input_frame_size = src_h << 16 | src_w;
1176 	cmd->hvsrc.output_picture_size = dst_h << 16 | dst_w;
1177 	cmd->top.input_viewport_ori = src_y << 16 | src_x;
1178 
1179 	/* Handle interlaced */
1180 	if (fb->flags & DRM_MODE_FB_INTERLACED) {
1181 		/* Top field to display */
1182 		cmd->top.config = TOP_CONFIG_INTER_TOP;
1183 
1184 		/* Update pitches and vert size */
1185 		cmd->top.input_frame_size = (src_h / 2) << 16 | src_w;
1186 		cmd->top.luma_processed_pitch *= 2;
1187 		cmd->top.luma_src_pitch *= 2;
1188 		cmd->top.chroma_processed_pitch *= 2;
1189 		cmd->top.chroma_src_pitch *= 2;
1190 
1191 		/* Enable directional deinterlacing processing */
1192 		cmd->csdi.config = CSDI_CONFIG_INTER_DIR;
1193 		cmd->csdi.config2 = CSDI_CONFIG2_DFLT;
1194 		cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT;
1195 	}
1196 
1197 	/* Update hvsrc lut coef */
1198 	scale_h = SCALE_FACTOR * dst_w / src_w;
1199 	sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc);
1200 
1201 	scale_v = SCALE_FACTOR * dst_h / src_h;
1202 	sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc);
1203 
1204 	writel(hqvdp->hqvdp_cmd_paddr + cmd_offset,
1205 	       hqvdp->regs + HQVDP_MBX_NEXT_CMD);
1206 
1207 	/* Interlaced : get ready to display the bottom field at next Vsync */
1208 	if (fb->flags & DRM_MODE_FB_INTERLACED)
1209 		hqvdp->btm_field_pending = true;
1210 
1211 	dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
1212 		__func__, hqvdp->hqvdp_cmd_paddr + cmd_offset);
1213 
1214 	sti_plane_update_fps(plane, true, true);
1215 
1216 	plane->status = STI_PLANE_UPDATED;
1217 }
1218 
1219 static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane,
1220 				     struct drm_plane_state *oldstate)
1221 {
1222 	struct sti_plane *plane = to_sti_plane(drm_plane);
1223 
1224 	if (!drm_plane->crtc) {
1225 		DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
1226 				 drm_plane->base.id);
1227 		return;
1228 	}
1229 
1230 	DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
1231 			 drm_plane->crtc->base.id,
1232 			 sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)),
1233 			 drm_plane->base.id, sti_plane_to_str(plane));
1234 
1235 	plane->status = STI_PLANE_DISABLING;
1236 }
1237 
1238 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs = {
1239 	.atomic_check = sti_hqvdp_atomic_check,
1240 	.atomic_update = sti_hqvdp_atomic_update,
1241 	.atomic_disable = sti_hqvdp_atomic_disable,
1242 };
1243 
1244 static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev,
1245 					  struct device *dev, int desc)
1246 {
1247 	struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
1248 	int res;
1249 
1250 	hqvdp->plane.desc = desc;
1251 	hqvdp->plane.status = STI_PLANE_DISABLED;
1252 
1253 	sti_hqvdp_init(hqvdp);
1254 
1255 	res = drm_universal_plane_init(drm_dev, &hqvdp->plane.drm_plane, 1,
1256 				       &sti_plane_helpers_funcs,
1257 				       hqvdp_supported_formats,
1258 				       ARRAY_SIZE(hqvdp_supported_formats),
1259 				       DRM_PLANE_TYPE_OVERLAY, NULL);
1260 	if (res) {
1261 		DRM_ERROR("Failed to initialize universal plane\n");
1262 		return NULL;
1263 	}
1264 
1265 	drm_plane_helper_add(&hqvdp->plane.drm_plane, &sti_hqvdp_helpers_funcs);
1266 
1267 	sti_plane_init_property(&hqvdp->plane, DRM_PLANE_TYPE_OVERLAY);
1268 
1269 	if (hqvdp_debugfs_init(hqvdp, drm_dev->primary))
1270 		DRM_ERROR("HQVDP debugfs setup failed\n");
1271 
1272 	return &hqvdp->plane.drm_plane;
1273 }
1274 
1275 int sti_hqvdp_bind(struct device *dev, struct device *master, void *data)
1276 {
1277 	struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
1278 	struct drm_device *drm_dev = data;
1279 	struct drm_plane *plane;
1280 
1281 	DRM_DEBUG_DRIVER("\n");
1282 
1283 	hqvdp->drm_dev = drm_dev;
1284 
1285 	/* Create HQVDP plane once xp70 is initialized */
1286 	plane = sti_hqvdp_create(drm_dev, hqvdp->dev, STI_HQVDP_0);
1287 	if (!plane)
1288 		DRM_ERROR("Can't create HQVDP plane\n");
1289 
1290 	return 0;
1291 }
1292 
1293 static void sti_hqvdp_unbind(struct device *dev,
1294 		struct device *master, void *data)
1295 {
1296 	/* do nothing */
1297 }
1298 
1299 static const struct component_ops sti_hqvdp_ops = {
1300 	.bind = sti_hqvdp_bind,
1301 	.unbind = sti_hqvdp_unbind,
1302 };
1303 
1304 static int sti_hqvdp_probe(struct platform_device *pdev)
1305 {
1306 	struct device *dev = &pdev->dev;
1307 	struct device_node *vtg_np;
1308 	struct sti_hqvdp *hqvdp;
1309 	struct resource *res;
1310 
1311 	DRM_DEBUG_DRIVER("\n");
1312 
1313 	hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL);
1314 	if (!hqvdp) {
1315 		DRM_ERROR("Failed to allocate HQVDP context\n");
1316 		return -ENOMEM;
1317 	}
1318 
1319 	hqvdp->dev = dev;
1320 
1321 	/* Get Memory resources */
1322 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1323 	if (res == NULL) {
1324 		DRM_ERROR("Get memory resource failed\n");
1325 		return -ENXIO;
1326 	}
1327 	hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res));
1328 	if (hqvdp->regs == NULL) {
1329 		DRM_ERROR("Register mapping failed\n");
1330 		return -ENXIO;
1331 	}
1332 
1333 	/* Get clock resources */
1334 	hqvdp->clk = devm_clk_get(dev, "hqvdp");
1335 	hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main");
1336 	if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) {
1337 		DRM_ERROR("Cannot get clocks\n");
1338 		return -ENXIO;
1339 	}
1340 
1341 	/* Get reset resources */
1342 	hqvdp->reset = devm_reset_control_get(dev, "hqvdp");
1343 	if (!IS_ERR(hqvdp->reset))
1344 		reset_control_deassert(hqvdp->reset);
1345 
1346 	vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0);
1347 	if (vtg_np)
1348 		hqvdp->vtg = of_vtg_find(vtg_np);
1349 
1350 	platform_set_drvdata(pdev, hqvdp);
1351 
1352 	return component_add(&pdev->dev, &sti_hqvdp_ops);
1353 }
1354 
1355 static int sti_hqvdp_remove(struct platform_device *pdev)
1356 {
1357 	component_del(&pdev->dev, &sti_hqvdp_ops);
1358 	return 0;
1359 }
1360 
1361 static struct of_device_id hqvdp_of_match[] = {
1362 	{ .compatible = "st,stih407-hqvdp", },
1363 	{ /* end node */ }
1364 };
1365 MODULE_DEVICE_TABLE(of, hqvdp_of_match);
1366 
1367 struct platform_driver sti_hqvdp_driver = {
1368 	.driver = {
1369 		.name = "sti-hqvdp",
1370 		.owner = THIS_MODULE,
1371 		.of_match_table = hqvdp_of_match,
1372 	},
1373 	.probe = sti_hqvdp_probe,
1374 	.remove = sti_hqvdp_remove,
1375 };
1376 
1377 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1378 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1379 MODULE_LICENSE("GPL");
1380