1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/component.h> 8 #include <linux/firmware.h> 9 #include <linux/reset.h> 10 #include <linux/seq_file.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_fb_cma_helper.h> 14 #include <drm/drm_gem_cma_helper.h> 15 16 #include "sti_compositor.h" 17 #include "sti_hqvdp_lut.h" 18 #include "sti_plane.h" 19 #include "sti_vtg.h" 20 #include "sti_drv.h" 21 22 /* Firmware name */ 23 #define HQVDP_FMW_NAME "hqvdp-stih407.bin" 24 25 /* Regs address */ 26 #define HQVDP_DMEM 0x00000000 /* 0x00000000 */ 27 #define HQVDP_PMEM 0x00040000 /* 0x00040000 */ 28 #define HQVDP_RD_PLUG 0x000E0000 /* 0x000E0000 */ 29 #define HQVDP_RD_PLUG_CONTROL (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */ 30 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */ 31 #define HQVDP_RD_PLUG_MIN_OPC (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */ 32 #define HQVDP_RD_PLUG_MAX_OPC (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */ 33 #define HQVDP_RD_PLUG_MAX_CHK (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */ 34 #define HQVDP_RD_PLUG_MAX_MSG (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */ 35 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */ 36 #define HQVDP_WR_PLUG 0x000E2000 /* 0x000E2000 */ 37 #define HQVDP_WR_PLUG_CONTROL (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */ 38 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */ 39 #define HQVDP_WR_PLUG_MIN_OPC (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */ 40 #define HQVDP_WR_PLUG_MAX_OPC (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */ 41 #define HQVDP_WR_PLUG_MAX_CHK (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */ 42 #define HQVDP_WR_PLUG_MAX_MSG (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */ 43 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */ 44 #define HQVDP_MBX 0x000E4000 /* 0x000E4000 */ 45 #define HQVDP_MBX_IRQ_TO_XP70 (HQVDP_MBX + 0x0000) /* 0x000E4000 */ 46 #define HQVDP_MBX_INFO_HOST (HQVDP_MBX + 0x0004) /* 0x000E4004 */ 47 #define HQVDP_MBX_IRQ_TO_HOST (HQVDP_MBX + 0x0008) /* 0x000E4008 */ 48 #define HQVDP_MBX_INFO_XP70 (HQVDP_MBX + 0x000C) /* 0x000E400C */ 49 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010) /* 0x000E4010 */ 50 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014) /* 0x000E4014 */ 51 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018) /* 0x000E4018 */ 52 #define HQVDP_MBX_GP_STATUS (HQVDP_MBX + 0x001C) /* 0x000E401C */ 53 #define HQVDP_MBX_NEXT_CMD (HQVDP_MBX + 0x0020) /* 0x000E4020 */ 54 #define HQVDP_MBX_CURRENT_CMD (HQVDP_MBX + 0x0024) /* 0x000E4024 */ 55 #define HQVDP_MBX_SOFT_VSYNC (HQVDP_MBX + 0x0028) /* 0x000E4028 */ 56 57 /* Plugs config */ 58 #define PLUG_CONTROL_ENABLE 0x00000001 59 #define PLUG_PAGE_SIZE_256 0x00000002 60 #define PLUG_MIN_OPC_8 0x00000003 61 #define PLUG_MAX_OPC_64 0x00000006 62 #define PLUG_MAX_CHK_2X 0x00000001 63 #define PLUG_MAX_MSG_1X 0x00000000 64 #define PLUG_MIN_SPACE_1 0x00000000 65 66 /* SW reset CTRL */ 67 #define SW_RESET_CTRL_FULL BIT(0) 68 #define SW_RESET_CTRL_CORE BIT(1) 69 70 /* Startup ctrl 1 */ 71 #define STARTUP_CTRL1_RST_DONE BIT(0) 72 #define STARTUP_CTRL1_AUTH_IDLE BIT(2) 73 74 /* Startup ctrl 2 */ 75 #define STARTUP_CTRL2_FETCH_EN BIT(1) 76 77 /* Info xP70 */ 78 #define INFO_XP70_FW_READY BIT(15) 79 #define INFO_XP70_FW_PROCESSING BIT(14) 80 #define INFO_XP70_FW_INITQUEUES BIT(13) 81 82 /* SOFT_VSYNC */ 83 #define SOFT_VSYNC_HW 0x00000000 84 #define SOFT_VSYNC_SW_CMD 0x00000001 85 #define SOFT_VSYNC_SW_CTRL_IRQ 0x00000003 86 87 /* Reset & boot poll config */ 88 #define POLL_MAX_ATTEMPT 50 89 #define POLL_DELAY_MS 20 90 91 #define SCALE_FACTOR 8192 92 #define SCALE_MAX_FOR_LEG_LUT_F 4096 93 #define SCALE_MAX_FOR_LEG_LUT_E 4915 94 #define SCALE_MAX_FOR_LEG_LUT_D 6654 95 #define SCALE_MAX_FOR_LEG_LUT_C 8192 96 97 enum sti_hvsrc_orient { 98 HVSRC_HORI, 99 HVSRC_VERT 100 }; 101 102 /* Command structures */ 103 struct sti_hqvdp_top { 104 u32 config; 105 u32 mem_format; 106 u32 current_luma; 107 u32 current_enh_luma; 108 u32 current_right_luma; 109 u32 current_enh_right_luma; 110 u32 current_chroma; 111 u32 current_enh_chroma; 112 u32 current_right_chroma; 113 u32 current_enh_right_chroma; 114 u32 output_luma; 115 u32 output_chroma; 116 u32 luma_src_pitch; 117 u32 luma_enh_src_pitch; 118 u32 luma_right_src_pitch; 119 u32 luma_enh_right_src_pitch; 120 u32 chroma_src_pitch; 121 u32 chroma_enh_src_pitch; 122 u32 chroma_right_src_pitch; 123 u32 chroma_enh_right_src_pitch; 124 u32 luma_processed_pitch; 125 u32 chroma_processed_pitch; 126 u32 input_frame_size; 127 u32 input_viewport_ori; 128 u32 input_viewport_ori_right; 129 u32 input_viewport_size; 130 u32 left_view_border_width; 131 u32 right_view_border_width; 132 u32 left_view_3d_offset_width; 133 u32 right_view_3d_offset_width; 134 u32 side_stripe_color; 135 u32 crc_reset_ctrl; 136 }; 137 138 /* Configs for interlaced : no IT, no pass thru, 3 fields */ 139 #define TOP_CONFIG_INTER_BTM 0x00000000 140 #define TOP_CONFIG_INTER_TOP 0x00000002 141 142 /* Config for progressive : no IT, no pass thru, 3 fields */ 143 #define TOP_CONFIG_PROGRESSIVE 0x00000001 144 145 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */ 146 #define TOP_MEM_FORMAT_DFLT 0x00018060 147 148 /* Min/Max size */ 149 #define MAX_WIDTH 0x1FFF 150 #define MAX_HEIGHT 0x0FFF 151 #define MIN_WIDTH 0x0030 152 #define MIN_HEIGHT 0x0010 153 154 struct sti_hqvdp_vc1re { 155 u32 ctrl_prv_csdi; 156 u32 ctrl_cur_csdi; 157 u32 ctrl_nxt_csdi; 158 u32 ctrl_cur_fmd; 159 u32 ctrl_nxt_fmd; 160 }; 161 162 struct sti_hqvdp_fmd { 163 u32 config; 164 u32 viewport_ori; 165 u32 viewport_size; 166 u32 next_next_luma; 167 u32 next_next_right_luma; 168 u32 next_next_next_luma; 169 u32 next_next_next_right_luma; 170 u32 threshold_scd; 171 u32 threshold_rfd; 172 u32 threshold_move; 173 u32 threshold_cfd; 174 }; 175 176 struct sti_hqvdp_csdi { 177 u32 config; 178 u32 config2; 179 u32 dcdi_config; 180 u32 prev_luma; 181 u32 prev_enh_luma; 182 u32 prev_right_luma; 183 u32 prev_enh_right_luma; 184 u32 next_luma; 185 u32 next_enh_luma; 186 u32 next_right_luma; 187 u32 next_enh_right_luma; 188 u32 prev_chroma; 189 u32 prev_enh_chroma; 190 u32 prev_right_chroma; 191 u32 prev_enh_right_chroma; 192 u32 next_chroma; 193 u32 next_enh_chroma; 194 u32 next_right_chroma; 195 u32 next_enh_right_chroma; 196 u32 prev_motion; 197 u32 prev_right_motion; 198 u32 cur_motion; 199 u32 cur_right_motion; 200 u32 next_motion; 201 u32 next_right_motion; 202 }; 203 204 /* Config for progressive: by pass */ 205 #define CSDI_CONFIG_PROG 0x00000000 206 /* Config for directional deinterlacing without motion */ 207 #define CSDI_CONFIG_INTER_DIR 0x00000016 208 /* Additional configs for fader, blender, motion,... deinterlace algorithms */ 209 #define CSDI_CONFIG2_DFLT 0x000001B3 210 #define CSDI_DCDI_CONFIG_DFLT 0x00203803 211 212 struct sti_hqvdp_hvsrc { 213 u32 hor_panoramic_ctrl; 214 u32 output_picture_size; 215 u32 init_horizontal; 216 u32 init_vertical; 217 u32 param_ctrl; 218 u32 yh_coef[NB_COEF]; 219 u32 ch_coef[NB_COEF]; 220 u32 yv_coef[NB_COEF]; 221 u32 cv_coef[NB_COEF]; 222 u32 hori_shift; 223 u32 vert_shift; 224 }; 225 226 /* Default ParamCtrl: all controls enabled */ 227 #define HVSRC_PARAM_CTRL_DFLT 0xFFFFFFFF 228 229 struct sti_hqvdp_iqi { 230 u32 config; 231 u32 demo_wind_size; 232 u32 pk_config; 233 u32 coeff0_coeff1; 234 u32 coeff2_coeff3; 235 u32 coeff4; 236 u32 pk_lut; 237 u32 pk_gain; 238 u32 pk_coring_level; 239 u32 cti_config; 240 u32 le_config; 241 u32 le_lut[64]; 242 u32 con_bri; 243 u32 sat_gain; 244 u32 pxf_conf; 245 u32 default_color; 246 }; 247 248 /* Default Config : IQI bypassed */ 249 #define IQI_CONFIG_DFLT 0x00000001 250 /* Default Contrast & Brightness gain = 256 */ 251 #define IQI_CON_BRI_DFLT 0x00000100 252 /* Default Saturation gain = 256 */ 253 #define IQI_SAT_GAIN_DFLT 0x00000100 254 /* Default PxfConf : P2I bypassed */ 255 #define IQI_PXF_CONF_DFLT 0x00000001 256 257 struct sti_hqvdp_top_status { 258 u32 processing_time; 259 u32 input_y_crc; 260 u32 input_uv_crc; 261 }; 262 263 struct sti_hqvdp_fmd_status { 264 u32 fmd_repeat_move_status; 265 u32 fmd_scene_count_status; 266 u32 cfd_sum; 267 u32 field_sum; 268 u32 next_y_fmd_crc; 269 u32 next_next_y_fmd_crc; 270 u32 next_next_next_y_fmd_crc; 271 }; 272 273 struct sti_hqvdp_csdi_status { 274 u32 prev_y_csdi_crc; 275 u32 cur_y_csdi_crc; 276 u32 next_y_csdi_crc; 277 u32 prev_uv_csdi_crc; 278 u32 cur_uv_csdi_crc; 279 u32 next_uv_csdi_crc; 280 u32 y_csdi_crc; 281 u32 uv_csdi_crc; 282 u32 uv_cup_crc; 283 u32 mot_csdi_crc; 284 u32 mot_cur_csdi_crc; 285 u32 mot_prev_csdi_crc; 286 }; 287 288 struct sti_hqvdp_hvsrc_status { 289 u32 y_hvsrc_crc; 290 u32 u_hvsrc_crc; 291 u32 v_hvsrc_crc; 292 }; 293 294 struct sti_hqvdp_iqi_status { 295 u32 pxf_it_status; 296 u32 y_iqi_crc; 297 u32 u_iqi_crc; 298 u32 v_iqi_crc; 299 }; 300 301 /* Main commands. We use 2 commands one being processed by the firmware, one 302 * ready to be fetched upon next Vsync*/ 303 #define NB_VDP_CMD 2 304 305 struct sti_hqvdp_cmd { 306 struct sti_hqvdp_top top; 307 struct sti_hqvdp_vc1re vc1re; 308 struct sti_hqvdp_fmd fmd; 309 struct sti_hqvdp_csdi csdi; 310 struct sti_hqvdp_hvsrc hvsrc; 311 struct sti_hqvdp_iqi iqi; 312 struct sti_hqvdp_top_status top_status; 313 struct sti_hqvdp_fmd_status fmd_status; 314 struct sti_hqvdp_csdi_status csdi_status; 315 struct sti_hqvdp_hvsrc_status hvsrc_status; 316 struct sti_hqvdp_iqi_status iqi_status; 317 }; 318 319 /* 320 * STI HQVDP structure 321 * 322 * @dev: driver device 323 * @drm_dev: the drm device 324 * @regs: registers 325 * @plane: plane structure for hqvdp it self 326 * @clk: IP clock 327 * @clk_pix_main: pix main clock 328 * @reset: reset control 329 * @vtg_nb: notifier to handle VTG Vsync 330 * @btm_field_pending: is there any bottom field (interlaced frame) to display 331 * @hqvdp_cmd: buffer of commands 332 * @hqvdp_cmd_paddr: physical address of hqvdp_cmd 333 * @vtg: vtg for main data path 334 * @xp70_initialized: true if xp70 is already initialized 335 * @vtg_registered: true if registered to VTG 336 */ 337 struct sti_hqvdp { 338 struct device *dev; 339 struct drm_device *drm_dev; 340 void __iomem *regs; 341 struct sti_plane plane; 342 struct clk *clk; 343 struct clk *clk_pix_main; 344 struct reset_control *reset; 345 struct notifier_block vtg_nb; 346 bool btm_field_pending; 347 void *hqvdp_cmd; 348 u32 hqvdp_cmd_paddr; 349 struct sti_vtg *vtg; 350 bool xp70_initialized; 351 bool vtg_registered; 352 }; 353 354 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane) 355 356 static const uint32_t hqvdp_supported_formats[] = { 357 DRM_FORMAT_NV12, 358 }; 359 360 /** 361 * sti_hqvdp_get_free_cmd 362 * @hqvdp: hqvdp structure 363 * 364 * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW. 365 * 366 * RETURNS: 367 * the offset of the command to be used. 368 * -1 in error cases 369 */ 370 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp) 371 { 372 u32 curr_cmd, next_cmd; 373 u32 cmd = hqvdp->hqvdp_cmd_paddr; 374 int i; 375 376 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 377 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 378 379 for (i = 0; i < NB_VDP_CMD; i++) { 380 if ((cmd != curr_cmd) && (cmd != next_cmd)) 381 return i * sizeof(struct sti_hqvdp_cmd); 382 cmd += sizeof(struct sti_hqvdp_cmd); 383 } 384 385 return -1; 386 } 387 388 /** 389 * sti_hqvdp_get_curr_cmd 390 * @hqvdp: hqvdp structure 391 * 392 * Look for the hqvdp_cmd that is being used by the FW. 393 * 394 * RETURNS: 395 * the offset of the command to be used. 396 * -1 in error cases 397 */ 398 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp) 399 { 400 u32 curr_cmd; 401 u32 cmd = hqvdp->hqvdp_cmd_paddr; 402 unsigned int i; 403 404 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 405 406 for (i = 0; i < NB_VDP_CMD; i++) { 407 if (cmd == curr_cmd) 408 return i * sizeof(struct sti_hqvdp_cmd); 409 410 cmd += sizeof(struct sti_hqvdp_cmd); 411 } 412 413 return -1; 414 } 415 416 /** 417 * sti_hqvdp_get_next_cmd 418 * @hqvdp: hqvdp structure 419 * 420 * Look for the next hqvdp_cmd that will be used by the FW. 421 * 422 * RETURNS: 423 * the offset of the next command that will be used. 424 * -1 in error cases 425 */ 426 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp *hqvdp) 427 { 428 int next_cmd; 429 dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr; 430 unsigned int i; 431 432 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 433 434 for (i = 0; i < NB_VDP_CMD; i++) { 435 if (cmd == next_cmd) 436 return i * sizeof(struct sti_hqvdp_cmd); 437 438 cmd += sizeof(struct sti_hqvdp_cmd); 439 } 440 441 return -1; 442 } 443 444 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 445 readl(hqvdp->regs + reg)) 446 447 static const char *hqvdp_dbg_get_lut(u32 *coef) 448 { 449 if (!memcmp(coef, coef_lut_a_legacy, 16)) 450 return "LUT A"; 451 if (!memcmp(coef, coef_lut_b, 16)) 452 return "LUT B"; 453 if (!memcmp(coef, coef_lut_c_y_legacy, 16)) 454 return "LUT C Y"; 455 if (!memcmp(coef, coef_lut_c_c_legacy, 16)) 456 return "LUT C C"; 457 if (!memcmp(coef, coef_lut_d_y_legacy, 16)) 458 return "LUT D Y"; 459 if (!memcmp(coef, coef_lut_d_c_legacy, 16)) 460 return "LUT D C"; 461 if (!memcmp(coef, coef_lut_e_y_legacy, 16)) 462 return "LUT E Y"; 463 if (!memcmp(coef, coef_lut_e_c_legacy, 16)) 464 return "LUT E C"; 465 if (!memcmp(coef, coef_lut_f_y_legacy, 16)) 466 return "LUT F Y"; 467 if (!memcmp(coef, coef_lut_f_c_legacy, 16)) 468 return "LUT F C"; 469 return "<UNKNOWN>"; 470 } 471 472 static void hqvdp_dbg_dump_cmd(struct seq_file *s, struct sti_hqvdp_cmd *c) 473 { 474 int src_w, src_h, dst_w, dst_h; 475 476 seq_puts(s, "\n\tTOP:"); 477 seq_printf(s, "\n\t %-20s 0x%08X", "Config", c->top.config); 478 switch (c->top.config) { 479 case TOP_CONFIG_PROGRESSIVE: 480 seq_puts(s, "\tProgressive"); 481 break; 482 case TOP_CONFIG_INTER_TOP: 483 seq_puts(s, "\tInterlaced, top field"); 484 break; 485 case TOP_CONFIG_INTER_BTM: 486 seq_puts(s, "\tInterlaced, bottom field"); 487 break; 488 default: 489 seq_puts(s, "\t<UNKNOWN>"); 490 break; 491 } 492 493 seq_printf(s, "\n\t %-20s 0x%08X", "MemFormat", c->top.mem_format); 494 seq_printf(s, "\n\t %-20s 0x%08X", "CurrentY", c->top.current_luma); 495 seq_printf(s, "\n\t %-20s 0x%08X", "CurrentC", c->top.current_chroma); 496 seq_printf(s, "\n\t %-20s 0x%08X", "YSrcPitch", c->top.luma_src_pitch); 497 seq_printf(s, "\n\t %-20s 0x%08X", "CSrcPitch", 498 c->top.chroma_src_pitch); 499 seq_printf(s, "\n\t %-20s 0x%08X", "InputFrameSize", 500 c->top.input_frame_size); 501 seq_printf(s, "\t%dx%d", 502 c->top.input_frame_size & 0x0000FFFF, 503 c->top.input_frame_size >> 16); 504 seq_printf(s, "\n\t %-20s 0x%08X", "InputViewportSize", 505 c->top.input_viewport_size); 506 src_w = c->top.input_viewport_size & 0x0000FFFF; 507 src_h = c->top.input_viewport_size >> 16; 508 seq_printf(s, "\t%dx%d", src_w, src_h); 509 510 seq_puts(s, "\n\tHVSRC:"); 511 seq_printf(s, "\n\t %-20s 0x%08X", "OutputPictureSize", 512 c->hvsrc.output_picture_size); 513 dst_w = c->hvsrc.output_picture_size & 0x0000FFFF; 514 dst_h = c->hvsrc.output_picture_size >> 16; 515 seq_printf(s, "\t%dx%d", dst_w, dst_h); 516 seq_printf(s, "\n\t %-20s 0x%08X", "ParamCtrl", c->hvsrc.param_ctrl); 517 518 seq_printf(s, "\n\t %-20s %s", "yh_coef", 519 hqvdp_dbg_get_lut(c->hvsrc.yh_coef)); 520 seq_printf(s, "\n\t %-20s %s", "ch_coef", 521 hqvdp_dbg_get_lut(c->hvsrc.ch_coef)); 522 seq_printf(s, "\n\t %-20s %s", "yv_coef", 523 hqvdp_dbg_get_lut(c->hvsrc.yv_coef)); 524 seq_printf(s, "\n\t %-20s %s", "cv_coef", 525 hqvdp_dbg_get_lut(c->hvsrc.cv_coef)); 526 527 seq_printf(s, "\n\t %-20s", "ScaleH"); 528 if (dst_w > src_w) 529 seq_printf(s, " %d/1", dst_w / src_w); 530 else 531 seq_printf(s, " 1/%d", src_w / dst_w); 532 533 seq_printf(s, "\n\t %-20s", "tScaleV"); 534 if (dst_h > src_h) 535 seq_printf(s, " %d/1", dst_h / src_h); 536 else 537 seq_printf(s, " 1/%d", src_h / dst_h); 538 539 seq_puts(s, "\n\tCSDI:"); 540 seq_printf(s, "\n\t %-20s 0x%08X\t", "Config", c->csdi.config); 541 switch (c->csdi.config) { 542 case CSDI_CONFIG_PROG: 543 seq_puts(s, "Bypass"); 544 break; 545 case CSDI_CONFIG_INTER_DIR: 546 seq_puts(s, "Deinterlace, directional"); 547 break; 548 default: 549 seq_puts(s, "<UNKNOWN>"); 550 break; 551 } 552 553 seq_printf(s, "\n\t %-20s 0x%08X", "Config2", c->csdi.config2); 554 seq_printf(s, "\n\t %-20s 0x%08X", "DcdiConfig", c->csdi.dcdi_config); 555 } 556 557 static int hqvdp_dbg_show(struct seq_file *s, void *data) 558 { 559 struct drm_info_node *node = s->private; 560 struct sti_hqvdp *hqvdp = (struct sti_hqvdp *)node->info_ent->data; 561 int cmd, cmd_offset, infoxp70; 562 void *virt; 563 564 seq_printf(s, "%s: (vaddr = 0x%p)", 565 sti_plane_to_str(&hqvdp->plane), hqvdp->regs); 566 567 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70); 568 DBGFS_DUMP(HQVDP_MBX_INFO_HOST); 569 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST); 570 DBGFS_DUMP(HQVDP_MBX_INFO_XP70); 571 infoxp70 = readl(hqvdp->regs + HQVDP_MBX_INFO_XP70); 572 seq_puts(s, "\tFirmware state: "); 573 if (infoxp70 & INFO_XP70_FW_READY) 574 seq_puts(s, "idle and ready"); 575 else if (infoxp70 & INFO_XP70_FW_PROCESSING) 576 seq_puts(s, "processing a picture"); 577 else if (infoxp70 & INFO_XP70_FW_INITQUEUES) 578 seq_puts(s, "programming queues"); 579 else 580 seq_puts(s, "NOT READY"); 581 582 DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL); 583 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1); 584 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1) 585 & STARTUP_CTRL1_RST_DONE) 586 seq_puts(s, "\tReset is done"); 587 else 588 seq_puts(s, "\tReset is NOT done"); 589 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2); 590 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2) 591 & STARTUP_CTRL2_FETCH_EN) 592 seq_puts(s, "\tFetch is enabled"); 593 else 594 seq_puts(s, "\tFetch is NOT enabled"); 595 DBGFS_DUMP(HQVDP_MBX_GP_STATUS); 596 DBGFS_DUMP(HQVDP_MBX_NEXT_CMD); 597 DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD); 598 DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC); 599 if (!(readl(hqvdp->regs + HQVDP_MBX_SOFT_VSYNC) & 3)) 600 seq_puts(s, "\tHW Vsync"); 601 else 602 seq_puts(s, "\tSW Vsync ?!?!"); 603 604 /* Last command */ 605 cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); 606 cmd_offset = sti_hqvdp_get_curr_cmd(hqvdp); 607 if (cmd_offset == -1) { 608 seq_puts(s, "\n\n Last command: unknown"); 609 } else { 610 virt = hqvdp->hqvdp_cmd + cmd_offset; 611 seq_printf(s, "\n\n Last command: address @ 0x%x (0x%p)", 612 cmd, virt); 613 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt); 614 } 615 616 /* Next command */ 617 cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); 618 cmd_offset = sti_hqvdp_get_next_cmd(hqvdp); 619 if (cmd_offset == -1) { 620 seq_puts(s, "\n\n Next command: unknown"); 621 } else { 622 virt = hqvdp->hqvdp_cmd + cmd_offset; 623 seq_printf(s, "\n\n Next command address: @ 0x%x (0x%p)", 624 cmd, virt); 625 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt); 626 } 627 628 seq_putc(s, '\n'); 629 return 0; 630 } 631 632 static struct drm_info_list hqvdp_debugfs_files[] = { 633 { "hqvdp", hqvdp_dbg_show, 0, NULL }, 634 }; 635 636 static int hqvdp_debugfs_init(struct sti_hqvdp *hqvdp, struct drm_minor *minor) 637 { 638 unsigned int i; 639 640 for (i = 0; i < ARRAY_SIZE(hqvdp_debugfs_files); i++) 641 hqvdp_debugfs_files[i].data = hqvdp; 642 643 return drm_debugfs_create_files(hqvdp_debugfs_files, 644 ARRAY_SIZE(hqvdp_debugfs_files), 645 minor->debugfs_root, minor); 646 } 647 648 /** 649 * sti_hqvdp_update_hvsrc 650 * @orient: horizontal or vertical 651 * @scale: scaling/zoom factor 652 * @hvsrc: the structure containing the LUT coef 653 * 654 * Update the Y and C Lut coef, as well as the shift param 655 * 656 * RETURNS: 657 * None. 658 */ 659 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale, 660 struct sti_hqvdp_hvsrc *hvsrc) 661 { 662 const int *coef_c, *coef_y; 663 int shift_c, shift_y; 664 665 /* Get the appropriate coef tables */ 666 if (scale < SCALE_MAX_FOR_LEG_LUT_F) { 667 coef_y = coef_lut_f_y_legacy; 668 coef_c = coef_lut_f_c_legacy; 669 shift_y = SHIFT_LUT_F_Y_LEGACY; 670 shift_c = SHIFT_LUT_F_C_LEGACY; 671 } else if (scale < SCALE_MAX_FOR_LEG_LUT_E) { 672 coef_y = coef_lut_e_y_legacy; 673 coef_c = coef_lut_e_c_legacy; 674 shift_y = SHIFT_LUT_E_Y_LEGACY; 675 shift_c = SHIFT_LUT_E_C_LEGACY; 676 } else if (scale < SCALE_MAX_FOR_LEG_LUT_D) { 677 coef_y = coef_lut_d_y_legacy; 678 coef_c = coef_lut_d_c_legacy; 679 shift_y = SHIFT_LUT_D_Y_LEGACY; 680 shift_c = SHIFT_LUT_D_C_LEGACY; 681 } else if (scale < SCALE_MAX_FOR_LEG_LUT_C) { 682 coef_y = coef_lut_c_y_legacy; 683 coef_c = coef_lut_c_c_legacy; 684 shift_y = SHIFT_LUT_C_Y_LEGACY; 685 shift_c = SHIFT_LUT_C_C_LEGACY; 686 } else if (scale == SCALE_MAX_FOR_LEG_LUT_C) { 687 coef_y = coef_c = coef_lut_b; 688 shift_y = shift_c = SHIFT_LUT_B; 689 } else { 690 coef_y = coef_c = coef_lut_a_legacy; 691 shift_y = shift_c = SHIFT_LUT_A_LEGACY; 692 } 693 694 if (orient == HVSRC_HORI) { 695 hvsrc->hori_shift = (shift_c << 16) | shift_y; 696 memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef)); 697 memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef)); 698 } else { 699 hvsrc->vert_shift = (shift_c << 16) | shift_y; 700 memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef)); 701 memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef)); 702 } 703 } 704 705 /** 706 * sti_hqvdp_check_hw_scaling 707 * @hqvdp: hqvdp pointer 708 * @mode: display mode with timing constraints 709 * @src_w: source width 710 * @src_h: source height 711 * @dst_w: destination width 712 * @dst_h: destination height 713 * 714 * Check if the HW is able to perform the scaling request 715 * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where: 716 * Zy = OutputHeight / InputHeight 717 * LFW = (Tx * IPClock) / (MaxNbCycles * Cp) 718 * Tx : Total video mode horizontal resolution 719 * IPClock : HQVDP IP clock (Mhz) 720 * MaxNbCycles: max(InputWidth, OutputWidth) 721 * Cp: Video mode pixel clock (Mhz) 722 * 723 * RETURNS: 724 * True if the HW can scale. 725 */ 726 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp *hqvdp, 727 struct drm_display_mode *mode, 728 int src_w, int src_h, 729 int dst_w, int dst_h) 730 { 731 unsigned long lfw; 732 unsigned int inv_zy; 733 734 lfw = mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000); 735 lfw /= max(src_w, dst_w) * mode->clock / 1000; 736 737 inv_zy = DIV_ROUND_UP(src_h, dst_h); 738 739 return (inv_zy <= lfw) ? true : false; 740 } 741 742 /** 743 * sti_hqvdp_disable 744 * @hqvdp: hqvdp pointer 745 * 746 * Disables the HQVDP plane 747 */ 748 static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp) 749 { 750 int i; 751 752 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp->plane)); 753 754 /* Unregister VTG Vsync callback */ 755 if (sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb)) 756 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 757 758 /* Set next cmd to NULL */ 759 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); 760 761 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 762 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70) 763 & INFO_XP70_FW_READY) 764 break; 765 msleep(POLL_DELAY_MS); 766 } 767 768 /* VTG can stop now */ 769 clk_disable_unprepare(hqvdp->clk_pix_main); 770 771 if (i == POLL_MAX_ATTEMPT) 772 DRM_ERROR("XP70 could not revert to idle\n"); 773 774 hqvdp->plane.status = STI_PLANE_DISABLED; 775 hqvdp->vtg_registered = false; 776 } 777 778 /** 779 * sti_vdp_vtg_cb 780 * @nb: notifier block 781 * @evt: event message 782 * @data: private data 783 * 784 * Handle VTG Vsync event, display pending bottom field 785 * 786 * RETURNS: 787 * 0 on success. 788 */ 789 static int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data) 790 { 791 struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb); 792 int btm_cmd_offset, top_cmd_offest; 793 struct sti_hqvdp_cmd *btm_cmd, *top_cmd; 794 795 if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) { 796 DRM_DEBUG_DRIVER("Unknown event\n"); 797 return 0; 798 } 799 800 if (hqvdp->plane.status == STI_PLANE_FLUSHING) { 801 /* disable need to be synchronize on vsync event */ 802 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 803 sti_plane_to_str(&hqvdp->plane)); 804 805 sti_hqvdp_disable(hqvdp); 806 } 807 808 if (hqvdp->btm_field_pending) { 809 /* Create the btm field command from the current one */ 810 btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp); 811 top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp); 812 if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) { 813 DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n"); 814 return -EBUSY; 815 } 816 817 btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset; 818 top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest; 819 820 memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd)); 821 822 btm_cmd->top.config = TOP_CONFIG_INTER_BTM; 823 btm_cmd->top.current_luma += 824 btm_cmd->top.luma_src_pitch / 2; 825 btm_cmd->top.current_chroma += 826 btm_cmd->top.chroma_src_pitch / 2; 827 828 /* Post the command to mailbox */ 829 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset, 830 hqvdp->regs + HQVDP_MBX_NEXT_CMD); 831 832 hqvdp->btm_field_pending = false; 833 834 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n", 835 __func__, hqvdp->hqvdp_cmd_paddr); 836 837 sti_plane_update_fps(&hqvdp->plane, false, true); 838 } 839 840 return 0; 841 } 842 843 static void sti_hqvdp_init(struct sti_hqvdp *hqvdp) 844 { 845 int size; 846 dma_addr_t dma_addr; 847 848 hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb; 849 850 /* Allocate memory for the VDP commands */ 851 size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd); 852 hqvdp->hqvdp_cmd = dma_alloc_wc(hqvdp->dev, size, 853 &dma_addr, 854 GFP_KERNEL | GFP_DMA); 855 if (!hqvdp->hqvdp_cmd) { 856 DRM_ERROR("Failed to allocate memory for VDP cmd\n"); 857 return; 858 } 859 860 hqvdp->hqvdp_cmd_paddr = (u32)dma_addr; 861 memset(hqvdp->hqvdp_cmd, 0, size); 862 } 863 864 static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp) 865 { 866 /* Configure Plugs (same for RD & WR) */ 867 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE); 868 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC); 869 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC); 870 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK); 871 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG); 872 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE); 873 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL); 874 875 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE); 876 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC); 877 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC); 878 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK); 879 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG); 880 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE); 881 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL); 882 } 883 884 /** 885 * sti_hqvdp_start_xp70 886 * @hqvdp: hqvdp pointer 887 * 888 * Run the xP70 initialization sequence 889 */ 890 static void sti_hqvdp_start_xp70(struct sti_hqvdp *hqvdp) 891 { 892 const struct firmware *firmware; 893 u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem; 894 u8 *data; 895 int i; 896 struct fw_header { 897 int rd_size; 898 int wr_size; 899 int pmem_size; 900 int dmem_size; 901 } *header; 902 903 DRM_DEBUG_DRIVER("\n"); 904 905 if (hqvdp->xp70_initialized) { 906 DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n"); 907 return; 908 } 909 910 /* Request firmware */ 911 if (request_firmware(&firmware, HQVDP_FMW_NAME, hqvdp->dev)) { 912 DRM_ERROR("Can't get HQVDP firmware\n"); 913 return; 914 } 915 916 /* Check firmware parts */ 917 if (!firmware) { 918 DRM_ERROR("Firmware not available\n"); 919 return; 920 } 921 922 header = (struct fw_header *)firmware->data; 923 if (firmware->size < sizeof(*header)) { 924 DRM_ERROR("Invalid firmware size (%d)\n", firmware->size); 925 goto out; 926 } 927 if ((sizeof(*header) + header->rd_size + header->wr_size + 928 header->pmem_size + header->dmem_size) != firmware->size) { 929 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n", 930 sizeof(*header), header->rd_size, header->wr_size, 931 header->pmem_size, header->dmem_size, 932 firmware->size); 933 goto out; 934 } 935 936 data = (u8 *)firmware->data; 937 data += sizeof(*header); 938 fw_rd_plug = (void *)data; 939 data += header->rd_size; 940 fw_wr_plug = (void *)data; 941 data += header->wr_size; 942 fw_pmem = (void *)data; 943 data += header->pmem_size; 944 fw_dmem = (void *)data; 945 946 /* Enable clock */ 947 if (clk_prepare_enable(hqvdp->clk)) 948 DRM_ERROR("Failed to prepare/enable HQVDP clk\n"); 949 950 /* Reset */ 951 writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL); 952 953 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 954 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1) 955 & STARTUP_CTRL1_RST_DONE) 956 break; 957 msleep(POLL_DELAY_MS); 958 } 959 if (i == POLL_MAX_ATTEMPT) { 960 DRM_ERROR("Could not reset\n"); 961 clk_disable_unprepare(hqvdp->clk); 962 goto out; 963 } 964 965 /* Init Read & Write plugs */ 966 for (i = 0; i < header->rd_size / 4; i++) 967 writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4); 968 for (i = 0; i < header->wr_size / 4; i++) 969 writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4); 970 971 sti_hqvdp_init_plugs(hqvdp); 972 973 /* Authorize Idle Mode */ 974 writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1); 975 976 /* Prevent VTG interruption during the boot */ 977 writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC); 978 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); 979 980 /* Download PMEM & DMEM */ 981 for (i = 0; i < header->pmem_size / 4; i++) 982 writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4); 983 for (i = 0; i < header->dmem_size / 4; i++) 984 writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4); 985 986 /* Enable fetch */ 987 writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2); 988 989 /* Wait end of boot */ 990 for (i = 0; i < POLL_MAX_ATTEMPT; i++) { 991 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70) 992 & INFO_XP70_FW_READY) 993 break; 994 msleep(POLL_DELAY_MS); 995 } 996 if (i == POLL_MAX_ATTEMPT) { 997 DRM_ERROR("Could not boot\n"); 998 clk_disable_unprepare(hqvdp->clk); 999 goto out; 1000 } 1001 1002 /* Launch Vsync */ 1003 writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC); 1004 1005 DRM_INFO("HQVDP XP70 initialized\n"); 1006 1007 hqvdp->xp70_initialized = true; 1008 1009 out: 1010 release_firmware(firmware); 1011 } 1012 1013 static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane, 1014 struct drm_plane_state *state) 1015 { 1016 struct sti_plane *plane = to_sti_plane(drm_plane); 1017 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1018 struct drm_crtc *crtc = state->crtc; 1019 struct drm_framebuffer *fb = state->fb; 1020 struct drm_crtc_state *crtc_state; 1021 struct drm_display_mode *mode; 1022 int dst_x, dst_y, dst_w, dst_h; 1023 int src_x, src_y, src_w, src_h; 1024 1025 /* no need for further checks if the plane is being disabled */ 1026 if (!crtc || !fb) 1027 return 0; 1028 1029 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 1030 mode = &crtc_state->mode; 1031 dst_x = state->crtc_x; 1032 dst_y = state->crtc_y; 1033 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 1034 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 1035 /* src_x are in 16.16 format */ 1036 src_x = state->src_x >> 16; 1037 src_y = state->src_y >> 16; 1038 src_w = state->src_w >> 16; 1039 src_h = state->src_h >> 16; 1040 1041 if (mode->clock && !sti_hqvdp_check_hw_scaling(hqvdp, mode, 1042 src_w, src_h, 1043 dst_w, dst_h)) { 1044 DRM_ERROR("Scaling beyond HW capabilities\n"); 1045 return -EINVAL; 1046 } 1047 1048 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 1049 DRM_ERROR("Can't get CMA GEM object for fb\n"); 1050 return -EINVAL; 1051 } 1052 1053 /* 1054 * Input / output size 1055 * Align to upper even value 1056 */ 1057 dst_w = ALIGN(dst_w, 2); 1058 dst_h = ALIGN(dst_h, 2); 1059 1060 if ((src_w > MAX_WIDTH) || (src_w < MIN_WIDTH) || 1061 (src_h > MAX_HEIGHT) || (src_h < MIN_HEIGHT) || 1062 (dst_w > MAX_WIDTH) || (dst_w < MIN_WIDTH) || 1063 (dst_h > MAX_HEIGHT) || (dst_h < MIN_HEIGHT)) { 1064 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n", 1065 src_w, src_h, 1066 dst_w, dst_h); 1067 return -EINVAL; 1068 } 1069 1070 if (!hqvdp->xp70_initialized) 1071 /* Start HQVDP XP70 coprocessor */ 1072 sti_hqvdp_start_xp70(hqvdp); 1073 1074 if (!hqvdp->vtg_registered) { 1075 /* Prevent VTG shutdown */ 1076 if (clk_prepare_enable(hqvdp->clk_pix_main)) { 1077 DRM_ERROR("Failed to prepare/enable pix main clk\n"); 1078 return -EINVAL; 1079 } 1080 1081 /* Register VTG Vsync callback to handle bottom fields */ 1082 if (sti_vtg_register_client(hqvdp->vtg, 1083 &hqvdp->vtg_nb, 1084 crtc)) { 1085 DRM_ERROR("Cannot register VTG notifier\n"); 1086 clk_disable_unprepare(hqvdp->clk_pix_main); 1087 return -EINVAL; 1088 } 1089 hqvdp->vtg_registered = true; 1090 } 1091 1092 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 1093 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)), 1094 drm_plane->base.id, sti_plane_to_str(plane)); 1095 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 1096 sti_plane_to_str(plane), 1097 dst_w, dst_h, dst_x, dst_y, 1098 src_w, src_h, src_x, src_y); 1099 1100 return 0; 1101 } 1102 1103 static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane, 1104 struct drm_plane_state *oldstate) 1105 { 1106 struct drm_plane_state *state = drm_plane->state; 1107 struct sti_plane *plane = to_sti_plane(drm_plane); 1108 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1109 struct drm_crtc *crtc = state->crtc; 1110 struct drm_framebuffer *fb = state->fb; 1111 struct drm_display_mode *mode; 1112 int dst_x, dst_y, dst_w, dst_h; 1113 int src_x, src_y, src_w, src_h; 1114 struct drm_gem_cma_object *cma_obj; 1115 struct sti_hqvdp_cmd *cmd; 1116 int scale_h, scale_v; 1117 int cmd_offset; 1118 1119 if (!crtc || !fb) 1120 return; 1121 1122 if ((oldstate->fb == state->fb) && 1123 (oldstate->crtc_x == state->crtc_x) && 1124 (oldstate->crtc_y == state->crtc_y) && 1125 (oldstate->crtc_w == state->crtc_w) && 1126 (oldstate->crtc_h == state->crtc_h) && 1127 (oldstate->src_x == state->src_x) && 1128 (oldstate->src_y == state->src_y) && 1129 (oldstate->src_w == state->src_w) && 1130 (oldstate->src_h == state->src_h)) { 1131 /* No change since last update, do not post cmd */ 1132 DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 1133 plane->status = STI_PLANE_UPDATED; 1134 return; 1135 } 1136 1137 mode = &crtc->mode; 1138 dst_x = state->crtc_x; 1139 dst_y = state->crtc_y; 1140 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 1141 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 1142 /* src_x are in 16.16 format */ 1143 src_x = state->src_x >> 16; 1144 src_y = state->src_y >> 16; 1145 src_w = state->src_w >> 16; 1146 src_h = state->src_h >> 16; 1147 1148 cmd_offset = sti_hqvdp_get_free_cmd(hqvdp); 1149 if (cmd_offset == -1) { 1150 DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n"); 1151 return; 1152 } 1153 cmd = hqvdp->hqvdp_cmd + cmd_offset; 1154 1155 /* Static parameters, defaulting to progressive mode */ 1156 cmd->top.config = TOP_CONFIG_PROGRESSIVE; 1157 cmd->top.mem_format = TOP_MEM_FORMAT_DFLT; 1158 cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT; 1159 cmd->csdi.config = CSDI_CONFIG_PROG; 1160 1161 /* VC1RE, FMD bypassed : keep everything set to 0 1162 * IQI/P2I bypassed */ 1163 cmd->iqi.config = IQI_CONFIG_DFLT; 1164 cmd->iqi.con_bri = IQI_CON_BRI_DFLT; 1165 cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT; 1166 cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT; 1167 1168 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 1169 1170 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 1171 (char *)&fb->format->format, 1172 (unsigned long)cma_obj->paddr); 1173 1174 /* Buffer planes address */ 1175 cmd->top.current_luma = (u32)cma_obj->paddr + fb->offsets[0]; 1176 cmd->top.current_chroma = (u32)cma_obj->paddr + fb->offsets[1]; 1177 1178 /* Pitches */ 1179 cmd->top.luma_processed_pitch = fb->pitches[0]; 1180 cmd->top.luma_src_pitch = fb->pitches[0]; 1181 cmd->top.chroma_processed_pitch = fb->pitches[1]; 1182 cmd->top.chroma_src_pitch = fb->pitches[1]; 1183 1184 /* Input / output size 1185 * Align to upper even value */ 1186 dst_w = ALIGN(dst_w, 2); 1187 dst_h = ALIGN(dst_h, 2); 1188 1189 cmd->top.input_viewport_size = src_h << 16 | src_w; 1190 cmd->top.input_frame_size = src_h << 16 | src_w; 1191 cmd->hvsrc.output_picture_size = dst_h << 16 | dst_w; 1192 cmd->top.input_viewport_ori = src_y << 16 | src_x; 1193 1194 /* Handle interlaced */ 1195 if (fb->flags & DRM_MODE_FB_INTERLACED) { 1196 /* Top field to display */ 1197 cmd->top.config = TOP_CONFIG_INTER_TOP; 1198 1199 /* Update pitches and vert size */ 1200 cmd->top.input_frame_size = (src_h / 2) << 16 | src_w; 1201 cmd->top.luma_processed_pitch *= 2; 1202 cmd->top.luma_src_pitch *= 2; 1203 cmd->top.chroma_processed_pitch *= 2; 1204 cmd->top.chroma_src_pitch *= 2; 1205 1206 /* Enable directional deinterlacing processing */ 1207 cmd->csdi.config = CSDI_CONFIG_INTER_DIR; 1208 cmd->csdi.config2 = CSDI_CONFIG2_DFLT; 1209 cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT; 1210 } 1211 1212 /* Update hvsrc lut coef */ 1213 scale_h = SCALE_FACTOR * dst_w / src_w; 1214 sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc); 1215 1216 scale_v = SCALE_FACTOR * dst_h / src_h; 1217 sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc); 1218 1219 writel(hqvdp->hqvdp_cmd_paddr + cmd_offset, 1220 hqvdp->regs + HQVDP_MBX_NEXT_CMD); 1221 1222 /* Interlaced : get ready to display the bottom field at next Vsync */ 1223 if (fb->flags & DRM_MODE_FB_INTERLACED) 1224 hqvdp->btm_field_pending = true; 1225 1226 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n", 1227 __func__, hqvdp->hqvdp_cmd_paddr + cmd_offset); 1228 1229 sti_plane_update_fps(plane, true, true); 1230 1231 plane->status = STI_PLANE_UPDATED; 1232 } 1233 1234 static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane, 1235 struct drm_plane_state *oldstate) 1236 { 1237 struct sti_plane *plane = to_sti_plane(drm_plane); 1238 1239 if (!oldstate->crtc) { 1240 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 1241 drm_plane->base.id); 1242 return; 1243 } 1244 1245 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 1246 oldstate->crtc->base.id, 1247 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 1248 drm_plane->base.id, sti_plane_to_str(plane)); 1249 1250 plane->status = STI_PLANE_DISABLING; 1251 } 1252 1253 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs = { 1254 .atomic_check = sti_hqvdp_atomic_check, 1255 .atomic_update = sti_hqvdp_atomic_update, 1256 .atomic_disable = sti_hqvdp_atomic_disable, 1257 }; 1258 1259 static void sti_hqvdp_destroy(struct drm_plane *drm_plane) 1260 { 1261 DRM_DEBUG_DRIVER("\n"); 1262 1263 drm_plane_helper_disable(drm_plane, NULL); 1264 drm_plane_cleanup(drm_plane); 1265 } 1266 1267 static int sti_hqvdp_late_register(struct drm_plane *drm_plane) 1268 { 1269 struct sti_plane *plane = to_sti_plane(drm_plane); 1270 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1271 1272 return hqvdp_debugfs_init(hqvdp, drm_plane->dev->primary); 1273 } 1274 1275 static const struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs = { 1276 .update_plane = drm_atomic_helper_update_plane, 1277 .disable_plane = drm_atomic_helper_disable_plane, 1278 .destroy = sti_hqvdp_destroy, 1279 .reset = sti_plane_reset, 1280 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1281 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1282 .late_register = sti_hqvdp_late_register, 1283 }; 1284 1285 static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev, 1286 struct device *dev, int desc) 1287 { 1288 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev); 1289 int res; 1290 1291 hqvdp->plane.desc = desc; 1292 hqvdp->plane.status = STI_PLANE_DISABLED; 1293 1294 sti_hqvdp_init(hqvdp); 1295 1296 res = drm_universal_plane_init(drm_dev, &hqvdp->plane.drm_plane, 1, 1297 &sti_hqvdp_plane_helpers_funcs, 1298 hqvdp_supported_formats, 1299 ARRAY_SIZE(hqvdp_supported_formats), 1300 NULL, DRM_PLANE_TYPE_OVERLAY, NULL); 1301 if (res) { 1302 DRM_ERROR("Failed to initialize universal plane\n"); 1303 return NULL; 1304 } 1305 1306 drm_plane_helper_add(&hqvdp->plane.drm_plane, &sti_hqvdp_helpers_funcs); 1307 1308 sti_plane_init_property(&hqvdp->plane, DRM_PLANE_TYPE_OVERLAY); 1309 1310 return &hqvdp->plane.drm_plane; 1311 } 1312 1313 static int sti_hqvdp_bind(struct device *dev, struct device *master, void *data) 1314 { 1315 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev); 1316 struct drm_device *drm_dev = data; 1317 struct drm_plane *plane; 1318 1319 DRM_DEBUG_DRIVER("\n"); 1320 1321 hqvdp->drm_dev = drm_dev; 1322 1323 /* Create HQVDP plane once xp70 is initialized */ 1324 plane = sti_hqvdp_create(drm_dev, hqvdp->dev, STI_HQVDP_0); 1325 if (!plane) 1326 DRM_ERROR("Can't create HQVDP plane\n"); 1327 1328 return 0; 1329 } 1330 1331 static void sti_hqvdp_unbind(struct device *dev, 1332 struct device *master, void *data) 1333 { 1334 /* do nothing */ 1335 } 1336 1337 static const struct component_ops sti_hqvdp_ops = { 1338 .bind = sti_hqvdp_bind, 1339 .unbind = sti_hqvdp_unbind, 1340 }; 1341 1342 static int sti_hqvdp_probe(struct platform_device *pdev) 1343 { 1344 struct device *dev = &pdev->dev; 1345 struct device_node *vtg_np; 1346 struct sti_hqvdp *hqvdp; 1347 struct resource *res; 1348 1349 DRM_DEBUG_DRIVER("\n"); 1350 1351 hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL); 1352 if (!hqvdp) { 1353 DRM_ERROR("Failed to allocate HQVDP context\n"); 1354 return -ENOMEM; 1355 } 1356 1357 hqvdp->dev = dev; 1358 1359 /* Get Memory resources */ 1360 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1361 if (!res) { 1362 DRM_ERROR("Get memory resource failed\n"); 1363 return -ENXIO; 1364 } 1365 hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res)); 1366 if (!hqvdp->regs) { 1367 DRM_ERROR("Register mapping failed\n"); 1368 return -ENXIO; 1369 } 1370 1371 /* Get clock resources */ 1372 hqvdp->clk = devm_clk_get(dev, "hqvdp"); 1373 hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main"); 1374 if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) { 1375 DRM_ERROR("Cannot get clocks\n"); 1376 return -ENXIO; 1377 } 1378 1379 /* Get reset resources */ 1380 hqvdp->reset = devm_reset_control_get(dev, "hqvdp"); 1381 if (!IS_ERR(hqvdp->reset)) 1382 reset_control_deassert(hqvdp->reset); 1383 1384 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0); 1385 if (vtg_np) 1386 hqvdp->vtg = of_vtg_find(vtg_np); 1387 of_node_put(vtg_np); 1388 1389 platform_set_drvdata(pdev, hqvdp); 1390 1391 return component_add(&pdev->dev, &sti_hqvdp_ops); 1392 } 1393 1394 static int sti_hqvdp_remove(struct platform_device *pdev) 1395 { 1396 component_del(&pdev->dev, &sti_hqvdp_ops); 1397 return 0; 1398 } 1399 1400 static const struct of_device_id hqvdp_of_match[] = { 1401 { .compatible = "st,stih407-hqvdp", }, 1402 { /* end node */ } 1403 }; 1404 MODULE_DEVICE_TABLE(of, hqvdp_of_match); 1405 1406 struct platform_driver sti_hqvdp_driver = { 1407 .driver = { 1408 .name = "sti-hqvdp", 1409 .owner = THIS_MODULE, 1410 .of_match_table = hqvdp_of_match, 1411 }, 1412 .probe = sti_hqvdp_probe, 1413 .remove = sti_hqvdp_remove, 1414 }; 1415 1416 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 1417 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 1418 MODULE_LICENSE("GPL"); 1419