1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 7 #ifndef _STI_HDMI_H_ 8 #define _STI_HDMI_H_ 9 10 #include <linux/hdmi.h> 11 #include <linux/platform_device.h> 12 13 #include <drm/drmP.h> 14 15 #define HDMI_STA 0x0010 16 #define HDMI_STA_DLL_LCK BIT(5) 17 #define HDMI_STA_HOT_PLUG BIT(4) 18 19 struct sti_hdmi; 20 21 struct hdmi_phy_ops { 22 bool (*start)(struct sti_hdmi *hdmi); 23 void (*stop)(struct sti_hdmi *hdmi); 24 }; 25 26 /* values for the framing mode property */ 27 enum sti_hdmi_modes { 28 HDMI_MODE_HDMI, 29 HDMI_MODE_DVI, 30 }; 31 32 static const struct drm_prop_enum_list hdmi_mode_names[] = { 33 { HDMI_MODE_HDMI, "hdmi" }, 34 { HDMI_MODE_DVI, "dvi" }, 35 }; 36 37 #define DEFAULT_HDMI_MODE HDMI_MODE_HDMI 38 39 static const struct drm_prop_enum_list colorspace_mode_names[] = { 40 { HDMI_COLORSPACE_RGB, "rgb" }, 41 { HDMI_COLORSPACE_YUV422, "yuv422" }, 42 { HDMI_COLORSPACE_YUV444, "yuv444" }, 43 }; 44 45 #define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB 46 47 /** 48 * STI hdmi structure 49 * 50 * @dev: driver device 51 * @drm_dev: pointer to drm device 52 * @mode: current display mode selected 53 * @regs: hdmi register 54 * @syscfg: syscfg register for pll rejection configuration 55 * @clk_pix: hdmi pixel clock 56 * @clk_tmds: hdmi tmds clock 57 * @clk_phy: hdmi phy clock 58 * @clk_audio: hdmi audio clock 59 * @irq: hdmi interrupt number 60 * @irq_status: interrupt status register 61 * @phy_ops: phy start/stop operations 62 * @enabled: true if hdmi is enabled else false 63 * @hpd: hot plug detect status 64 * @wait_event: wait event 65 * @event_received: wait event status 66 * @reset: reset control of the hdmi phy 67 * @ddc_adapt: i2c ddc adapter 68 * @colorspace: current colorspace selected 69 * @hdmi_mode: select framing for HDMI or DVI 70 */ 71 struct sti_hdmi { 72 struct device dev; 73 struct drm_device *drm_dev; 74 struct drm_display_mode mode; 75 void __iomem *regs; 76 void __iomem *syscfg; 77 struct clk *clk_pix; 78 struct clk *clk_tmds; 79 struct clk *clk_phy; 80 struct clk *clk_audio; 81 int irq; 82 u32 irq_status; 83 struct hdmi_phy_ops *phy_ops; 84 bool enabled; 85 bool hpd; 86 wait_queue_head_t wait_event; 87 bool event_received; 88 struct reset_control *reset; 89 struct i2c_adapter *ddc_adapt; 90 enum hdmi_colorspace colorspace; 91 enum sti_hdmi_modes hdmi_mode; 92 }; 93 94 u32 hdmi_read(struct sti_hdmi *hdmi, int offset); 95 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset); 96 97 /** 98 * hdmi phy config structure 99 * 100 * A pointer to an array of these structures is passed to a TMDS (HDMI) output 101 * via the control interface to provide board and SoC specific 102 * configurations of the HDMI PHY. Each entry in the array specifies a hardware 103 * specific configuration for a given TMDS clock frequency range. 104 * 105 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to 106 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to 107 * @config: SoC specific register configuration 108 */ 109 struct hdmi_phy_config { 110 u32 min_tmds_freq; 111 u32 max_tmds_freq; 112 u32 config[4]; 113 }; 114 115 #endif 116