1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. 5 */ 6 7 #ifndef _STI_HDMI_H_ 8 #define _STI_HDMI_H_ 9 10 #include <linux/hdmi.h> 11 #include <linux/platform_device.h> 12 13 #include <drm/drmP.h> 14 #include <media/cec-notifier.h> 15 16 #define HDMI_STA 0x0010 17 #define HDMI_STA_DLL_LCK BIT(5) 18 #define HDMI_STA_HOT_PLUG BIT(4) 19 20 struct sti_hdmi; 21 22 struct hdmi_phy_ops { 23 bool (*start)(struct sti_hdmi *hdmi); 24 void (*stop)(struct sti_hdmi *hdmi); 25 }; 26 27 struct hdmi_audio_params { 28 bool enabled; 29 unsigned int sample_width; 30 unsigned int sample_rate; 31 struct hdmi_audio_infoframe cea; 32 }; 33 34 static const struct drm_prop_enum_list colorspace_mode_names[] = { 35 { HDMI_COLORSPACE_RGB, "rgb" }, 36 { HDMI_COLORSPACE_YUV422, "yuv422" }, 37 { HDMI_COLORSPACE_YUV444, "yuv444" }, 38 }; 39 40 #define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB 41 42 /** 43 * STI hdmi structure 44 * 45 * @dev: driver device 46 * @drm_dev: pointer to drm device 47 * @mode: current display mode selected 48 * @regs: hdmi register 49 * @syscfg: syscfg register for pll rejection configuration 50 * @clk_pix: hdmi pixel clock 51 * @clk_tmds: hdmi tmds clock 52 * @clk_phy: hdmi phy clock 53 * @clk_audio: hdmi audio clock 54 * @irq: hdmi interrupt number 55 * @irq_status: interrupt status register 56 * @phy_ops: phy start/stop operations 57 * @enabled: true if hdmi is enabled else false 58 * @hpd: hot plug detect status 59 * @wait_event: wait event 60 * @event_received: wait event status 61 * @reset: reset control of the hdmi phy 62 * @ddc_adapt: i2c ddc adapter 63 * @colorspace: current colorspace selected 64 * @hdmi_monitor: true if HDMI monitor detected else DVI monitor assumed 65 * @audio_pdev: ASoC hdmi-codec platform device 66 * @audio: hdmi audio parameters. 67 * @drm_connector: hdmi connector 68 * @notifier: hotplug detect notifier 69 */ 70 struct sti_hdmi { 71 struct device dev; 72 struct drm_device *drm_dev; 73 struct drm_display_mode mode; 74 void __iomem *regs; 75 void __iomem *syscfg; 76 struct clk *clk_pix; 77 struct clk *clk_tmds; 78 struct clk *clk_phy; 79 struct clk *clk_audio; 80 int irq; 81 u32 irq_status; 82 struct hdmi_phy_ops *phy_ops; 83 bool enabled; 84 bool hpd; 85 wait_queue_head_t wait_event; 86 bool event_received; 87 struct reset_control *reset; 88 struct i2c_adapter *ddc_adapt; 89 enum hdmi_colorspace colorspace; 90 bool hdmi_monitor; 91 struct platform_device *audio_pdev; 92 struct hdmi_audio_params audio; 93 struct drm_connector *drm_connector; 94 struct cec_notifier *notifier; 95 }; 96 97 u32 hdmi_read(struct sti_hdmi *hdmi, int offset); 98 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset); 99 100 /** 101 * hdmi phy config structure 102 * 103 * A pointer to an array of these structures is passed to a TMDS (HDMI) output 104 * via the control interface to provide board and SoC specific 105 * configurations of the HDMI PHY. Each entry in the array specifies a hardware 106 * specific configuration for a given TMDS clock frequency range. 107 * 108 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to 109 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to 110 * @config: SoC specific register configuration 111 */ 112 struct hdmi_phy_config { 113 u32 min_tmds_freq; 114 u32 max_tmds_freq; 115 u32 config[4]; 116 }; 117 118 #endif 119