1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/seq_file.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_debugfs.h> 16 #include <drm/drm_device.h> 17 #include <drm/drm_file.h> 18 #include <drm/drm_print.h> 19 #include <drm/drm_probe_helper.h> 20 21 /* HDformatter registers */ 22 #define HDA_ANA_CFG 0x0000 23 #define HDA_ANA_SCALE_CTRL_Y 0x0004 24 #define HDA_ANA_SCALE_CTRL_CB 0x0008 25 #define HDA_ANA_SCALE_CTRL_CR 0x000C 26 #define HDA_ANA_ANC_CTRL 0x0010 27 #define HDA_ANA_SRC_Y_CFG 0x0014 28 #define HDA_COEFF_Y_PH1_TAP123 0x0018 29 #define HDA_COEFF_Y_PH1_TAP456 0x001C 30 #define HDA_COEFF_Y_PH2_TAP123 0x0020 31 #define HDA_COEFF_Y_PH2_TAP456 0x0024 32 #define HDA_COEFF_Y_PH3_TAP123 0x0028 33 #define HDA_COEFF_Y_PH3_TAP456 0x002C 34 #define HDA_COEFF_Y_PH4_TAP123 0x0030 35 #define HDA_COEFF_Y_PH4_TAP456 0x0034 36 #define HDA_ANA_SRC_C_CFG 0x0040 37 #define HDA_COEFF_C_PH1_TAP123 0x0044 38 #define HDA_COEFF_C_PH1_TAP456 0x0048 39 #define HDA_COEFF_C_PH2_TAP123 0x004C 40 #define HDA_COEFF_C_PH2_TAP456 0x0050 41 #define HDA_COEFF_C_PH3_TAP123 0x0054 42 #define HDA_COEFF_C_PH3_TAP456 0x0058 43 #define HDA_COEFF_C_PH4_TAP123 0x005C 44 #define HDA_COEFF_C_PH4_TAP456 0x0060 45 #define HDA_SYNC_AWGI 0x0300 46 47 /* HDA_ANA_CFG */ 48 #define CFG_AWG_ASYNC_EN BIT(0) 49 #define CFG_AWG_ASYNC_HSYNC_MTD BIT(1) 50 #define CFG_AWG_ASYNC_VSYNC_MTD BIT(2) 51 #define CFG_AWG_SYNC_DEL BIT(3) 52 #define CFG_AWG_FLTR_MODE_SHIFT 4 53 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT) 54 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT) 55 #define CFG_AWG_FLTR_MODE_ED (1 << CFG_AWG_FLTR_MODE_SHIFT) 56 #define CFG_AWG_FLTR_MODE_HD (2 << CFG_AWG_FLTR_MODE_SHIFT) 57 #define CFG_SYNC_ON_PBPR_MASK BIT(8) 58 #define CFG_PREFILTER_EN_MASK BIT(9) 59 #define CFG_PBPR_SYNC_OFF_SHIFT 16 60 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT) 61 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */ 62 63 /* Default scaling values */ 64 #define SCALE_CTRL_Y_DFLT 0x00C50256 65 #define SCALE_CTRL_CB_DFLT 0x00DB0249 66 #define SCALE_CTRL_CR_DFLT 0x00DB0249 67 68 /* Video DACs control */ 69 #define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1) 70 71 /* Upsampler values for the alternative 2X Filter */ 72 #define SAMPLER_COEF_NB 8 73 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000 74 static u32 coef_y_alt_2x[] = { 75 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000, 76 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000 77 }; 78 79 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004 80 static u32 coef_c_alt_2x[] = { 81 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000, 82 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000 83 }; 84 85 /* Upsampler values for the 4X Filter */ 86 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005 87 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004 88 static u32 coef_yc_4x[] = { 89 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24, 90 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D 91 }; 92 93 /* AWG instructions for some video modes */ 94 #define AWG_MAX_INST 64 95 96 /* 720p@50 */ 97 static u32 AWGi_720p_50[] = { 98 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 99 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 100 0x00000D8E, 0x00000104, 0x00001804, 0x00000971, 101 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5, 102 0x00000104, 0x00001AE8 103 }; 104 105 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50) 106 107 /* 720p@60 */ 108 static u32 AWGi_720p_60[] = { 109 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 110 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 111 0x00000C44, 0x00000104, 0x00001804, 0x00000971, 112 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10, 113 0x00000104, 0x00001AE8 114 }; 115 116 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60) 117 118 /* 1080p@30 */ 119 static u32 AWGi_1080p_30[] = { 120 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 121 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 122 0x00000C2A, 0x00000104, 0x00001804, 0x00000971, 123 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF, 124 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B, 125 0x00001C52 126 }; 127 128 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30) 129 130 /* 1080p@25 */ 131 static u32 AWGi_1080p_25[] = { 132 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 133 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 134 0x00000DE2, 0x00000104, 0x00001804, 0x00000971, 135 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51, 136 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B, 137 0x00001C52 138 }; 139 140 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25) 141 142 /* 1080p@24 */ 143 static u32 AWGi_1080p_24[] = { 144 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 145 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 146 0x00000E50, 0x00000104, 0x00001804, 0x00000971, 147 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76, 148 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B, 149 0x00001C52 150 }; 151 152 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24) 153 154 /* 720x480p@60 */ 155 static u32 AWGi_720x480p_60[] = { 156 0x00000904, 0x00000F18, 0x0000013B, 0x00001805, 157 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06 158 }; 159 160 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60) 161 162 /* Video mode category */ 163 enum sti_hda_vid_cat { 164 VID_SD, 165 VID_ED, 166 VID_HD_74M, 167 VID_HD_148M 168 }; 169 170 struct sti_hda_video_config { 171 struct drm_display_mode mode; 172 u32 *awg_instr; 173 int nb_instr; 174 enum sti_hda_vid_cat vid_cat; 175 }; 176 177 /* HD analog supported modes 178 * Interlaced modes may be added when supported by the whole display chain 179 */ 180 static const struct sti_hda_video_config hda_supported_modes[] = { 181 /* 1080p30 74.250Mhz */ 182 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 183 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 185 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 186 /* 1080p30 74.176Mhz */ 187 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008, 188 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 190 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 191 /* 1080p24 74.250Mhz */ 192 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 193 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 195 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 196 /* 1080p24 74.176Mhz */ 197 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558, 198 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 200 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 201 /* 1080p25 74.250Mhz */ 202 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 203 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 205 AWGi_1080p_25, NN_1080p_25, VID_HD_74M}, 206 /* 720p60 74.250Mhz */ 207 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 208 1430, 1650, 0, 720, 725, 730, 750, 0, 209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 210 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 211 /* 720p60 74.176Mhz */ 212 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390, 213 1430, 1650, 0, 720, 725, 730, 750, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 215 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 216 /* 720p50 74.250Mhz */ 217 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 218 1760, 1980, 0, 720, 725, 730, 750, 0, 219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 220 AWGi_720p_50, NN_720p_50, VID_HD_74M}, 221 /* 720x480p60 27.027Mhz */ 222 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736, 223 798, 858, 0, 480, 489, 495, 525, 0, 224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 225 AWGi_720x480p_60, NN_720x480p_60, VID_ED}, 226 /* 720x480p60 27.000Mhz */ 227 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 228 798, 858, 0, 480, 489, 495, 525, 0, 229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 230 AWGi_720x480p_60, NN_720x480p_60, VID_ED} 231 }; 232 233 /** 234 * STI hd analog structure 235 * 236 * @dev: driver device 237 * @drm_dev: pointer to drm device 238 * @mode: current display mode selected 239 * @regs: HD analog register 240 * @video_dacs_ctrl: video DACS control register 241 * @enabled: true if HD analog is enabled else false 242 */ 243 struct sti_hda { 244 struct device dev; 245 struct drm_device *drm_dev; 246 struct drm_display_mode mode; 247 void __iomem *regs; 248 void __iomem *video_dacs_ctrl; 249 struct clk *clk_pix; 250 struct clk *clk_hddac; 251 bool enabled; 252 }; 253 254 struct sti_hda_connector { 255 struct drm_connector drm_connector; 256 struct drm_encoder *encoder; 257 struct sti_hda *hda; 258 }; 259 260 #define to_sti_hda_connector(x) \ 261 container_of(x, struct sti_hda_connector, drm_connector) 262 263 static u32 hda_read(struct sti_hda *hda, int offset) 264 { 265 return readl(hda->regs + offset); 266 } 267 268 static void hda_write(struct sti_hda *hda, u32 val, int offset) 269 { 270 writel(val, hda->regs + offset); 271 } 272 273 /** 274 * Search for a video mode in the supported modes table 275 * 276 * @mode: mode being searched 277 * @idx: index of the found mode 278 * 279 * Return true if mode is found 280 */ 281 static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx) 282 { 283 unsigned int i; 284 285 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) 286 if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) { 287 *idx = i; 288 return true; 289 } 290 return false; 291 } 292 293 /** 294 * Enable the HD DACS 295 * 296 * @hda: pointer to HD analog structure 297 * @enable: true if HD DACS need to be enabled, else false 298 */ 299 static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable) 300 { 301 if (hda->video_dacs_ctrl) { 302 u32 val; 303 304 val = readl(hda->video_dacs_ctrl); 305 if (enable) 306 val &= ~DAC_CFG_HD_HZUVW_OFF_MASK; 307 else 308 val |= DAC_CFG_HD_HZUVW_OFF_MASK; 309 310 writel(val, hda->video_dacs_ctrl); 311 } 312 } 313 314 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 315 readl(hda->regs + reg)) 316 317 static void hda_dbg_cfg(struct seq_file *s, int val) 318 { 319 seq_puts(s, "\tAWG "); 320 seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled"); 321 } 322 323 static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg) 324 { 325 unsigned int i; 326 327 seq_puts(s, "\n\n HDA AWG microcode:"); 328 for (i = 0; i < AWG_MAX_INST; i++) { 329 if (i % 8 == 0) 330 seq_printf(s, "\n %04X:", i); 331 seq_printf(s, " %04X", readl(reg + i * 4)); 332 } 333 } 334 335 static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg) 336 { 337 u32 val = readl(reg); 338 339 seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); 340 seq_puts(s, "\tHD DACs "); 341 seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled"); 342 } 343 344 static int hda_dbg_show(struct seq_file *s, void *data) 345 { 346 struct drm_info_node *node = s->private; 347 struct sti_hda *hda = (struct sti_hda *)node->info_ent->data; 348 349 seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs); 350 DBGFS_DUMP(HDA_ANA_CFG); 351 hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG)); 352 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y); 353 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB); 354 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR); 355 DBGFS_DUMP(HDA_ANA_ANC_CTRL); 356 DBGFS_DUMP(HDA_ANA_SRC_Y_CFG); 357 DBGFS_DUMP(HDA_ANA_SRC_C_CFG); 358 hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI); 359 if (hda->video_dacs_ctrl) 360 hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl); 361 seq_putc(s, '\n'); 362 return 0; 363 } 364 365 static struct drm_info_list hda_debugfs_files[] = { 366 { "hda", hda_dbg_show, 0, NULL }, 367 }; 368 369 static int hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor) 370 { 371 unsigned int i; 372 373 for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++) 374 hda_debugfs_files[i].data = hda; 375 376 return drm_debugfs_create_files(hda_debugfs_files, 377 ARRAY_SIZE(hda_debugfs_files), 378 minor->debugfs_root, minor); 379 } 380 381 /** 382 * Configure AWG, writing instructions 383 * 384 * @hda: pointer to HD analog structure 385 * @awg_instr: pointer to AWG instructions table 386 * @nb: nb of AWG instructions 387 */ 388 static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb) 389 { 390 unsigned int i; 391 392 DRM_DEBUG_DRIVER("\n"); 393 394 for (i = 0; i < nb; i++) 395 hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4); 396 for (i = nb; i < AWG_MAX_INST; i++) 397 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4); 398 } 399 400 static void sti_hda_disable(struct drm_bridge *bridge) 401 { 402 struct sti_hda *hda = bridge->driver_private; 403 u32 val; 404 405 if (!hda->enabled) 406 return; 407 408 DRM_DEBUG_DRIVER("\n"); 409 410 /* Disable HD DAC and AWG */ 411 val = hda_read(hda, HDA_ANA_CFG); 412 val &= ~CFG_AWG_ASYNC_EN; 413 hda_write(hda, val, HDA_ANA_CFG); 414 hda_write(hda, 0, HDA_ANA_ANC_CTRL); 415 416 hda_enable_hd_dacs(hda, false); 417 418 /* Disable/unprepare hda clock */ 419 clk_disable_unprepare(hda->clk_hddac); 420 clk_disable_unprepare(hda->clk_pix); 421 422 hda->enabled = false; 423 } 424 425 static void sti_hda_pre_enable(struct drm_bridge *bridge) 426 { 427 struct sti_hda *hda = bridge->driver_private; 428 u32 val, i, mode_idx; 429 u32 src_filter_y, src_filter_c; 430 u32 *coef_y, *coef_c; 431 u32 filter_mode; 432 433 DRM_DEBUG_DRIVER("\n"); 434 435 if (hda->enabled) 436 return; 437 438 /* Prepare/enable clocks */ 439 if (clk_prepare_enable(hda->clk_pix)) 440 DRM_ERROR("Failed to prepare/enable hda_pix clk\n"); 441 if (clk_prepare_enable(hda->clk_hddac)) 442 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n"); 443 444 if (!hda_get_mode_idx(hda->mode, &mode_idx)) { 445 DRM_ERROR("Undefined mode\n"); 446 return; 447 } 448 449 switch (hda_supported_modes[mode_idx].vid_cat) { 450 case VID_HD_148M: 451 DRM_ERROR("Beyond HD analog capabilities\n"); 452 return; 453 case VID_HD_74M: 454 /* HD use alternate 2x filter */ 455 filter_mode = CFG_AWG_FLTR_MODE_HD; 456 src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X; 457 src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X; 458 coef_y = coef_y_alt_2x; 459 coef_c = coef_c_alt_2x; 460 break; 461 case VID_ED: 462 /* ED uses 4x filter */ 463 filter_mode = CFG_AWG_FLTR_MODE_ED; 464 src_filter_y = HDA_ANA_SRC_Y_CFG_4X; 465 src_filter_c = HDA_ANA_SRC_C_CFG_4X; 466 coef_y = coef_yc_4x; 467 coef_c = coef_yc_4x; 468 break; 469 case VID_SD: 470 DRM_ERROR("Not supported\n"); 471 return; 472 default: 473 DRM_ERROR("Undefined resolution\n"); 474 return; 475 } 476 DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx); 477 478 /* Enable HD Video DACs */ 479 hda_enable_hd_dacs(hda, true); 480 481 /* Configure scaler */ 482 hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y); 483 hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB); 484 hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR); 485 486 /* Configure sampler */ 487 hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG); 488 hda_write(hda, src_filter_c, HDA_ANA_SRC_C_CFG); 489 for (i = 0; i < SAMPLER_COEF_NB; i++) { 490 hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4); 491 hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4); 492 } 493 494 /* Configure main HDFormatter */ 495 val = 0; 496 val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ? 497 0 : CFG_AWG_ASYNC_VSYNC_MTD; 498 val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT); 499 val |= filter_mode; 500 hda_write(hda, val, HDA_ANA_CFG); 501 502 /* Configure AWG */ 503 sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr, 504 hda_supported_modes[mode_idx].nb_instr); 505 506 /* Enable AWG */ 507 val = hda_read(hda, HDA_ANA_CFG); 508 val |= CFG_AWG_ASYNC_EN; 509 hda_write(hda, val, HDA_ANA_CFG); 510 511 hda->enabled = true; 512 } 513 514 static void sti_hda_set_mode(struct drm_bridge *bridge, 515 const struct drm_display_mode *mode, 516 const struct drm_display_mode *adjusted_mode) 517 { 518 struct sti_hda *hda = bridge->driver_private; 519 u32 mode_idx; 520 int hddac_rate; 521 int ret; 522 523 DRM_DEBUG_DRIVER("\n"); 524 525 memcpy(&hda->mode, mode, sizeof(struct drm_display_mode)); 526 527 if (!hda_get_mode_idx(hda->mode, &mode_idx)) { 528 DRM_ERROR("Undefined mode\n"); 529 return; 530 } 531 532 switch (hda_supported_modes[mode_idx].vid_cat) { 533 case VID_HD_74M: 534 /* HD use alternate 2x filter */ 535 hddac_rate = mode->clock * 1000 * 2; 536 break; 537 case VID_ED: 538 /* ED uses 4x filter */ 539 hddac_rate = mode->clock * 1000 * 4; 540 break; 541 default: 542 DRM_ERROR("Undefined mode\n"); 543 return; 544 } 545 546 /* HD DAC = 148.5Mhz or 108 Mhz */ 547 ret = clk_set_rate(hda->clk_hddac, hddac_rate); 548 if (ret < 0) 549 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n", 550 hddac_rate); 551 552 /* HDformatter clock = compositor clock */ 553 ret = clk_set_rate(hda->clk_pix, mode->clock * 1000); 554 if (ret < 0) 555 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n", 556 mode->clock * 1000); 557 } 558 559 static void sti_hda_bridge_nope(struct drm_bridge *bridge) 560 { 561 /* do nothing */ 562 } 563 564 static const struct drm_bridge_funcs sti_hda_bridge_funcs = { 565 .pre_enable = sti_hda_pre_enable, 566 .enable = sti_hda_bridge_nope, 567 .disable = sti_hda_disable, 568 .post_disable = sti_hda_bridge_nope, 569 .mode_set = sti_hda_set_mode, 570 }; 571 572 static int sti_hda_connector_get_modes(struct drm_connector *connector) 573 { 574 unsigned int i; 575 int count = 0; 576 struct sti_hda_connector *hda_connector 577 = to_sti_hda_connector(connector); 578 struct sti_hda *hda = hda_connector->hda; 579 580 DRM_DEBUG_DRIVER("\n"); 581 582 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) { 583 struct drm_display_mode *mode = 584 drm_mode_duplicate(hda->drm_dev, 585 &hda_supported_modes[i].mode); 586 if (!mode) 587 continue; 588 mode->vrefresh = drm_mode_vrefresh(mode); 589 590 /* the first mode is the preferred mode */ 591 if (i == 0) 592 mode->type |= DRM_MODE_TYPE_PREFERRED; 593 594 drm_mode_probed_add(connector, mode); 595 count++; 596 } 597 598 return count; 599 } 600 601 #define CLK_TOLERANCE_HZ 50 602 603 static int sti_hda_connector_mode_valid(struct drm_connector *connector, 604 struct drm_display_mode *mode) 605 { 606 int target = mode->clock * 1000; 607 int target_min = target - CLK_TOLERANCE_HZ; 608 int target_max = target + CLK_TOLERANCE_HZ; 609 int result; 610 int idx; 611 struct sti_hda_connector *hda_connector 612 = to_sti_hda_connector(connector); 613 struct sti_hda *hda = hda_connector->hda; 614 615 if (!hda_get_mode_idx(*mode, &idx)) { 616 return MODE_BAD; 617 } else { 618 result = clk_round_rate(hda->clk_pix, target); 619 620 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", 621 target, result); 622 623 if ((result < target_min) || (result > target_max)) { 624 DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n", 625 target); 626 return MODE_BAD; 627 } 628 } 629 630 return MODE_OK; 631 } 632 633 static const 634 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = { 635 .get_modes = sti_hda_connector_get_modes, 636 .mode_valid = sti_hda_connector_mode_valid, 637 }; 638 639 static int sti_hda_late_register(struct drm_connector *connector) 640 { 641 struct sti_hda_connector *hda_connector 642 = to_sti_hda_connector(connector); 643 struct sti_hda *hda = hda_connector->hda; 644 645 if (hda_debugfs_init(hda, hda->drm_dev->primary)) { 646 DRM_ERROR("HDA debugfs setup failed\n"); 647 return -EINVAL; 648 } 649 650 return 0; 651 } 652 653 static const struct drm_connector_funcs sti_hda_connector_funcs = { 654 .fill_modes = drm_helper_probe_single_connector_modes, 655 .destroy = drm_connector_cleanup, 656 .reset = drm_atomic_helper_connector_reset, 657 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 658 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 659 .late_register = sti_hda_late_register, 660 }; 661 662 static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev) 663 { 664 struct drm_encoder *encoder; 665 666 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 667 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC) 668 return encoder; 669 } 670 671 return NULL; 672 } 673 674 static int sti_hda_bind(struct device *dev, struct device *master, void *data) 675 { 676 struct sti_hda *hda = dev_get_drvdata(dev); 677 struct drm_device *drm_dev = data; 678 struct drm_encoder *encoder; 679 struct sti_hda_connector *connector; 680 struct drm_connector *drm_connector; 681 struct drm_bridge *bridge; 682 int err; 683 684 /* Set the drm device handle */ 685 hda->drm_dev = drm_dev; 686 687 encoder = sti_hda_find_encoder(drm_dev); 688 if (!encoder) 689 return -ENOMEM; 690 691 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); 692 if (!connector) 693 return -ENOMEM; 694 695 connector->hda = hda; 696 697 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); 698 if (!bridge) 699 return -ENOMEM; 700 701 bridge->driver_private = hda; 702 bridge->funcs = &sti_hda_bridge_funcs; 703 drm_bridge_attach(encoder, bridge, NULL); 704 705 connector->encoder = encoder; 706 707 drm_connector = (struct drm_connector *)connector; 708 709 drm_connector->polled = DRM_CONNECTOR_POLL_HPD; 710 711 drm_connector_init(drm_dev, drm_connector, 712 &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component); 713 drm_connector_helper_add(drm_connector, 714 &sti_hda_connector_helper_funcs); 715 716 err = drm_connector_attach_encoder(drm_connector, encoder); 717 if (err) { 718 DRM_ERROR("Failed to attach a connector to a encoder\n"); 719 goto err_sysfs; 720 } 721 722 /* force to disable hd dacs at startup */ 723 hda_enable_hd_dacs(hda, false); 724 725 return 0; 726 727 err_sysfs: 728 return -EINVAL; 729 } 730 731 static void sti_hda_unbind(struct device *dev, 732 struct device *master, void *data) 733 { 734 } 735 736 static const struct component_ops sti_hda_ops = { 737 .bind = sti_hda_bind, 738 .unbind = sti_hda_unbind, 739 }; 740 741 static int sti_hda_probe(struct platform_device *pdev) 742 { 743 struct device *dev = &pdev->dev; 744 struct sti_hda *hda; 745 struct resource *res; 746 747 DRM_INFO("%s\n", __func__); 748 749 hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL); 750 if (!hda) 751 return -ENOMEM; 752 753 hda->dev = pdev->dev; 754 755 /* Get resources */ 756 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg"); 757 if (!res) { 758 DRM_ERROR("Invalid hda resource\n"); 759 return -ENOMEM; 760 } 761 hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); 762 if (!hda->regs) 763 return -ENOMEM; 764 765 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 766 "video-dacs-ctrl"); 767 if (res) { 768 hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start, 769 resource_size(res)); 770 if (!hda->video_dacs_ctrl) 771 return -ENOMEM; 772 } else { 773 /* If no existing video-dacs-ctrl resource continue the probe */ 774 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n"); 775 hda->video_dacs_ctrl = NULL; 776 } 777 778 /* Get clock resources */ 779 hda->clk_pix = devm_clk_get(dev, "pix"); 780 if (IS_ERR(hda->clk_pix)) { 781 DRM_ERROR("Cannot get hda_pix clock\n"); 782 return PTR_ERR(hda->clk_pix); 783 } 784 785 hda->clk_hddac = devm_clk_get(dev, "hddac"); 786 if (IS_ERR(hda->clk_hddac)) { 787 DRM_ERROR("Cannot get hda_hddac clock\n"); 788 return PTR_ERR(hda->clk_hddac); 789 } 790 791 platform_set_drvdata(pdev, hda); 792 793 return component_add(&pdev->dev, &sti_hda_ops); 794 } 795 796 static int sti_hda_remove(struct platform_device *pdev) 797 { 798 component_del(&pdev->dev, &sti_hda_ops); 799 return 0; 800 } 801 802 static const struct of_device_id hda_of_match[] = { 803 { .compatible = "st,stih416-hda", }, 804 { .compatible = "st,stih407-hda", }, 805 { /* end node */ } 806 }; 807 MODULE_DEVICE_TABLE(of, hda_of_match); 808 809 struct platform_driver sti_hda_driver = { 810 .driver = { 811 .name = "sti-hda", 812 .owner = THIS_MODULE, 813 .of_match_table = hda_of_match, 814 }, 815 .probe = sti_hda_probe, 816 .remove = sti_hda_remove, 817 }; 818 819 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 820 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 821 MODULE_LICENSE("GPL"); 822