1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * Fabien Dessenne <fabien.dessenne@st.com> 6 * for STMicroelectronics. 7 */ 8 9 #include <linux/dma-mapping.h> 10 #include <linux/seq_file.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_fb_cma_helper.h> 15 #include <drm/drm_fourcc.h> 16 #include <drm/drm_framebuffer.h> 17 #include <drm/drm_gem_cma_helper.h> 18 19 #include "sti_compositor.h" 20 #include "sti_gdp.h" 21 #include "sti_plane.h" 22 #include "sti_vtg.h" 23 24 #define ALPHASWITCH BIT(6) 25 #define ENA_COLOR_FILL BIT(8) 26 #define BIGNOTLITTLE BIT(23) 27 #define WAIT_NEXT_VSYNC BIT(31) 28 29 /* GDP color formats */ 30 #define GDP_RGB565 0x00 31 #define GDP_RGB888 0x01 32 #define GDP_RGB888_32 0x02 33 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 34 #define GDP_ARGB8565 0x04 35 #define GDP_ARGB8888 0x05 36 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 37 #define GDP_ARGB1555 0x06 38 #define GDP_ARGB4444 0x07 39 40 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 41 42 static struct gdp_format_to_str { 43 int format; 44 char name[20]; 45 } gdp_format_to_str[] = { 46 GDP2STR(RGB565), 47 GDP2STR(RGB888), 48 GDP2STR(RGB888_32), 49 GDP2STR(XBGR8888), 50 GDP2STR(ARGB8565), 51 GDP2STR(ARGB8888), 52 GDP2STR(ABGR8888), 53 GDP2STR(ARGB1555), 54 GDP2STR(ARGB4444) 55 }; 56 57 #define GAM_GDP_CTL_OFFSET 0x00 58 #define GAM_GDP_AGC_OFFSET 0x04 59 #define GAM_GDP_VPO_OFFSET 0x0C 60 #define GAM_GDP_VPS_OFFSET 0x10 61 #define GAM_GDP_PML_OFFSET 0x14 62 #define GAM_GDP_PMP_OFFSET 0x18 63 #define GAM_GDP_SIZE_OFFSET 0x1C 64 #define GAM_GDP_NVN_OFFSET 0x24 65 #define GAM_GDP_KEY1_OFFSET 0x28 66 #define GAM_GDP_KEY2_OFFSET 0x2C 67 #define GAM_GDP_PPT_OFFSET 0x34 68 #define GAM_GDP_CML_OFFSET 0x3C 69 #define GAM_GDP_MST_OFFSET 0x68 70 71 #define GAM_GDP_ALPHARANGE_255 BIT(5) 72 #define GAM_GDP_AGC_FULL_RANGE 0x00808080 73 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 74 75 #define GAM_GDP_SIZE_MAX_WIDTH 3840 76 #define GAM_GDP_SIZE_MAX_HEIGHT 2160 77 78 #define GDP_NODE_NB_BANK 2 79 #define GDP_NODE_PER_FIELD 2 80 81 struct sti_gdp_node { 82 u32 gam_gdp_ctl; 83 u32 gam_gdp_agc; 84 u32 reserved1; 85 u32 gam_gdp_vpo; 86 u32 gam_gdp_vps; 87 u32 gam_gdp_pml; 88 u32 gam_gdp_pmp; 89 u32 gam_gdp_size; 90 u32 reserved2; 91 u32 gam_gdp_nvn; 92 u32 gam_gdp_key1; 93 u32 gam_gdp_key2; 94 u32 reserved3; 95 u32 gam_gdp_ppt; 96 u32 reserved4; 97 u32 gam_gdp_cml; 98 }; 99 100 struct sti_gdp_node_list { 101 struct sti_gdp_node *top_field; 102 dma_addr_t top_field_paddr; 103 struct sti_gdp_node *btm_field; 104 dma_addr_t btm_field_paddr; 105 }; 106 107 /* 108 * STI GDP structure 109 * 110 * @sti_plane: sti_plane structure 111 * @dev: driver device 112 * @regs: gdp registers 113 * @clk_pix: pixel clock for the current gdp 114 * @clk_main_parent: gdp parent clock if main path used 115 * @clk_aux_parent: gdp parent clock if aux path used 116 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 117 * @is_curr_top: true if the current node processed is the top field 118 * @node_list: array of node list 119 * @vtg: registered vtg 120 */ 121 struct sti_gdp { 122 struct sti_plane plane; 123 struct device *dev; 124 void __iomem *regs; 125 struct clk *clk_pix; 126 struct clk *clk_main_parent; 127 struct clk *clk_aux_parent; 128 struct notifier_block vtg_field_nb; 129 bool is_curr_top; 130 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 131 struct sti_vtg *vtg; 132 }; 133 134 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 135 136 static const uint32_t gdp_supported_formats[] = { 137 DRM_FORMAT_XRGB8888, 138 DRM_FORMAT_XBGR8888, 139 DRM_FORMAT_ARGB8888, 140 DRM_FORMAT_ABGR8888, 141 DRM_FORMAT_ARGB4444, 142 DRM_FORMAT_ARGB1555, 143 DRM_FORMAT_RGB565, 144 DRM_FORMAT_RGB888, 145 }; 146 147 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 148 readl(gdp->regs + reg ## _OFFSET)) 149 150 static void gdp_dbg_ctl(struct seq_file *s, int val) 151 { 152 int i; 153 154 seq_puts(s, "\tColor:"); 155 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 156 if (gdp_format_to_str[i].format == (val & 0x1F)) { 157 seq_puts(s, gdp_format_to_str[i].name); 158 break; 159 } 160 } 161 if (i == ARRAY_SIZE(gdp_format_to_str)) 162 seq_puts(s, "<UNKNOWN>"); 163 164 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 165 } 166 167 static void gdp_dbg_vpo(struct seq_file *s, int val) 168 { 169 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 170 } 171 172 static void gdp_dbg_vps(struct seq_file *s, int val) 173 { 174 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 175 } 176 177 static void gdp_dbg_size(struct seq_file *s, int val) 178 { 179 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 180 } 181 182 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 183 { 184 void *base = NULL; 185 unsigned int i; 186 187 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 188 if (gdp->node_list[i].top_field_paddr == val) { 189 base = gdp->node_list[i].top_field; 190 break; 191 } 192 if (gdp->node_list[i].btm_field_paddr == val) { 193 base = gdp->node_list[i].btm_field; 194 break; 195 } 196 } 197 198 if (base) 199 seq_printf(s, "\tVirt @: %p", base); 200 } 201 202 static void gdp_dbg_ppt(struct seq_file *s, int val) 203 { 204 if (val & GAM_GDP_PPT_IGNORE) 205 seq_puts(s, "\tNot displayed on mixer!"); 206 } 207 208 static void gdp_dbg_mst(struct seq_file *s, int val) 209 { 210 if (val & 1) 211 seq_puts(s, "\tBUFFER UNDERFLOW!"); 212 } 213 214 static int gdp_dbg_show(struct seq_file *s, void *data) 215 { 216 struct drm_info_node *node = s->private; 217 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 218 struct drm_plane *drm_plane = &gdp->plane.drm_plane; 219 struct drm_crtc *crtc; 220 221 drm_modeset_lock(&drm_plane->mutex, NULL); 222 crtc = drm_plane->state->crtc; 223 drm_modeset_unlock(&drm_plane->mutex); 224 225 seq_printf(s, "%s: (vaddr = 0x%p)", 226 sti_plane_to_str(&gdp->plane), gdp->regs); 227 228 DBGFS_DUMP(GAM_GDP_CTL); 229 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 230 DBGFS_DUMP(GAM_GDP_AGC); 231 DBGFS_DUMP(GAM_GDP_VPO); 232 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 233 DBGFS_DUMP(GAM_GDP_VPS); 234 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 235 DBGFS_DUMP(GAM_GDP_PML); 236 DBGFS_DUMP(GAM_GDP_PMP); 237 DBGFS_DUMP(GAM_GDP_SIZE); 238 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 239 DBGFS_DUMP(GAM_GDP_NVN); 240 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 241 DBGFS_DUMP(GAM_GDP_KEY1); 242 DBGFS_DUMP(GAM_GDP_KEY2); 243 DBGFS_DUMP(GAM_GDP_PPT); 244 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 245 DBGFS_DUMP(GAM_GDP_CML); 246 DBGFS_DUMP(GAM_GDP_MST); 247 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 248 249 seq_puts(s, "\n\n"); 250 if (!crtc) 251 seq_puts(s, " Not connected to any DRM CRTC\n"); 252 else 253 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 254 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 255 256 return 0; 257 } 258 259 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 260 { 261 seq_printf(s, "\t@:0x%p", node); 262 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 263 gdp_dbg_ctl(s, node->gam_gdp_ctl); 264 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 265 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 266 gdp_dbg_vpo(s, node->gam_gdp_vpo); 267 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 268 gdp_dbg_vps(s, node->gam_gdp_vps); 269 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 270 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 271 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 272 gdp_dbg_size(s, node->gam_gdp_size); 273 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 274 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 275 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 276 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 277 gdp_dbg_ppt(s, node->gam_gdp_ppt); 278 seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml); 279 } 280 281 static int gdp_node_dbg_show(struct seq_file *s, void *arg) 282 { 283 struct drm_info_node *node = s->private; 284 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 285 unsigned int b; 286 287 for (b = 0; b < GDP_NODE_NB_BANK; b++) { 288 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 289 gdp_node_dump_node(s, gdp->node_list[b].top_field); 290 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 291 gdp_node_dump_node(s, gdp->node_list[b].btm_field); 292 } 293 294 return 0; 295 } 296 297 static struct drm_info_list gdp0_debugfs_files[] = { 298 { "gdp0", gdp_dbg_show, 0, NULL }, 299 { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 300 }; 301 302 static struct drm_info_list gdp1_debugfs_files[] = { 303 { "gdp1", gdp_dbg_show, 0, NULL }, 304 { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 305 }; 306 307 static struct drm_info_list gdp2_debugfs_files[] = { 308 { "gdp2", gdp_dbg_show, 0, NULL }, 309 { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 310 }; 311 312 static struct drm_info_list gdp3_debugfs_files[] = { 313 { "gdp3", gdp_dbg_show, 0, NULL }, 314 { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 315 }; 316 317 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 318 { 319 unsigned int i; 320 struct drm_info_list *gdp_debugfs_files; 321 int nb_files; 322 323 switch (gdp->plane.desc) { 324 case STI_GDP_0: 325 gdp_debugfs_files = gdp0_debugfs_files; 326 nb_files = ARRAY_SIZE(gdp0_debugfs_files); 327 break; 328 case STI_GDP_1: 329 gdp_debugfs_files = gdp1_debugfs_files; 330 nb_files = ARRAY_SIZE(gdp1_debugfs_files); 331 break; 332 case STI_GDP_2: 333 gdp_debugfs_files = gdp2_debugfs_files; 334 nb_files = ARRAY_SIZE(gdp2_debugfs_files); 335 break; 336 case STI_GDP_3: 337 gdp_debugfs_files = gdp3_debugfs_files; 338 nb_files = ARRAY_SIZE(gdp3_debugfs_files); 339 break; 340 default: 341 return -EINVAL; 342 } 343 344 for (i = 0; i < nb_files; i++) 345 gdp_debugfs_files[i].data = gdp; 346 347 drm_debugfs_create_files(gdp_debugfs_files, 348 nb_files, 349 minor->debugfs_root, minor); 350 return 0; 351 } 352 353 static int sti_gdp_fourcc2format(int fourcc) 354 { 355 switch (fourcc) { 356 case DRM_FORMAT_XRGB8888: 357 return GDP_RGB888_32; 358 case DRM_FORMAT_XBGR8888: 359 return GDP_XBGR8888; 360 case DRM_FORMAT_ARGB8888: 361 return GDP_ARGB8888; 362 case DRM_FORMAT_ABGR8888: 363 return GDP_ABGR8888; 364 case DRM_FORMAT_ARGB4444: 365 return GDP_ARGB4444; 366 case DRM_FORMAT_ARGB1555: 367 return GDP_ARGB1555; 368 case DRM_FORMAT_RGB565: 369 return GDP_RGB565; 370 case DRM_FORMAT_RGB888: 371 return GDP_RGB888; 372 } 373 return -1; 374 } 375 376 static int sti_gdp_get_alpharange(int format) 377 { 378 switch (format) { 379 case GDP_ARGB8565: 380 case GDP_ARGB8888: 381 case GDP_ABGR8888: 382 return GAM_GDP_ALPHARANGE_255; 383 } 384 return 0; 385 } 386 387 /** 388 * sti_gdp_get_free_nodes 389 * @gdp: gdp pointer 390 * 391 * Look for a GDP node list that is not currently read by the HW. 392 * 393 * RETURNS: 394 * Pointer to the free GDP node list 395 */ 396 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 397 { 398 int hw_nvn; 399 unsigned int i; 400 401 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 402 if (!hw_nvn) 403 goto end; 404 405 for (i = 0; i < GDP_NODE_NB_BANK; i++) 406 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 407 (hw_nvn != gdp->node_list[i].top_field_paddr)) 408 return &gdp->node_list[i]; 409 410 /* in hazardous cases restart with the first node */ 411 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 412 sti_plane_to_str(&gdp->plane), hw_nvn); 413 414 end: 415 return &gdp->node_list[0]; 416 } 417 418 /** 419 * sti_gdp_get_current_nodes 420 * @gdp: gdp pointer 421 * 422 * Look for GDP nodes that are currently read by the HW. 423 * 424 * RETURNS: 425 * Pointer to the current GDP node list 426 */ 427 static 428 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 429 { 430 int hw_nvn; 431 unsigned int i; 432 433 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 434 if (!hw_nvn) 435 goto end; 436 437 for (i = 0; i < GDP_NODE_NB_BANK; i++) 438 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 439 (hw_nvn == gdp->node_list[i].top_field_paddr)) 440 return &gdp->node_list[i]; 441 442 end: 443 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 444 hw_nvn, sti_plane_to_str(&gdp->plane)); 445 446 return NULL; 447 } 448 449 /** 450 * sti_gdp_disable 451 * @gdp: gdp pointer 452 * 453 * Disable a GDP. 454 */ 455 static void sti_gdp_disable(struct sti_gdp *gdp) 456 { 457 unsigned int i; 458 459 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 460 461 /* Set the nodes as 'to be ignored on mixer' */ 462 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 463 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 464 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 465 } 466 467 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 468 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 469 470 if (gdp->clk_pix) 471 clk_disable_unprepare(gdp->clk_pix); 472 473 gdp->plane.status = STI_PLANE_DISABLED; 474 gdp->vtg = NULL; 475 } 476 477 /** 478 * sti_gdp_field_cb 479 * @nb: notifier block 480 * @event: event message 481 * @data: private data 482 * 483 * Handle VTG top field and bottom field event. 484 * 485 * RETURNS: 486 * 0 on success. 487 */ 488 static int sti_gdp_field_cb(struct notifier_block *nb, 489 unsigned long event, void *data) 490 { 491 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 492 493 if (gdp->plane.status == STI_PLANE_FLUSHING) { 494 /* disable need to be synchronize on vsync event */ 495 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 496 sti_plane_to_str(&gdp->plane)); 497 498 sti_gdp_disable(gdp); 499 } 500 501 switch (event) { 502 case VTG_TOP_FIELD_EVENT: 503 gdp->is_curr_top = true; 504 break; 505 case VTG_BOTTOM_FIELD_EVENT: 506 gdp->is_curr_top = false; 507 break; 508 default: 509 DRM_ERROR("unsupported event: %lu\n", event); 510 break; 511 } 512 513 return 0; 514 } 515 516 static void sti_gdp_init(struct sti_gdp *gdp) 517 { 518 struct device_node *np = gdp->dev->of_node; 519 dma_addr_t dma_addr; 520 void *base; 521 unsigned int i, size; 522 523 /* Allocate all the nodes within a single memory page */ 524 size = sizeof(struct sti_gdp_node) * 525 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 526 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL); 527 528 if (!base) { 529 DRM_ERROR("Failed to allocate memory for GDP node\n"); 530 return; 531 } 532 memset(base, 0, size); 533 534 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 535 if (dma_addr & 0xF) { 536 DRM_ERROR("Mem alignment failed\n"); 537 return; 538 } 539 gdp->node_list[i].top_field = base; 540 gdp->node_list[i].top_field_paddr = dma_addr; 541 542 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 543 base += sizeof(struct sti_gdp_node); 544 dma_addr += sizeof(struct sti_gdp_node); 545 546 if (dma_addr & 0xF) { 547 DRM_ERROR("Mem alignment failed\n"); 548 return; 549 } 550 gdp->node_list[i].btm_field = base; 551 gdp->node_list[i].btm_field_paddr = dma_addr; 552 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 553 base += sizeof(struct sti_gdp_node); 554 dma_addr += sizeof(struct sti_gdp_node); 555 } 556 557 if (of_device_is_compatible(np, "st,stih407-compositor")) { 558 /* GDP of STiH407 chip have its own pixel clock */ 559 char *clk_name; 560 561 switch (gdp->plane.desc) { 562 case STI_GDP_0: 563 clk_name = "pix_gdp1"; 564 break; 565 case STI_GDP_1: 566 clk_name = "pix_gdp2"; 567 break; 568 case STI_GDP_2: 569 clk_name = "pix_gdp3"; 570 break; 571 case STI_GDP_3: 572 clk_name = "pix_gdp4"; 573 break; 574 default: 575 DRM_ERROR("GDP id not recognized\n"); 576 return; 577 } 578 579 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 580 if (IS_ERR(gdp->clk_pix)) 581 DRM_ERROR("Cannot get %s clock\n", clk_name); 582 583 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 584 if (IS_ERR(gdp->clk_main_parent)) 585 DRM_ERROR("Cannot get main_parent clock\n"); 586 587 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 588 if (IS_ERR(gdp->clk_aux_parent)) 589 DRM_ERROR("Cannot get aux_parent clock\n"); 590 } 591 } 592 593 /** 594 * sti_gdp_get_dst 595 * @dev: device 596 * @dst: requested destination size 597 * @src: source size 598 * 599 * Return the cropped / clamped destination size 600 * 601 * RETURNS: 602 * cropped / clamped destination size 603 */ 604 static int sti_gdp_get_dst(struct device *dev, int dst, int src) 605 { 606 if (dst == src) 607 return dst; 608 609 if (dst < src) { 610 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 611 return dst; 612 } 613 614 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 615 return src; 616 } 617 618 static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 619 struct drm_atomic_state *state) 620 { 621 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 622 drm_plane); 623 struct sti_plane *plane = to_sti_plane(drm_plane); 624 struct sti_gdp *gdp = to_sti_gdp(plane); 625 struct drm_crtc *crtc = new_plane_state->crtc; 626 struct drm_framebuffer *fb = new_plane_state->fb; 627 struct drm_crtc_state *crtc_state; 628 struct sti_mixer *mixer; 629 struct drm_display_mode *mode; 630 int dst_x, dst_y, dst_w, dst_h; 631 int src_x, src_y, src_w, src_h; 632 int format; 633 634 /* no need for further checks if the plane is being disabled */ 635 if (!crtc || !fb) 636 return 0; 637 638 mixer = to_sti_mixer(crtc); 639 crtc_state = drm_atomic_get_crtc_state(state, crtc); 640 mode = &crtc_state->mode; 641 dst_x = new_plane_state->crtc_x; 642 dst_y = new_plane_state->crtc_y; 643 dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x); 644 dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y); 645 /* src_x are in 16.16 format */ 646 src_x = new_plane_state->src_x >> 16; 647 src_y = new_plane_state->src_y >> 16; 648 src_w = clamp_val(new_plane_state->src_w >> 16, 0, 649 GAM_GDP_SIZE_MAX_WIDTH); 650 src_h = clamp_val(new_plane_state->src_h >> 16, 0, 651 GAM_GDP_SIZE_MAX_HEIGHT); 652 653 format = sti_gdp_fourcc2format(fb->format->format); 654 if (format == -1) { 655 DRM_ERROR("Format not supported by GDP %.4s\n", 656 (char *)&fb->format->format); 657 return -EINVAL; 658 } 659 660 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 661 DRM_ERROR("Can't get CMA GEM object for fb\n"); 662 return -EINVAL; 663 } 664 665 /* Set gdp clock */ 666 if (mode->clock && gdp->clk_pix) { 667 struct clk *clkp; 668 int rate = mode->clock * 1000; 669 int res; 670 671 /* 672 * According to the mixer used, the gdp pixel clock 673 * should have a different parent clock. 674 */ 675 if (mixer->id == STI_MIXER_MAIN) 676 clkp = gdp->clk_main_parent; 677 else 678 clkp = gdp->clk_aux_parent; 679 680 if (clkp) 681 clk_set_parent(gdp->clk_pix, clkp); 682 683 res = clk_set_rate(gdp->clk_pix, rate); 684 if (res < 0) { 685 DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 686 rate); 687 return -EINVAL; 688 } 689 } 690 691 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 692 crtc->base.id, sti_mixer_to_str(mixer), 693 drm_plane->base.id, sti_plane_to_str(plane)); 694 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 695 sti_plane_to_str(plane), 696 dst_w, dst_h, dst_x, dst_y, 697 src_w, src_h, src_x, src_y); 698 699 return 0; 700 } 701 702 static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 703 struct drm_atomic_state *state) 704 { 705 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 706 drm_plane); 707 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 708 drm_plane); 709 struct sti_plane *plane = to_sti_plane(drm_plane); 710 struct sti_gdp *gdp = to_sti_gdp(plane); 711 struct drm_crtc *crtc = newstate->crtc; 712 struct drm_framebuffer *fb = newstate->fb; 713 struct drm_display_mode *mode; 714 int dst_x, dst_y, dst_w, dst_h; 715 int src_x, src_y, src_w, src_h; 716 struct drm_gem_cma_object *cma_obj; 717 struct sti_gdp_node_list *list; 718 struct sti_gdp_node_list *curr_list; 719 struct sti_gdp_node *top_field, *btm_field; 720 u32 dma_updated_top; 721 u32 dma_updated_btm; 722 int format; 723 unsigned int bpp; 724 u32 ydo, xdo, yds, xds; 725 726 if (!crtc || !fb) 727 return; 728 729 if ((oldstate->fb == newstate->fb) && 730 (oldstate->crtc_x == newstate->crtc_x) && 731 (oldstate->crtc_y == newstate->crtc_y) && 732 (oldstate->crtc_w == newstate->crtc_w) && 733 (oldstate->crtc_h == newstate->crtc_h) && 734 (oldstate->src_x == newstate->src_x) && 735 (oldstate->src_y == newstate->src_y) && 736 (oldstate->src_w == newstate->src_w) && 737 (oldstate->src_h == newstate->src_h)) { 738 /* No change since last update, do not post cmd */ 739 DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 740 plane->status = STI_PLANE_UPDATED; 741 return; 742 } 743 744 if (!gdp->vtg) { 745 struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 746 struct sti_mixer *mixer = to_sti_mixer(crtc); 747 748 /* Register gdp callback */ 749 gdp->vtg = compo->vtg[mixer->id]; 750 sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc); 751 clk_prepare_enable(gdp->clk_pix); 752 } 753 754 mode = &crtc->mode; 755 dst_x = newstate->crtc_x; 756 dst_y = newstate->crtc_y; 757 dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x); 758 dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y); 759 /* src_x are in 16.16 format */ 760 src_x = newstate->src_x >> 16; 761 src_y = newstate->src_y >> 16; 762 src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 763 src_h = clamp_val(newstate->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 764 765 list = sti_gdp_get_free_nodes(gdp); 766 top_field = list->top_field; 767 btm_field = list->btm_field; 768 769 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 770 sti_plane_to_str(plane), top_field, btm_field); 771 772 /* build the top field */ 773 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 774 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 775 format = sti_gdp_fourcc2format(fb->format->format); 776 top_field->gam_gdp_ctl |= format; 777 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 778 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 779 780 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 781 782 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 783 (char *)&fb->format->format, 784 (unsigned long)cma_obj->paddr); 785 786 /* pixel memory location */ 787 bpp = fb->format->cpp[0]; 788 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 789 top_field->gam_gdp_pml += src_x * bpp; 790 top_field->gam_gdp_pml += src_y * fb->pitches[0]; 791 792 /* output parameters (clamped / cropped) */ 793 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 794 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 795 ydo = sti_vtg_get_line_number(*mode, dst_y); 796 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 797 xdo = sti_vtg_get_pixel_number(*mode, dst_x); 798 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 799 top_field->gam_gdp_vpo = (ydo << 16) | xdo; 800 top_field->gam_gdp_vps = (yds << 16) | xds; 801 802 /* input parameters */ 803 src_w = dst_w; 804 top_field->gam_gdp_pmp = fb->pitches[0]; 805 top_field->gam_gdp_size = src_h << 16 | src_w; 806 807 /* Same content and chained together */ 808 memcpy(btm_field, top_field, sizeof(*btm_field)); 809 top_field->gam_gdp_nvn = list->btm_field_paddr; 810 btm_field->gam_gdp_nvn = list->top_field_paddr; 811 812 /* Interlaced mode */ 813 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 814 btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 815 fb->pitches[0]; 816 817 /* Update the NVN field of the 'right' field of the current GDP node 818 * (being used by the HW) with the address of the updated ('free') top 819 * field GDP node. 820 * - In interlaced mode the 'right' field is the bottom field as we 821 * update frames starting from their top field 822 * - In progressive mode, we update both bottom and top fields which 823 * are equal nodes. 824 * At the next VSYNC, the updated node list will be used by the HW. 825 */ 826 curr_list = sti_gdp_get_current_nodes(gdp); 827 dma_updated_top = list->top_field_paddr; 828 dma_updated_btm = list->btm_field_paddr; 829 830 dev_dbg(gdp->dev, "Current NVN:0x%X\n", 831 readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 832 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 833 (unsigned long)cma_obj->paddr, 834 readl(gdp->regs + GAM_GDP_PML_OFFSET)); 835 836 if (!curr_list) { 837 /* First update or invalid node should directly write in the 838 * hw register */ 839 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n", 840 sti_plane_to_str(plane)); 841 842 writel(gdp->is_curr_top ? 843 dma_updated_btm : dma_updated_top, 844 gdp->regs + GAM_GDP_NVN_OFFSET); 845 goto end; 846 } 847 848 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 849 if (gdp->is_curr_top) { 850 /* Do not update in the middle of the frame, but 851 * postpone the update after the bottom field has 852 * been displayed */ 853 curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 854 } else { 855 /* Direct update to avoid one frame delay */ 856 writel(dma_updated_top, 857 gdp->regs + GAM_GDP_NVN_OFFSET); 858 } 859 } else { 860 /* Direct update for progressive to avoid one frame delay */ 861 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 862 } 863 864 end: 865 sti_plane_update_fps(plane, true, false); 866 867 plane->status = STI_PLANE_UPDATED; 868 } 869 870 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 871 struct drm_atomic_state *state) 872 { 873 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 874 drm_plane); 875 struct sti_plane *plane = to_sti_plane(drm_plane); 876 877 if (!oldstate->crtc) { 878 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 879 drm_plane->base.id); 880 return; 881 } 882 883 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 884 oldstate->crtc->base.id, 885 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 886 drm_plane->base.id, sti_plane_to_str(plane)); 887 888 plane->status = STI_PLANE_DISABLING; 889 } 890 891 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 892 .atomic_check = sti_gdp_atomic_check, 893 .atomic_update = sti_gdp_atomic_update, 894 .atomic_disable = sti_gdp_atomic_disable, 895 }; 896 897 static int sti_gdp_late_register(struct drm_plane *drm_plane) 898 { 899 struct sti_plane *plane = to_sti_plane(drm_plane); 900 struct sti_gdp *gdp = to_sti_gdp(plane); 901 902 return gdp_debugfs_init(gdp, drm_plane->dev->primary); 903 } 904 905 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 906 .update_plane = drm_atomic_helper_update_plane, 907 .disable_plane = drm_atomic_helper_disable_plane, 908 .destroy = drm_plane_cleanup, 909 .reset = drm_atomic_helper_plane_reset, 910 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 911 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 912 .late_register = sti_gdp_late_register, 913 }; 914 915 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 916 struct device *dev, int desc, 917 void __iomem *baseaddr, 918 unsigned int possible_crtcs, 919 enum drm_plane_type type) 920 { 921 struct sti_gdp *gdp; 922 int res; 923 924 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 925 if (!gdp) { 926 DRM_ERROR("Failed to allocate memory for GDP\n"); 927 return NULL; 928 } 929 930 gdp->dev = dev; 931 gdp->regs = baseaddr; 932 gdp->plane.desc = desc; 933 gdp->plane.status = STI_PLANE_DISABLED; 934 935 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 936 937 sti_gdp_init(gdp); 938 939 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 940 possible_crtcs, 941 &sti_gdp_plane_helpers_funcs, 942 gdp_supported_formats, 943 ARRAY_SIZE(gdp_supported_formats), 944 NULL, type, NULL); 945 if (res) { 946 DRM_ERROR("Failed to initialize universal plane\n"); 947 goto err; 948 } 949 950 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 951 952 sti_plane_init_property(&gdp->plane, type); 953 954 return &gdp->plane.drm_plane; 955 956 err: 957 devm_kfree(dev, gdp); 958 return NULL; 959 } 960