1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * for STMicroelectronics. 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/dma-mapping.h> 11 12 #include "sti_compositor.h" 13 #include "sti_gdp.h" 14 #include "sti_layer.h" 15 #include "sti_vtg.h" 16 17 #define ENA_COLOR_FILL BIT(8) 18 #define WAIT_NEXT_VSYNC BIT(31) 19 20 /* GDP color formats */ 21 #define GDP_RGB565 0x00 22 #define GDP_RGB888 0x01 23 #define GDP_RGB888_32 0x02 24 #define GDP_ARGB8565 0x04 25 #define GDP_ARGB8888 0x05 26 #define GDP_ARGB1555 0x06 27 #define GDP_ARGB4444 0x07 28 #define GDP_CLUT8 0x0B 29 #define GDP_YCBR888 0x10 30 #define GDP_YCBR422R 0x12 31 #define GDP_AYCBR8888 0x15 32 33 #define GAM_GDP_CTL_OFFSET 0x00 34 #define GAM_GDP_AGC_OFFSET 0x04 35 #define GAM_GDP_VPO_OFFSET 0x0C 36 #define GAM_GDP_VPS_OFFSET 0x10 37 #define GAM_GDP_PML_OFFSET 0x14 38 #define GAM_GDP_PMP_OFFSET 0x18 39 #define GAM_GDP_SIZE_OFFSET 0x1C 40 #define GAM_GDP_NVN_OFFSET 0x24 41 #define GAM_GDP_KEY1_OFFSET 0x28 42 #define GAM_GDP_KEY2_OFFSET 0x2C 43 #define GAM_GDP_PPT_OFFSET 0x34 44 #define GAM_GDP_CML_OFFSET 0x3C 45 #define GAM_GDP_MST_OFFSET 0x68 46 47 #define GAM_GDP_ALPHARANGE_255 BIT(5) 48 #define GAM_GDP_AGC_FULL_RANGE 0x00808080 49 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 50 #define GAM_GDP_SIZE_MAX 0x7FF 51 52 #define GDP_NODE_NB_BANK 2 53 #define GDP_NODE_PER_FIELD 2 54 55 struct sti_gdp_node { 56 u32 gam_gdp_ctl; 57 u32 gam_gdp_agc; 58 u32 reserved1; 59 u32 gam_gdp_vpo; 60 u32 gam_gdp_vps; 61 u32 gam_gdp_pml; 62 u32 gam_gdp_pmp; 63 u32 gam_gdp_size; 64 u32 reserved2; 65 u32 gam_gdp_nvn; 66 u32 gam_gdp_key1; 67 u32 gam_gdp_key2; 68 u32 reserved3; 69 u32 gam_gdp_ppt; 70 u32 reserved4; 71 u32 gam_gdp_cml; 72 }; 73 74 struct sti_gdp_node_list { 75 struct sti_gdp_node *top_field; 76 struct sti_gdp_node *btm_field; 77 }; 78 79 /** 80 * STI GDP structure 81 * 82 * @layer: layer structure 83 * @clk_pix: pixel clock for the current gdp 84 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 85 * @is_curr_top: true if the current node processed is the top field 86 * @node_list: array of node list 87 */ 88 struct sti_gdp { 89 struct sti_layer layer; 90 struct clk *clk_pix; 91 struct notifier_block vtg_field_nb; 92 bool is_curr_top; 93 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 94 }; 95 96 #define to_sti_gdp(x) container_of(x, struct sti_gdp, layer) 97 98 static const uint32_t gdp_supported_formats[] = { 99 DRM_FORMAT_XRGB8888, 100 DRM_FORMAT_ARGB8888, 101 DRM_FORMAT_ARGB4444, 102 DRM_FORMAT_ARGB1555, 103 DRM_FORMAT_RGB565, 104 DRM_FORMAT_RGB888, 105 DRM_FORMAT_AYUV, 106 DRM_FORMAT_YUV444, 107 DRM_FORMAT_VYUY, 108 DRM_FORMAT_C8, 109 }; 110 111 static const uint32_t *sti_gdp_get_formats(struct sti_layer *layer) 112 { 113 return gdp_supported_formats; 114 } 115 116 static unsigned int sti_gdp_get_nb_formats(struct sti_layer *layer) 117 { 118 return ARRAY_SIZE(gdp_supported_formats); 119 } 120 121 static int sti_gdp_fourcc2format(int fourcc) 122 { 123 switch (fourcc) { 124 case DRM_FORMAT_XRGB8888: 125 return GDP_RGB888_32; 126 case DRM_FORMAT_ARGB8888: 127 return GDP_ARGB8888; 128 case DRM_FORMAT_ARGB4444: 129 return GDP_ARGB4444; 130 case DRM_FORMAT_ARGB1555: 131 return GDP_ARGB1555; 132 case DRM_FORMAT_RGB565: 133 return GDP_RGB565; 134 case DRM_FORMAT_RGB888: 135 return GDP_RGB888; 136 case DRM_FORMAT_AYUV: 137 return GDP_AYCBR8888; 138 case DRM_FORMAT_YUV444: 139 return GDP_YCBR888; 140 case DRM_FORMAT_VYUY: 141 return GDP_YCBR422R; 142 case DRM_FORMAT_C8: 143 return GDP_CLUT8; 144 } 145 return -1; 146 } 147 148 static int sti_gdp_get_alpharange(int format) 149 { 150 switch (format) { 151 case GDP_ARGB8565: 152 case GDP_ARGB8888: 153 case GDP_AYCBR8888: 154 return GAM_GDP_ALPHARANGE_255; 155 } 156 return 0; 157 } 158 159 /** 160 * sti_gdp_get_free_nodes 161 * @layer: gdp layer 162 * 163 * Look for a GDP node list that is not currently read by the HW. 164 * 165 * RETURNS: 166 * Pointer to the free GDP node list 167 */ 168 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_layer *layer) 169 { 170 int hw_nvn; 171 void *virt_nvn; 172 struct sti_gdp *gdp = to_sti_gdp(layer); 173 unsigned int i; 174 175 hw_nvn = readl(layer->regs + GAM_GDP_NVN_OFFSET); 176 if (!hw_nvn) 177 goto end; 178 179 virt_nvn = dma_to_virt(layer->dev, (dma_addr_t) hw_nvn); 180 181 for (i = 0; i < GDP_NODE_NB_BANK; i++) 182 if ((virt_nvn != gdp->node_list[i].btm_field) && 183 (virt_nvn != gdp->node_list[i].top_field)) 184 return &gdp->node_list[i]; 185 186 /* in hazardious cases restart with the first node */ 187 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 188 sti_layer_to_str(layer), hw_nvn); 189 190 end: 191 return &gdp->node_list[0]; 192 } 193 194 /** 195 * sti_gdp_get_current_nodes 196 * @layer: GDP layer 197 * 198 * Look for GDP nodes that are currently read by the HW. 199 * 200 * RETURNS: 201 * Pointer to the current GDP node list 202 */ 203 static 204 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_layer *layer) 205 { 206 int hw_nvn; 207 void *virt_nvn; 208 struct sti_gdp *gdp = to_sti_gdp(layer); 209 unsigned int i; 210 211 hw_nvn = readl(layer->regs + GAM_GDP_NVN_OFFSET); 212 if (!hw_nvn) 213 goto end; 214 215 virt_nvn = dma_to_virt(layer->dev, (dma_addr_t) hw_nvn); 216 217 for (i = 0; i < GDP_NODE_NB_BANK; i++) 218 if ((virt_nvn == gdp->node_list[i].btm_field) || 219 (virt_nvn == gdp->node_list[i].top_field)) 220 return &gdp->node_list[i]; 221 222 end: 223 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 224 hw_nvn, sti_layer_to_str(layer)); 225 226 return NULL; 227 } 228 229 /** 230 * sti_gdp_prepare_layer 231 * @lay: gdp layer 232 * @first_prepare: true if it is the first time this function is called 233 * 234 * Update the free GDP node list according to the layer properties. 235 * 236 * RETURNS: 237 * 0 on success. 238 */ 239 static int sti_gdp_prepare_layer(struct sti_layer *layer, bool first_prepare) 240 { 241 struct sti_gdp_node_list *list; 242 struct sti_gdp_node *top_field, *btm_field; 243 struct drm_display_mode *mode = layer->mode; 244 struct device *dev = layer->dev; 245 struct sti_gdp *gdp = to_sti_gdp(layer); 246 struct sti_compositor *compo = dev_get_drvdata(dev); 247 int format; 248 unsigned int depth, bpp; 249 int rate = mode->clock * 1000; 250 int res; 251 u32 ydo, xdo, yds, xds; 252 253 list = sti_gdp_get_free_nodes(layer); 254 top_field = list->top_field; 255 btm_field = list->btm_field; 256 257 dev_dbg(dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 258 sti_layer_to_str(layer), top_field, btm_field); 259 260 /* Build the top field from layer params */ 261 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 262 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 263 format = sti_gdp_fourcc2format(layer->format); 264 if (format == -1) { 265 DRM_ERROR("Format not supported by GDP %.4s\n", 266 (char *)&layer->format); 267 return 1; 268 } 269 top_field->gam_gdp_ctl |= format; 270 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 271 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 272 273 /* pixel memory location */ 274 drm_fb_get_bpp_depth(layer->format, &depth, &bpp); 275 top_field->gam_gdp_pml = (u32) layer->paddr + layer->offsets[0]; 276 top_field->gam_gdp_pml += layer->src_x * (bpp >> 3); 277 top_field->gam_gdp_pml += layer->src_y * layer->pitches[0]; 278 279 /* input parameters */ 280 top_field->gam_gdp_pmp = layer->pitches[0]; 281 top_field->gam_gdp_size = 282 clamp_val(layer->src_h, 0, GAM_GDP_SIZE_MAX) << 16 | 283 clamp_val(layer->src_w, 0, GAM_GDP_SIZE_MAX); 284 285 /* output parameters */ 286 ydo = sti_vtg_get_line_number(*mode, layer->dst_y); 287 yds = sti_vtg_get_line_number(*mode, layer->dst_y + layer->dst_h - 1); 288 xdo = sti_vtg_get_pixel_number(*mode, layer->dst_x); 289 xds = sti_vtg_get_pixel_number(*mode, layer->dst_x + layer->dst_w - 1); 290 top_field->gam_gdp_vpo = (ydo << 16) | xdo; 291 top_field->gam_gdp_vps = (yds << 16) | xds; 292 293 /* Same content and chained together */ 294 memcpy(btm_field, top_field, sizeof(*btm_field)); 295 top_field->gam_gdp_nvn = virt_to_dma(dev, btm_field); 296 btm_field->gam_gdp_nvn = virt_to_dma(dev, top_field); 297 298 /* Interlaced mode */ 299 if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE) 300 btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 301 layer->pitches[0]; 302 303 if (first_prepare) { 304 /* Register gdp callback */ 305 if (sti_vtg_register_client(layer->mixer_id == STI_MIXER_MAIN ? 306 compo->vtg_main : compo->vtg_aux, 307 &gdp->vtg_field_nb, layer->mixer_id)) { 308 DRM_ERROR("Cannot register VTG notifier\n"); 309 return 1; 310 } 311 312 /* Set and enable gdp clock */ 313 if (gdp->clk_pix) { 314 res = clk_set_rate(gdp->clk_pix, rate); 315 if (res < 0) { 316 DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 317 rate); 318 return 1; 319 } 320 321 if (clk_prepare_enable(gdp->clk_pix)) { 322 DRM_ERROR("Failed to prepare/enable gdp\n"); 323 return 1; 324 } 325 } 326 } 327 328 return 0; 329 } 330 331 /** 332 * sti_gdp_commit_layer 333 * @lay: gdp layer 334 * 335 * Update the NVN field of the 'right' field of the current GDP node (being 336 * used by the HW) with the address of the updated ('free') top field GDP node. 337 * - In interlaced mode the 'right' field is the bottom field as we update 338 * frames starting from their top field 339 * - In progressive mode, we update both bottom and top fields which are 340 * equal nodes. 341 * At the next VSYNC, the updated node list will be used by the HW. 342 * 343 * RETURNS: 344 * 0 on success. 345 */ 346 static int sti_gdp_commit_layer(struct sti_layer *layer) 347 { 348 struct sti_gdp_node_list *updated_list = sti_gdp_get_free_nodes(layer); 349 struct sti_gdp_node *updated_top_node = updated_list->top_field; 350 struct sti_gdp_node *updated_btm_node = updated_list->btm_field; 351 struct sti_gdp *gdp = to_sti_gdp(layer); 352 u32 dma_updated_top = virt_to_dma(layer->dev, updated_top_node); 353 u32 dma_updated_btm = virt_to_dma(layer->dev, updated_btm_node); 354 struct sti_gdp_node_list *curr_list = sti_gdp_get_current_nodes(layer); 355 356 dev_dbg(layer->dev, "%s %s top/btm_node:0x%p/0x%p\n", __func__, 357 sti_layer_to_str(layer), 358 updated_top_node, updated_btm_node); 359 dev_dbg(layer->dev, "Current NVN:0x%X\n", 360 readl(layer->regs + GAM_GDP_NVN_OFFSET)); 361 dev_dbg(layer->dev, "Posted buff: %lx current buff: %x\n", 362 (unsigned long)layer->paddr, 363 readl(layer->regs + GAM_GDP_PML_OFFSET)); 364 365 if (curr_list == NULL) { 366 /* First update or invalid node should directly write in the 367 * hw register */ 368 DRM_DEBUG_DRIVER("%s first update (or invalid node)", 369 sti_layer_to_str(layer)); 370 371 writel(gdp->is_curr_top == true ? 372 dma_updated_btm : dma_updated_top, 373 layer->regs + GAM_GDP_NVN_OFFSET); 374 return 0; 375 } 376 377 if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE) { 378 if (gdp->is_curr_top == true) { 379 /* Do not update in the middle of the frame, but 380 * postpone the update after the bottom field has 381 * been displayed */ 382 curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 383 } else { 384 /* Direct update to avoid one frame delay */ 385 writel(dma_updated_top, 386 layer->regs + GAM_GDP_NVN_OFFSET); 387 } 388 } else { 389 /* Direct update for progressive to avoid one frame delay */ 390 writel(dma_updated_top, layer->regs + GAM_GDP_NVN_OFFSET); 391 } 392 393 return 0; 394 } 395 396 /** 397 * sti_gdp_disable_layer 398 * @lay: gdp layer 399 * 400 * Disable a GDP. 401 * 402 * RETURNS: 403 * 0 on success. 404 */ 405 static int sti_gdp_disable_layer(struct sti_layer *layer) 406 { 407 unsigned int i; 408 struct sti_gdp *gdp = to_sti_gdp(layer); 409 struct sti_compositor *compo = dev_get_drvdata(layer->dev); 410 411 DRM_DEBUG_DRIVER("%s\n", sti_layer_to_str(layer)); 412 413 /* Set the nodes as 'to be ignored on mixer' */ 414 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 415 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 416 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 417 } 418 419 if (sti_vtg_unregister_client(layer->mixer_id == STI_MIXER_MAIN ? 420 compo->vtg_main : compo->vtg_aux, &gdp->vtg_field_nb)) 421 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 422 423 if (gdp->clk_pix) 424 clk_disable_unprepare(gdp->clk_pix); 425 426 return 0; 427 } 428 429 /** 430 * sti_gdp_field_cb 431 * @nb: notifier block 432 * @event: event message 433 * @data: private data 434 * 435 * Handle VTG top field and bottom field event. 436 * 437 * RETURNS: 438 * 0 on success. 439 */ 440 int sti_gdp_field_cb(struct notifier_block *nb, 441 unsigned long event, void *data) 442 { 443 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 444 445 switch (event) { 446 case VTG_TOP_FIELD_EVENT: 447 gdp->is_curr_top = true; 448 break; 449 case VTG_BOTTOM_FIELD_EVENT: 450 gdp->is_curr_top = false; 451 break; 452 default: 453 DRM_ERROR("unsupported event: %lu\n", event); 454 break; 455 } 456 457 return 0; 458 } 459 460 static void sti_gdp_init(struct sti_layer *layer) 461 { 462 struct sti_gdp *gdp = to_sti_gdp(layer); 463 struct device_node *np = layer->dev->of_node; 464 dma_addr_t dma; 465 void *base; 466 unsigned int i, size; 467 468 /* Allocate all the nodes within a single memory page */ 469 size = sizeof(struct sti_gdp_node) * 470 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 471 472 base = dma_alloc_writecombine(layer->dev, 473 size, &dma, GFP_KERNEL | GFP_DMA); 474 if (!base) { 475 DRM_ERROR("Failed to allocate memory for GDP node\n"); 476 return; 477 } 478 memset(base, 0, size); 479 480 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 481 if (virt_to_dma(layer->dev, base) & 0xF) { 482 DRM_ERROR("Mem alignment failed\n"); 483 return; 484 } 485 gdp->node_list[i].top_field = base; 486 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 487 base += sizeof(struct sti_gdp_node); 488 489 if (virt_to_dma(layer->dev, base) & 0xF) { 490 DRM_ERROR("Mem alignment failed\n"); 491 return; 492 } 493 gdp->node_list[i].btm_field = base; 494 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 495 base += sizeof(struct sti_gdp_node); 496 } 497 498 if (of_device_is_compatible(np, "st,stih407-compositor")) { 499 /* GDP of STiH407 chip have its own pixel clock */ 500 char *clk_name; 501 502 switch (layer->desc) { 503 case STI_GDP_0: 504 clk_name = "pix_gdp1"; 505 break; 506 case STI_GDP_1: 507 clk_name = "pix_gdp2"; 508 break; 509 case STI_GDP_2: 510 clk_name = "pix_gdp3"; 511 break; 512 case STI_GDP_3: 513 clk_name = "pix_gdp4"; 514 break; 515 default: 516 DRM_ERROR("GDP id not recognized\n"); 517 return; 518 } 519 520 gdp->clk_pix = devm_clk_get(layer->dev, clk_name); 521 if (IS_ERR(gdp->clk_pix)) 522 DRM_ERROR("Cannot get %s clock\n", clk_name); 523 } 524 } 525 526 static const struct sti_layer_funcs gdp_ops = { 527 .get_formats = sti_gdp_get_formats, 528 .get_nb_formats = sti_gdp_get_nb_formats, 529 .init = sti_gdp_init, 530 .prepare = sti_gdp_prepare_layer, 531 .commit = sti_gdp_commit_layer, 532 .disable = sti_gdp_disable_layer, 533 }; 534 535 struct sti_layer *sti_gdp_create(struct device *dev, int id) 536 { 537 struct sti_gdp *gdp; 538 539 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 540 if (!gdp) { 541 DRM_ERROR("Failed to allocate memory for GDP\n"); 542 return NULL; 543 } 544 545 gdp->layer.ops = &gdp_ops; 546 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 547 548 return (struct sti_layer *)gdp; 549 } 550