1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * Fabien Dessenne <fabien.dessenne@st.com> 6 * for STMicroelectronics. 7 */ 8 9 #include <linux/dma-mapping.h> 10 #include <linux/seq_file.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_fb_cma_helper.h> 15 #include <drm/drm_fourcc.h> 16 #include <drm/drm_gem_cma_helper.h> 17 18 #include "sti_compositor.h" 19 #include "sti_gdp.h" 20 #include "sti_plane.h" 21 #include "sti_vtg.h" 22 23 #define ALPHASWITCH BIT(6) 24 #define ENA_COLOR_FILL BIT(8) 25 #define BIGNOTLITTLE BIT(23) 26 #define WAIT_NEXT_VSYNC BIT(31) 27 28 /* GDP color formats */ 29 #define GDP_RGB565 0x00 30 #define GDP_RGB888 0x01 31 #define GDP_RGB888_32 0x02 32 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 33 #define GDP_ARGB8565 0x04 34 #define GDP_ARGB8888 0x05 35 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 36 #define GDP_ARGB1555 0x06 37 #define GDP_ARGB4444 0x07 38 39 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 40 41 static struct gdp_format_to_str { 42 int format; 43 char name[20]; 44 } gdp_format_to_str[] = { 45 GDP2STR(RGB565), 46 GDP2STR(RGB888), 47 GDP2STR(RGB888_32), 48 GDP2STR(XBGR8888), 49 GDP2STR(ARGB8565), 50 GDP2STR(ARGB8888), 51 GDP2STR(ABGR8888), 52 GDP2STR(ARGB1555), 53 GDP2STR(ARGB4444) 54 }; 55 56 #define GAM_GDP_CTL_OFFSET 0x00 57 #define GAM_GDP_AGC_OFFSET 0x04 58 #define GAM_GDP_VPO_OFFSET 0x0C 59 #define GAM_GDP_VPS_OFFSET 0x10 60 #define GAM_GDP_PML_OFFSET 0x14 61 #define GAM_GDP_PMP_OFFSET 0x18 62 #define GAM_GDP_SIZE_OFFSET 0x1C 63 #define GAM_GDP_NVN_OFFSET 0x24 64 #define GAM_GDP_KEY1_OFFSET 0x28 65 #define GAM_GDP_KEY2_OFFSET 0x2C 66 #define GAM_GDP_PPT_OFFSET 0x34 67 #define GAM_GDP_CML_OFFSET 0x3C 68 #define GAM_GDP_MST_OFFSET 0x68 69 70 #define GAM_GDP_ALPHARANGE_255 BIT(5) 71 #define GAM_GDP_AGC_FULL_RANGE 0x00808080 72 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 73 74 #define GAM_GDP_SIZE_MAX_WIDTH 3840 75 #define GAM_GDP_SIZE_MAX_HEIGHT 2160 76 77 #define GDP_NODE_NB_BANK 2 78 #define GDP_NODE_PER_FIELD 2 79 80 struct sti_gdp_node { 81 u32 gam_gdp_ctl; 82 u32 gam_gdp_agc; 83 u32 reserved1; 84 u32 gam_gdp_vpo; 85 u32 gam_gdp_vps; 86 u32 gam_gdp_pml; 87 u32 gam_gdp_pmp; 88 u32 gam_gdp_size; 89 u32 reserved2; 90 u32 gam_gdp_nvn; 91 u32 gam_gdp_key1; 92 u32 gam_gdp_key2; 93 u32 reserved3; 94 u32 gam_gdp_ppt; 95 u32 reserved4; 96 u32 gam_gdp_cml; 97 }; 98 99 struct sti_gdp_node_list { 100 struct sti_gdp_node *top_field; 101 dma_addr_t top_field_paddr; 102 struct sti_gdp_node *btm_field; 103 dma_addr_t btm_field_paddr; 104 }; 105 106 /* 107 * STI GDP structure 108 * 109 * @sti_plane: sti_plane structure 110 * @dev: driver device 111 * @regs: gdp registers 112 * @clk_pix: pixel clock for the current gdp 113 * @clk_main_parent: gdp parent clock if main path used 114 * @clk_aux_parent: gdp parent clock if aux path used 115 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 116 * @is_curr_top: true if the current node processed is the top field 117 * @node_list: array of node list 118 * @vtg: registered vtg 119 */ 120 struct sti_gdp { 121 struct sti_plane plane; 122 struct device *dev; 123 void __iomem *regs; 124 struct clk *clk_pix; 125 struct clk *clk_main_parent; 126 struct clk *clk_aux_parent; 127 struct notifier_block vtg_field_nb; 128 bool is_curr_top; 129 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 130 struct sti_vtg *vtg; 131 }; 132 133 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 134 135 static const uint32_t gdp_supported_formats[] = { 136 DRM_FORMAT_XRGB8888, 137 DRM_FORMAT_XBGR8888, 138 DRM_FORMAT_ARGB8888, 139 DRM_FORMAT_ABGR8888, 140 DRM_FORMAT_ARGB4444, 141 DRM_FORMAT_ARGB1555, 142 DRM_FORMAT_RGB565, 143 DRM_FORMAT_RGB888, 144 }; 145 146 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 147 readl(gdp->regs + reg ## _OFFSET)) 148 149 static void gdp_dbg_ctl(struct seq_file *s, int val) 150 { 151 int i; 152 153 seq_puts(s, "\tColor:"); 154 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 155 if (gdp_format_to_str[i].format == (val & 0x1F)) { 156 seq_puts(s, gdp_format_to_str[i].name); 157 break; 158 } 159 } 160 if (i == ARRAY_SIZE(gdp_format_to_str)) 161 seq_puts(s, "<UNKNOWN>"); 162 163 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 164 } 165 166 static void gdp_dbg_vpo(struct seq_file *s, int val) 167 { 168 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 169 } 170 171 static void gdp_dbg_vps(struct seq_file *s, int val) 172 { 173 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 174 } 175 176 static void gdp_dbg_size(struct seq_file *s, int val) 177 { 178 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 179 } 180 181 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 182 { 183 void *base = NULL; 184 unsigned int i; 185 186 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 187 if (gdp->node_list[i].top_field_paddr == val) { 188 base = gdp->node_list[i].top_field; 189 break; 190 } 191 if (gdp->node_list[i].btm_field_paddr == val) { 192 base = gdp->node_list[i].btm_field; 193 break; 194 } 195 } 196 197 if (base) 198 seq_printf(s, "\tVirt @: %p", base); 199 } 200 201 static void gdp_dbg_ppt(struct seq_file *s, int val) 202 { 203 if (val & GAM_GDP_PPT_IGNORE) 204 seq_puts(s, "\tNot displayed on mixer!"); 205 } 206 207 static void gdp_dbg_mst(struct seq_file *s, int val) 208 { 209 if (val & 1) 210 seq_puts(s, "\tBUFFER UNDERFLOW!"); 211 } 212 213 static int gdp_dbg_show(struct seq_file *s, void *data) 214 { 215 struct drm_info_node *node = s->private; 216 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 217 struct drm_plane *drm_plane = &gdp->plane.drm_plane; 218 struct drm_crtc *crtc; 219 220 drm_modeset_lock(&drm_plane->mutex, NULL); 221 crtc = drm_plane->state->crtc; 222 drm_modeset_unlock(&drm_plane->mutex); 223 224 seq_printf(s, "%s: (vaddr = 0x%p)", 225 sti_plane_to_str(&gdp->plane), gdp->regs); 226 227 DBGFS_DUMP(GAM_GDP_CTL); 228 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 229 DBGFS_DUMP(GAM_GDP_AGC); 230 DBGFS_DUMP(GAM_GDP_VPO); 231 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 232 DBGFS_DUMP(GAM_GDP_VPS); 233 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 234 DBGFS_DUMP(GAM_GDP_PML); 235 DBGFS_DUMP(GAM_GDP_PMP); 236 DBGFS_DUMP(GAM_GDP_SIZE); 237 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 238 DBGFS_DUMP(GAM_GDP_NVN); 239 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 240 DBGFS_DUMP(GAM_GDP_KEY1); 241 DBGFS_DUMP(GAM_GDP_KEY2); 242 DBGFS_DUMP(GAM_GDP_PPT); 243 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 244 DBGFS_DUMP(GAM_GDP_CML); 245 DBGFS_DUMP(GAM_GDP_MST); 246 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 247 248 seq_puts(s, "\n\n"); 249 if (!crtc) 250 seq_puts(s, " Not connected to any DRM CRTC\n"); 251 else 252 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 253 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 254 255 return 0; 256 } 257 258 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 259 { 260 seq_printf(s, "\t@:0x%p", node); 261 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 262 gdp_dbg_ctl(s, node->gam_gdp_ctl); 263 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 264 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 265 gdp_dbg_vpo(s, node->gam_gdp_vpo); 266 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 267 gdp_dbg_vps(s, node->gam_gdp_vps); 268 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 269 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 270 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 271 gdp_dbg_size(s, node->gam_gdp_size); 272 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 273 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 274 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 275 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 276 gdp_dbg_ppt(s, node->gam_gdp_ppt); 277 seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml); 278 } 279 280 static int gdp_node_dbg_show(struct seq_file *s, void *arg) 281 { 282 struct drm_info_node *node = s->private; 283 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 284 unsigned int b; 285 286 for (b = 0; b < GDP_NODE_NB_BANK; b++) { 287 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 288 gdp_node_dump_node(s, gdp->node_list[b].top_field); 289 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 290 gdp_node_dump_node(s, gdp->node_list[b].btm_field); 291 } 292 293 return 0; 294 } 295 296 static struct drm_info_list gdp0_debugfs_files[] = { 297 { "gdp0", gdp_dbg_show, 0, NULL }, 298 { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 299 }; 300 301 static struct drm_info_list gdp1_debugfs_files[] = { 302 { "gdp1", gdp_dbg_show, 0, NULL }, 303 { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 304 }; 305 306 static struct drm_info_list gdp2_debugfs_files[] = { 307 { "gdp2", gdp_dbg_show, 0, NULL }, 308 { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 309 }; 310 311 static struct drm_info_list gdp3_debugfs_files[] = { 312 { "gdp3", gdp_dbg_show, 0, NULL }, 313 { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 314 }; 315 316 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 317 { 318 unsigned int i; 319 struct drm_info_list *gdp_debugfs_files; 320 int nb_files; 321 322 switch (gdp->plane.desc) { 323 case STI_GDP_0: 324 gdp_debugfs_files = gdp0_debugfs_files; 325 nb_files = ARRAY_SIZE(gdp0_debugfs_files); 326 break; 327 case STI_GDP_1: 328 gdp_debugfs_files = gdp1_debugfs_files; 329 nb_files = ARRAY_SIZE(gdp1_debugfs_files); 330 break; 331 case STI_GDP_2: 332 gdp_debugfs_files = gdp2_debugfs_files; 333 nb_files = ARRAY_SIZE(gdp2_debugfs_files); 334 break; 335 case STI_GDP_3: 336 gdp_debugfs_files = gdp3_debugfs_files; 337 nb_files = ARRAY_SIZE(gdp3_debugfs_files); 338 break; 339 default: 340 return -EINVAL; 341 } 342 343 for (i = 0; i < nb_files; i++) 344 gdp_debugfs_files[i].data = gdp; 345 346 drm_debugfs_create_files(gdp_debugfs_files, 347 nb_files, 348 minor->debugfs_root, minor); 349 return 0; 350 } 351 352 static int sti_gdp_fourcc2format(int fourcc) 353 { 354 switch (fourcc) { 355 case DRM_FORMAT_XRGB8888: 356 return GDP_RGB888_32; 357 case DRM_FORMAT_XBGR8888: 358 return GDP_XBGR8888; 359 case DRM_FORMAT_ARGB8888: 360 return GDP_ARGB8888; 361 case DRM_FORMAT_ABGR8888: 362 return GDP_ABGR8888; 363 case DRM_FORMAT_ARGB4444: 364 return GDP_ARGB4444; 365 case DRM_FORMAT_ARGB1555: 366 return GDP_ARGB1555; 367 case DRM_FORMAT_RGB565: 368 return GDP_RGB565; 369 case DRM_FORMAT_RGB888: 370 return GDP_RGB888; 371 } 372 return -1; 373 } 374 375 static int sti_gdp_get_alpharange(int format) 376 { 377 switch (format) { 378 case GDP_ARGB8565: 379 case GDP_ARGB8888: 380 case GDP_ABGR8888: 381 return GAM_GDP_ALPHARANGE_255; 382 } 383 return 0; 384 } 385 386 /** 387 * sti_gdp_get_free_nodes 388 * @gdp: gdp pointer 389 * 390 * Look for a GDP node list that is not currently read by the HW. 391 * 392 * RETURNS: 393 * Pointer to the free GDP node list 394 */ 395 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 396 { 397 int hw_nvn; 398 unsigned int i; 399 400 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 401 if (!hw_nvn) 402 goto end; 403 404 for (i = 0; i < GDP_NODE_NB_BANK; i++) 405 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 406 (hw_nvn != gdp->node_list[i].top_field_paddr)) 407 return &gdp->node_list[i]; 408 409 /* in hazardious cases restart with the first node */ 410 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 411 sti_plane_to_str(&gdp->plane), hw_nvn); 412 413 end: 414 return &gdp->node_list[0]; 415 } 416 417 /** 418 * sti_gdp_get_current_nodes 419 * @gdp: gdp pointer 420 * 421 * Look for GDP nodes that are currently read by the HW. 422 * 423 * RETURNS: 424 * Pointer to the current GDP node list 425 */ 426 static 427 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 428 { 429 int hw_nvn; 430 unsigned int i; 431 432 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 433 if (!hw_nvn) 434 goto end; 435 436 for (i = 0; i < GDP_NODE_NB_BANK; i++) 437 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 438 (hw_nvn == gdp->node_list[i].top_field_paddr)) 439 return &gdp->node_list[i]; 440 441 end: 442 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 443 hw_nvn, sti_plane_to_str(&gdp->plane)); 444 445 return NULL; 446 } 447 448 /** 449 * sti_gdp_disable 450 * @gdp: gdp pointer 451 * 452 * Disable a GDP. 453 */ 454 static void sti_gdp_disable(struct sti_gdp *gdp) 455 { 456 unsigned int i; 457 458 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 459 460 /* Set the nodes as 'to be ignored on mixer' */ 461 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 462 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 463 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 464 } 465 466 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 467 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 468 469 if (gdp->clk_pix) 470 clk_disable_unprepare(gdp->clk_pix); 471 472 gdp->plane.status = STI_PLANE_DISABLED; 473 gdp->vtg = NULL; 474 } 475 476 /** 477 * sti_gdp_field_cb 478 * @nb: notifier block 479 * @event: event message 480 * @data: private data 481 * 482 * Handle VTG top field and bottom field event. 483 * 484 * RETURNS: 485 * 0 on success. 486 */ 487 static int sti_gdp_field_cb(struct notifier_block *nb, 488 unsigned long event, void *data) 489 { 490 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 491 492 if (gdp->plane.status == STI_PLANE_FLUSHING) { 493 /* disable need to be synchronize on vsync event */ 494 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 495 sti_plane_to_str(&gdp->plane)); 496 497 sti_gdp_disable(gdp); 498 } 499 500 switch (event) { 501 case VTG_TOP_FIELD_EVENT: 502 gdp->is_curr_top = true; 503 break; 504 case VTG_BOTTOM_FIELD_EVENT: 505 gdp->is_curr_top = false; 506 break; 507 default: 508 DRM_ERROR("unsupported event: %lu\n", event); 509 break; 510 } 511 512 return 0; 513 } 514 515 static void sti_gdp_init(struct sti_gdp *gdp) 516 { 517 struct device_node *np = gdp->dev->of_node; 518 dma_addr_t dma_addr; 519 void *base; 520 unsigned int i, size; 521 522 /* Allocate all the nodes within a single memory page */ 523 size = sizeof(struct sti_gdp_node) * 524 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 525 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL); 526 527 if (!base) { 528 DRM_ERROR("Failed to allocate memory for GDP node\n"); 529 return; 530 } 531 memset(base, 0, size); 532 533 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 534 if (dma_addr & 0xF) { 535 DRM_ERROR("Mem alignment failed\n"); 536 return; 537 } 538 gdp->node_list[i].top_field = base; 539 gdp->node_list[i].top_field_paddr = dma_addr; 540 541 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 542 base += sizeof(struct sti_gdp_node); 543 dma_addr += sizeof(struct sti_gdp_node); 544 545 if (dma_addr & 0xF) { 546 DRM_ERROR("Mem alignment failed\n"); 547 return; 548 } 549 gdp->node_list[i].btm_field = base; 550 gdp->node_list[i].btm_field_paddr = dma_addr; 551 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 552 base += sizeof(struct sti_gdp_node); 553 dma_addr += sizeof(struct sti_gdp_node); 554 } 555 556 if (of_device_is_compatible(np, "st,stih407-compositor")) { 557 /* GDP of STiH407 chip have its own pixel clock */ 558 char *clk_name; 559 560 switch (gdp->plane.desc) { 561 case STI_GDP_0: 562 clk_name = "pix_gdp1"; 563 break; 564 case STI_GDP_1: 565 clk_name = "pix_gdp2"; 566 break; 567 case STI_GDP_2: 568 clk_name = "pix_gdp3"; 569 break; 570 case STI_GDP_3: 571 clk_name = "pix_gdp4"; 572 break; 573 default: 574 DRM_ERROR("GDP id not recognized\n"); 575 return; 576 } 577 578 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 579 if (IS_ERR(gdp->clk_pix)) 580 DRM_ERROR("Cannot get %s clock\n", clk_name); 581 582 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 583 if (IS_ERR(gdp->clk_main_parent)) 584 DRM_ERROR("Cannot get main_parent clock\n"); 585 586 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 587 if (IS_ERR(gdp->clk_aux_parent)) 588 DRM_ERROR("Cannot get aux_parent clock\n"); 589 } 590 } 591 592 /** 593 * sti_gdp_get_dst 594 * @dev: device 595 * @dst: requested destination size 596 * @src: source size 597 * 598 * Return the cropped / clamped destination size 599 * 600 * RETURNS: 601 * cropped / clamped destination size 602 */ 603 static int sti_gdp_get_dst(struct device *dev, int dst, int src) 604 { 605 if (dst == src) 606 return dst; 607 608 if (dst < src) { 609 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 610 return dst; 611 } 612 613 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 614 return src; 615 } 616 617 static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 618 struct drm_atomic_state *state) 619 { 620 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 621 drm_plane); 622 struct sti_plane *plane = to_sti_plane(drm_plane); 623 struct sti_gdp *gdp = to_sti_gdp(plane); 624 struct drm_crtc *crtc = new_plane_state->crtc; 625 struct drm_framebuffer *fb = new_plane_state->fb; 626 struct drm_crtc_state *crtc_state; 627 struct sti_mixer *mixer; 628 struct drm_display_mode *mode; 629 int dst_x, dst_y, dst_w, dst_h; 630 int src_x, src_y, src_w, src_h; 631 int format; 632 633 /* no need for further checks if the plane is being disabled */ 634 if (!crtc || !fb) 635 return 0; 636 637 mixer = to_sti_mixer(crtc); 638 crtc_state = drm_atomic_get_crtc_state(state, crtc); 639 mode = &crtc_state->mode; 640 dst_x = new_plane_state->crtc_x; 641 dst_y = new_plane_state->crtc_y; 642 dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x); 643 dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y); 644 /* src_x are in 16.16 format */ 645 src_x = new_plane_state->src_x >> 16; 646 src_y = new_plane_state->src_y >> 16; 647 src_w = clamp_val(new_plane_state->src_w >> 16, 0, 648 GAM_GDP_SIZE_MAX_WIDTH); 649 src_h = clamp_val(new_plane_state->src_h >> 16, 0, 650 GAM_GDP_SIZE_MAX_HEIGHT); 651 652 format = sti_gdp_fourcc2format(fb->format->format); 653 if (format == -1) { 654 DRM_ERROR("Format not supported by GDP %.4s\n", 655 (char *)&fb->format->format); 656 return -EINVAL; 657 } 658 659 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 660 DRM_ERROR("Can't get CMA GEM object for fb\n"); 661 return -EINVAL; 662 } 663 664 /* Set gdp clock */ 665 if (mode->clock && gdp->clk_pix) { 666 struct clk *clkp; 667 int rate = mode->clock * 1000; 668 int res; 669 670 /* 671 * According to the mixer used, the gdp pixel clock 672 * should have a different parent clock. 673 */ 674 if (mixer->id == STI_MIXER_MAIN) 675 clkp = gdp->clk_main_parent; 676 else 677 clkp = gdp->clk_aux_parent; 678 679 if (clkp) 680 clk_set_parent(gdp->clk_pix, clkp); 681 682 res = clk_set_rate(gdp->clk_pix, rate); 683 if (res < 0) { 684 DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 685 rate); 686 return -EINVAL; 687 } 688 } 689 690 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 691 crtc->base.id, sti_mixer_to_str(mixer), 692 drm_plane->base.id, sti_plane_to_str(plane)); 693 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 694 sti_plane_to_str(plane), 695 dst_w, dst_h, dst_x, dst_y, 696 src_w, src_h, src_x, src_y); 697 698 return 0; 699 } 700 701 static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 702 struct drm_atomic_state *state) 703 { 704 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 705 drm_plane); 706 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state, 707 drm_plane); 708 struct sti_plane *plane = to_sti_plane(drm_plane); 709 struct sti_gdp *gdp = to_sti_gdp(plane); 710 struct drm_crtc *crtc = newstate->crtc; 711 struct drm_framebuffer *fb = newstate->fb; 712 struct drm_display_mode *mode; 713 int dst_x, dst_y, dst_w, dst_h; 714 int src_x, src_y, src_w, src_h; 715 struct drm_gem_cma_object *cma_obj; 716 struct sti_gdp_node_list *list; 717 struct sti_gdp_node_list *curr_list; 718 struct sti_gdp_node *top_field, *btm_field; 719 u32 dma_updated_top; 720 u32 dma_updated_btm; 721 int format; 722 unsigned int bpp; 723 u32 ydo, xdo, yds, xds; 724 725 if (!crtc || !fb) 726 return; 727 728 if ((oldstate->fb == newstate->fb) && 729 (oldstate->crtc_x == newstate->crtc_x) && 730 (oldstate->crtc_y == newstate->crtc_y) && 731 (oldstate->crtc_w == newstate->crtc_w) && 732 (oldstate->crtc_h == newstate->crtc_h) && 733 (oldstate->src_x == newstate->src_x) && 734 (oldstate->src_y == newstate->src_y) && 735 (oldstate->src_w == newstate->src_w) && 736 (oldstate->src_h == newstate->src_h)) { 737 /* No change since last update, do not post cmd */ 738 DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 739 plane->status = STI_PLANE_UPDATED; 740 return; 741 } 742 743 if (!gdp->vtg) { 744 struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 745 struct sti_mixer *mixer = to_sti_mixer(crtc); 746 747 /* Register gdp callback */ 748 gdp->vtg = compo->vtg[mixer->id]; 749 sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc); 750 clk_prepare_enable(gdp->clk_pix); 751 } 752 753 mode = &crtc->mode; 754 dst_x = newstate->crtc_x; 755 dst_y = newstate->crtc_y; 756 dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x); 757 dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y); 758 /* src_x are in 16.16 format */ 759 src_x = newstate->src_x >> 16; 760 src_y = newstate->src_y >> 16; 761 src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 762 src_h = clamp_val(newstate->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 763 764 list = sti_gdp_get_free_nodes(gdp); 765 top_field = list->top_field; 766 btm_field = list->btm_field; 767 768 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 769 sti_plane_to_str(plane), top_field, btm_field); 770 771 /* build the top field */ 772 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 773 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 774 format = sti_gdp_fourcc2format(fb->format->format); 775 top_field->gam_gdp_ctl |= format; 776 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 777 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 778 779 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 780 781 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 782 (char *)&fb->format->format, 783 (unsigned long)cma_obj->paddr); 784 785 /* pixel memory location */ 786 bpp = fb->format->cpp[0]; 787 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 788 top_field->gam_gdp_pml += src_x * bpp; 789 top_field->gam_gdp_pml += src_y * fb->pitches[0]; 790 791 /* output parameters (clamped / cropped) */ 792 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 793 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 794 ydo = sti_vtg_get_line_number(*mode, dst_y); 795 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 796 xdo = sti_vtg_get_pixel_number(*mode, dst_x); 797 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 798 top_field->gam_gdp_vpo = (ydo << 16) | xdo; 799 top_field->gam_gdp_vps = (yds << 16) | xds; 800 801 /* input parameters */ 802 src_w = dst_w; 803 top_field->gam_gdp_pmp = fb->pitches[0]; 804 top_field->gam_gdp_size = src_h << 16 | src_w; 805 806 /* Same content and chained together */ 807 memcpy(btm_field, top_field, sizeof(*btm_field)); 808 top_field->gam_gdp_nvn = list->btm_field_paddr; 809 btm_field->gam_gdp_nvn = list->top_field_paddr; 810 811 /* Interlaced mode */ 812 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 813 btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 814 fb->pitches[0]; 815 816 /* Update the NVN field of the 'right' field of the current GDP node 817 * (being used by the HW) with the address of the updated ('free') top 818 * field GDP node. 819 * - In interlaced mode the 'right' field is the bottom field as we 820 * update frames starting from their top field 821 * - In progressive mode, we update both bottom and top fields which 822 * are equal nodes. 823 * At the next VSYNC, the updated node list will be used by the HW. 824 */ 825 curr_list = sti_gdp_get_current_nodes(gdp); 826 dma_updated_top = list->top_field_paddr; 827 dma_updated_btm = list->btm_field_paddr; 828 829 dev_dbg(gdp->dev, "Current NVN:0x%X\n", 830 readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 831 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 832 (unsigned long)cma_obj->paddr, 833 readl(gdp->regs + GAM_GDP_PML_OFFSET)); 834 835 if (!curr_list) { 836 /* First update or invalid node should directly write in the 837 * hw register */ 838 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n", 839 sti_plane_to_str(plane)); 840 841 writel(gdp->is_curr_top ? 842 dma_updated_btm : dma_updated_top, 843 gdp->regs + GAM_GDP_NVN_OFFSET); 844 goto end; 845 } 846 847 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 848 if (gdp->is_curr_top) { 849 /* Do not update in the middle of the frame, but 850 * postpone the update after the bottom field has 851 * been displayed */ 852 curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 853 } else { 854 /* Direct update to avoid one frame delay */ 855 writel(dma_updated_top, 856 gdp->regs + GAM_GDP_NVN_OFFSET); 857 } 858 } else { 859 /* Direct update for progressive to avoid one frame delay */ 860 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 861 } 862 863 end: 864 sti_plane_update_fps(plane, true, false); 865 866 plane->status = STI_PLANE_UPDATED; 867 } 868 869 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 870 struct drm_atomic_state *state) 871 { 872 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state, 873 drm_plane); 874 struct sti_plane *plane = to_sti_plane(drm_plane); 875 876 if (!oldstate->crtc) { 877 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 878 drm_plane->base.id); 879 return; 880 } 881 882 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 883 oldstate->crtc->base.id, 884 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 885 drm_plane->base.id, sti_plane_to_str(plane)); 886 887 plane->status = STI_PLANE_DISABLING; 888 } 889 890 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 891 .atomic_check = sti_gdp_atomic_check, 892 .atomic_update = sti_gdp_atomic_update, 893 .atomic_disable = sti_gdp_atomic_disable, 894 }; 895 896 static int sti_gdp_late_register(struct drm_plane *drm_plane) 897 { 898 struct sti_plane *plane = to_sti_plane(drm_plane); 899 struct sti_gdp *gdp = to_sti_gdp(plane); 900 901 return gdp_debugfs_init(gdp, drm_plane->dev->primary); 902 } 903 904 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 905 .update_plane = drm_atomic_helper_update_plane, 906 .disable_plane = drm_atomic_helper_disable_plane, 907 .destroy = drm_plane_cleanup, 908 .reset = drm_atomic_helper_plane_reset, 909 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 910 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 911 .late_register = sti_gdp_late_register, 912 }; 913 914 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 915 struct device *dev, int desc, 916 void __iomem *baseaddr, 917 unsigned int possible_crtcs, 918 enum drm_plane_type type) 919 { 920 struct sti_gdp *gdp; 921 int res; 922 923 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 924 if (!gdp) { 925 DRM_ERROR("Failed to allocate memory for GDP\n"); 926 return NULL; 927 } 928 929 gdp->dev = dev; 930 gdp->regs = baseaddr; 931 gdp->plane.desc = desc; 932 gdp->plane.status = STI_PLANE_DISABLED; 933 934 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 935 936 sti_gdp_init(gdp); 937 938 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 939 possible_crtcs, 940 &sti_gdp_plane_helpers_funcs, 941 gdp_supported_formats, 942 ARRAY_SIZE(gdp_supported_formats), 943 NULL, type, NULL); 944 if (res) { 945 DRM_ERROR("Failed to initialize universal plane\n"); 946 goto err; 947 } 948 949 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 950 951 sti_plane_init_property(&gdp->plane, type); 952 953 return &gdp->plane.drm_plane; 954 955 err: 956 devm_kfree(dev, gdp); 957 return NULL; 958 } 959