1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * Fabien Dessenne <fabien.dessenne@st.com> 6 * for STMicroelectronics. 7 */ 8 #include <linux/seq_file.h> 9 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_fb_cma_helper.h> 12 #include <drm/drm_gem_cma_helper.h> 13 14 #include "sti_compositor.h" 15 #include "sti_gdp.h" 16 #include "sti_plane.h" 17 #include "sti_vtg.h" 18 19 #define ALPHASWITCH BIT(6) 20 #define ENA_COLOR_FILL BIT(8) 21 #define BIGNOTLITTLE BIT(23) 22 #define WAIT_NEXT_VSYNC BIT(31) 23 24 /* GDP color formats */ 25 #define GDP_RGB565 0x00 26 #define GDP_RGB888 0x01 27 #define GDP_RGB888_32 0x02 28 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 29 #define GDP_ARGB8565 0x04 30 #define GDP_ARGB8888 0x05 31 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 32 #define GDP_ARGB1555 0x06 33 #define GDP_ARGB4444 0x07 34 35 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 36 37 static struct gdp_format_to_str { 38 int format; 39 char name[20]; 40 } gdp_format_to_str[] = { 41 GDP2STR(RGB565), 42 GDP2STR(RGB888), 43 GDP2STR(RGB888_32), 44 GDP2STR(XBGR8888), 45 GDP2STR(ARGB8565), 46 GDP2STR(ARGB8888), 47 GDP2STR(ABGR8888), 48 GDP2STR(ARGB1555), 49 GDP2STR(ARGB4444) 50 }; 51 52 #define GAM_GDP_CTL_OFFSET 0x00 53 #define GAM_GDP_AGC_OFFSET 0x04 54 #define GAM_GDP_VPO_OFFSET 0x0C 55 #define GAM_GDP_VPS_OFFSET 0x10 56 #define GAM_GDP_PML_OFFSET 0x14 57 #define GAM_GDP_PMP_OFFSET 0x18 58 #define GAM_GDP_SIZE_OFFSET 0x1C 59 #define GAM_GDP_NVN_OFFSET 0x24 60 #define GAM_GDP_KEY1_OFFSET 0x28 61 #define GAM_GDP_KEY2_OFFSET 0x2C 62 #define GAM_GDP_PPT_OFFSET 0x34 63 #define GAM_GDP_CML_OFFSET 0x3C 64 #define GAM_GDP_MST_OFFSET 0x68 65 66 #define GAM_GDP_ALPHARANGE_255 BIT(5) 67 #define GAM_GDP_AGC_FULL_RANGE 0x00808080 68 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 69 70 #define GAM_GDP_SIZE_MAX_WIDTH 3840 71 #define GAM_GDP_SIZE_MAX_HEIGHT 2160 72 73 #define GDP_NODE_NB_BANK 2 74 #define GDP_NODE_PER_FIELD 2 75 76 struct sti_gdp_node { 77 u32 gam_gdp_ctl; 78 u32 gam_gdp_agc; 79 u32 reserved1; 80 u32 gam_gdp_vpo; 81 u32 gam_gdp_vps; 82 u32 gam_gdp_pml; 83 u32 gam_gdp_pmp; 84 u32 gam_gdp_size; 85 u32 reserved2; 86 u32 gam_gdp_nvn; 87 u32 gam_gdp_key1; 88 u32 gam_gdp_key2; 89 u32 reserved3; 90 u32 gam_gdp_ppt; 91 u32 reserved4; 92 u32 gam_gdp_cml; 93 }; 94 95 struct sti_gdp_node_list { 96 struct sti_gdp_node *top_field; 97 dma_addr_t top_field_paddr; 98 struct sti_gdp_node *btm_field; 99 dma_addr_t btm_field_paddr; 100 }; 101 102 /** 103 * STI GDP structure 104 * 105 * @sti_plane: sti_plane structure 106 * @dev: driver device 107 * @regs: gdp registers 108 * @clk_pix: pixel clock for the current gdp 109 * @clk_main_parent: gdp parent clock if main path used 110 * @clk_aux_parent: gdp parent clock if aux path used 111 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 112 * @is_curr_top: true if the current node processed is the top field 113 * @node_list: array of node list 114 * @vtg: registered vtg 115 */ 116 struct sti_gdp { 117 struct sti_plane plane; 118 struct device *dev; 119 void __iomem *regs; 120 struct clk *clk_pix; 121 struct clk *clk_main_parent; 122 struct clk *clk_aux_parent; 123 struct notifier_block vtg_field_nb; 124 bool is_curr_top; 125 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 126 struct sti_vtg *vtg; 127 }; 128 129 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 130 131 static const uint32_t gdp_supported_formats[] = { 132 DRM_FORMAT_XRGB8888, 133 DRM_FORMAT_XBGR8888, 134 DRM_FORMAT_ARGB8888, 135 DRM_FORMAT_ABGR8888, 136 DRM_FORMAT_ARGB4444, 137 DRM_FORMAT_ARGB1555, 138 DRM_FORMAT_RGB565, 139 DRM_FORMAT_RGB888, 140 }; 141 142 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 143 readl(gdp->regs + reg ## _OFFSET)) 144 145 static void gdp_dbg_ctl(struct seq_file *s, int val) 146 { 147 int i; 148 149 seq_puts(s, "\tColor:"); 150 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 151 if (gdp_format_to_str[i].format == (val & 0x1F)) { 152 seq_puts(s, gdp_format_to_str[i].name); 153 break; 154 } 155 } 156 if (i == ARRAY_SIZE(gdp_format_to_str)) 157 seq_puts(s, "<UNKNOWN>"); 158 159 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 160 } 161 162 static void gdp_dbg_vpo(struct seq_file *s, int val) 163 { 164 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 165 } 166 167 static void gdp_dbg_vps(struct seq_file *s, int val) 168 { 169 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 170 } 171 172 static void gdp_dbg_size(struct seq_file *s, int val) 173 { 174 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 175 } 176 177 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 178 { 179 void *base = NULL; 180 unsigned int i; 181 182 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 183 if (gdp->node_list[i].top_field_paddr == val) { 184 base = gdp->node_list[i].top_field; 185 break; 186 } 187 if (gdp->node_list[i].btm_field_paddr == val) { 188 base = gdp->node_list[i].btm_field; 189 break; 190 } 191 } 192 193 if (base) 194 seq_printf(s, "\tVirt @: %p", base); 195 } 196 197 static void gdp_dbg_ppt(struct seq_file *s, int val) 198 { 199 if (val & GAM_GDP_PPT_IGNORE) 200 seq_puts(s, "\tNot displayed on mixer!"); 201 } 202 203 static void gdp_dbg_mst(struct seq_file *s, int val) 204 { 205 if (val & 1) 206 seq_puts(s, "\tBUFFER UNDERFLOW!"); 207 } 208 209 static int gdp_dbg_show(struct seq_file *s, void *data) 210 { 211 struct drm_info_node *node = s->private; 212 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 213 struct drm_plane *drm_plane = &gdp->plane.drm_plane; 214 struct drm_crtc *crtc; 215 216 drm_modeset_lock(&drm_plane->mutex, NULL); 217 crtc = drm_plane->state->crtc; 218 drm_modeset_unlock(&drm_plane->mutex); 219 220 seq_printf(s, "%s: (vaddr = 0x%p)", 221 sti_plane_to_str(&gdp->plane), gdp->regs); 222 223 DBGFS_DUMP(GAM_GDP_CTL); 224 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 225 DBGFS_DUMP(GAM_GDP_AGC); 226 DBGFS_DUMP(GAM_GDP_VPO); 227 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 228 DBGFS_DUMP(GAM_GDP_VPS); 229 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 230 DBGFS_DUMP(GAM_GDP_PML); 231 DBGFS_DUMP(GAM_GDP_PMP); 232 DBGFS_DUMP(GAM_GDP_SIZE); 233 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 234 DBGFS_DUMP(GAM_GDP_NVN); 235 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 236 DBGFS_DUMP(GAM_GDP_KEY1); 237 DBGFS_DUMP(GAM_GDP_KEY2); 238 DBGFS_DUMP(GAM_GDP_PPT); 239 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 240 DBGFS_DUMP(GAM_GDP_CML); 241 DBGFS_DUMP(GAM_GDP_MST); 242 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 243 244 seq_puts(s, "\n\n"); 245 if (!crtc) 246 seq_puts(s, " Not connected to any DRM CRTC\n"); 247 else 248 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 249 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 250 251 return 0; 252 } 253 254 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 255 { 256 seq_printf(s, "\t@:0x%p", node); 257 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 258 gdp_dbg_ctl(s, node->gam_gdp_ctl); 259 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 260 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 261 gdp_dbg_vpo(s, node->gam_gdp_vpo); 262 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 263 gdp_dbg_vps(s, node->gam_gdp_vps); 264 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 265 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 266 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 267 gdp_dbg_size(s, node->gam_gdp_size); 268 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 269 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 270 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 271 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 272 gdp_dbg_ppt(s, node->gam_gdp_ppt); 273 seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml); 274 } 275 276 static int gdp_node_dbg_show(struct seq_file *s, void *arg) 277 { 278 struct drm_info_node *node = s->private; 279 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 280 unsigned int b; 281 282 for (b = 0; b < GDP_NODE_NB_BANK; b++) { 283 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 284 gdp_node_dump_node(s, gdp->node_list[b].top_field); 285 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 286 gdp_node_dump_node(s, gdp->node_list[b].btm_field); 287 } 288 289 return 0; 290 } 291 292 static struct drm_info_list gdp0_debugfs_files[] = { 293 { "gdp0", gdp_dbg_show, 0, NULL }, 294 { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 295 }; 296 297 static struct drm_info_list gdp1_debugfs_files[] = { 298 { "gdp1", gdp_dbg_show, 0, NULL }, 299 { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 300 }; 301 302 static struct drm_info_list gdp2_debugfs_files[] = { 303 { "gdp2", gdp_dbg_show, 0, NULL }, 304 { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 305 }; 306 307 static struct drm_info_list gdp3_debugfs_files[] = { 308 { "gdp3", gdp_dbg_show, 0, NULL }, 309 { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 310 }; 311 312 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 313 { 314 unsigned int i; 315 struct drm_info_list *gdp_debugfs_files; 316 int nb_files; 317 318 switch (gdp->plane.desc) { 319 case STI_GDP_0: 320 gdp_debugfs_files = gdp0_debugfs_files; 321 nb_files = ARRAY_SIZE(gdp0_debugfs_files); 322 break; 323 case STI_GDP_1: 324 gdp_debugfs_files = gdp1_debugfs_files; 325 nb_files = ARRAY_SIZE(gdp1_debugfs_files); 326 break; 327 case STI_GDP_2: 328 gdp_debugfs_files = gdp2_debugfs_files; 329 nb_files = ARRAY_SIZE(gdp2_debugfs_files); 330 break; 331 case STI_GDP_3: 332 gdp_debugfs_files = gdp3_debugfs_files; 333 nb_files = ARRAY_SIZE(gdp3_debugfs_files); 334 break; 335 default: 336 return -EINVAL; 337 } 338 339 for (i = 0; i < nb_files; i++) 340 gdp_debugfs_files[i].data = gdp; 341 342 return drm_debugfs_create_files(gdp_debugfs_files, 343 nb_files, 344 minor->debugfs_root, minor); 345 } 346 347 static int sti_gdp_fourcc2format(int fourcc) 348 { 349 switch (fourcc) { 350 case DRM_FORMAT_XRGB8888: 351 return GDP_RGB888_32; 352 case DRM_FORMAT_XBGR8888: 353 return GDP_XBGR8888; 354 case DRM_FORMAT_ARGB8888: 355 return GDP_ARGB8888; 356 case DRM_FORMAT_ABGR8888: 357 return GDP_ABGR8888; 358 case DRM_FORMAT_ARGB4444: 359 return GDP_ARGB4444; 360 case DRM_FORMAT_ARGB1555: 361 return GDP_ARGB1555; 362 case DRM_FORMAT_RGB565: 363 return GDP_RGB565; 364 case DRM_FORMAT_RGB888: 365 return GDP_RGB888; 366 } 367 return -1; 368 } 369 370 static int sti_gdp_get_alpharange(int format) 371 { 372 switch (format) { 373 case GDP_ARGB8565: 374 case GDP_ARGB8888: 375 case GDP_ABGR8888: 376 return GAM_GDP_ALPHARANGE_255; 377 } 378 return 0; 379 } 380 381 /** 382 * sti_gdp_get_free_nodes 383 * @gdp: gdp pointer 384 * 385 * Look for a GDP node list that is not currently read by the HW. 386 * 387 * RETURNS: 388 * Pointer to the free GDP node list 389 */ 390 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 391 { 392 int hw_nvn; 393 unsigned int i; 394 395 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 396 if (!hw_nvn) 397 goto end; 398 399 for (i = 0; i < GDP_NODE_NB_BANK; i++) 400 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 401 (hw_nvn != gdp->node_list[i].top_field_paddr)) 402 return &gdp->node_list[i]; 403 404 /* in hazardious cases restart with the first node */ 405 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 406 sti_plane_to_str(&gdp->plane), hw_nvn); 407 408 end: 409 return &gdp->node_list[0]; 410 } 411 412 /** 413 * sti_gdp_get_current_nodes 414 * @gdp: gdp pointer 415 * 416 * Look for GDP nodes that are currently read by the HW. 417 * 418 * RETURNS: 419 * Pointer to the current GDP node list 420 */ 421 static 422 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 423 { 424 int hw_nvn; 425 unsigned int i; 426 427 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 428 if (!hw_nvn) 429 goto end; 430 431 for (i = 0; i < GDP_NODE_NB_BANK; i++) 432 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 433 (hw_nvn == gdp->node_list[i].top_field_paddr)) 434 return &gdp->node_list[i]; 435 436 end: 437 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 438 hw_nvn, sti_plane_to_str(&gdp->plane)); 439 440 return NULL; 441 } 442 443 /** 444 * sti_gdp_disable 445 * @gdp: gdp pointer 446 * 447 * Disable a GDP. 448 */ 449 static void sti_gdp_disable(struct sti_gdp *gdp) 450 { 451 unsigned int i; 452 453 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 454 455 /* Set the nodes as 'to be ignored on mixer' */ 456 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 457 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 458 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 459 } 460 461 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 462 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 463 464 if (gdp->clk_pix) 465 clk_disable_unprepare(gdp->clk_pix); 466 467 gdp->plane.status = STI_PLANE_DISABLED; 468 gdp->vtg = NULL; 469 } 470 471 /** 472 * sti_gdp_field_cb 473 * @nb: notifier block 474 * @event: event message 475 * @data: private data 476 * 477 * Handle VTG top field and bottom field event. 478 * 479 * RETURNS: 480 * 0 on success. 481 */ 482 static int sti_gdp_field_cb(struct notifier_block *nb, 483 unsigned long event, void *data) 484 { 485 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 486 487 if (gdp->plane.status == STI_PLANE_FLUSHING) { 488 /* disable need to be synchronize on vsync event */ 489 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 490 sti_plane_to_str(&gdp->plane)); 491 492 sti_gdp_disable(gdp); 493 } 494 495 switch (event) { 496 case VTG_TOP_FIELD_EVENT: 497 gdp->is_curr_top = true; 498 break; 499 case VTG_BOTTOM_FIELD_EVENT: 500 gdp->is_curr_top = false; 501 break; 502 default: 503 DRM_ERROR("unsupported event: %lu\n", event); 504 break; 505 } 506 507 return 0; 508 } 509 510 static void sti_gdp_init(struct sti_gdp *gdp) 511 { 512 struct device_node *np = gdp->dev->of_node; 513 dma_addr_t dma_addr; 514 void *base; 515 unsigned int i, size; 516 517 /* Allocate all the nodes within a single memory page */ 518 size = sizeof(struct sti_gdp_node) * 519 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 520 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA); 521 522 if (!base) { 523 DRM_ERROR("Failed to allocate memory for GDP node\n"); 524 return; 525 } 526 memset(base, 0, size); 527 528 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 529 if (dma_addr & 0xF) { 530 DRM_ERROR("Mem alignment failed\n"); 531 return; 532 } 533 gdp->node_list[i].top_field = base; 534 gdp->node_list[i].top_field_paddr = dma_addr; 535 536 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 537 base += sizeof(struct sti_gdp_node); 538 dma_addr += sizeof(struct sti_gdp_node); 539 540 if (dma_addr & 0xF) { 541 DRM_ERROR("Mem alignment failed\n"); 542 return; 543 } 544 gdp->node_list[i].btm_field = base; 545 gdp->node_list[i].btm_field_paddr = dma_addr; 546 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 547 base += sizeof(struct sti_gdp_node); 548 dma_addr += sizeof(struct sti_gdp_node); 549 } 550 551 if (of_device_is_compatible(np, "st,stih407-compositor")) { 552 /* GDP of STiH407 chip have its own pixel clock */ 553 char *clk_name; 554 555 switch (gdp->plane.desc) { 556 case STI_GDP_0: 557 clk_name = "pix_gdp1"; 558 break; 559 case STI_GDP_1: 560 clk_name = "pix_gdp2"; 561 break; 562 case STI_GDP_2: 563 clk_name = "pix_gdp3"; 564 break; 565 case STI_GDP_3: 566 clk_name = "pix_gdp4"; 567 break; 568 default: 569 DRM_ERROR("GDP id not recognized\n"); 570 return; 571 } 572 573 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 574 if (IS_ERR(gdp->clk_pix)) 575 DRM_ERROR("Cannot get %s clock\n", clk_name); 576 577 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 578 if (IS_ERR(gdp->clk_main_parent)) 579 DRM_ERROR("Cannot get main_parent clock\n"); 580 581 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 582 if (IS_ERR(gdp->clk_aux_parent)) 583 DRM_ERROR("Cannot get aux_parent clock\n"); 584 } 585 } 586 587 /** 588 * sti_gdp_get_dst 589 * @dev: device 590 * @dst: requested destination size 591 * @src: source size 592 * 593 * Return the cropped / clamped destination size 594 * 595 * RETURNS: 596 * cropped / clamped destination size 597 */ 598 static int sti_gdp_get_dst(struct device *dev, int dst, int src) 599 { 600 if (dst == src) 601 return dst; 602 603 if (dst < src) { 604 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 605 return dst; 606 } 607 608 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 609 return src; 610 } 611 612 static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 613 struct drm_plane_state *state) 614 { 615 struct sti_plane *plane = to_sti_plane(drm_plane); 616 struct sti_gdp *gdp = to_sti_gdp(plane); 617 struct drm_crtc *crtc = state->crtc; 618 struct drm_framebuffer *fb = state->fb; 619 struct drm_crtc_state *crtc_state; 620 struct sti_mixer *mixer; 621 struct drm_display_mode *mode; 622 int dst_x, dst_y, dst_w, dst_h; 623 int src_x, src_y, src_w, src_h; 624 int format; 625 626 /* no need for further checks if the plane is being disabled */ 627 if (!crtc || !fb) 628 return 0; 629 630 mixer = to_sti_mixer(crtc); 631 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 632 mode = &crtc_state->mode; 633 dst_x = state->crtc_x; 634 dst_y = state->crtc_y; 635 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 636 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 637 /* src_x are in 16.16 format */ 638 src_x = state->src_x >> 16; 639 src_y = state->src_y >> 16; 640 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 641 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 642 643 format = sti_gdp_fourcc2format(fb->format->format); 644 if (format == -1) { 645 DRM_ERROR("Format not supported by GDP %.4s\n", 646 (char *)&fb->format->format); 647 return -EINVAL; 648 } 649 650 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 651 DRM_ERROR("Can't get CMA GEM object for fb\n"); 652 return -EINVAL; 653 } 654 655 /* Set gdp clock */ 656 if (mode->clock && gdp->clk_pix) { 657 struct clk *clkp; 658 int rate = mode->clock * 1000; 659 int res; 660 661 /* 662 * According to the mixer used, the gdp pixel clock 663 * should have a different parent clock. 664 */ 665 if (mixer->id == STI_MIXER_MAIN) 666 clkp = gdp->clk_main_parent; 667 else 668 clkp = gdp->clk_aux_parent; 669 670 if (clkp) 671 clk_set_parent(gdp->clk_pix, clkp); 672 673 res = clk_set_rate(gdp->clk_pix, rate); 674 if (res < 0) { 675 DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 676 rate); 677 return -EINVAL; 678 } 679 } 680 681 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 682 crtc->base.id, sti_mixer_to_str(mixer), 683 drm_plane->base.id, sti_plane_to_str(plane)); 684 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 685 sti_plane_to_str(plane), 686 dst_w, dst_h, dst_x, dst_y, 687 src_w, src_h, src_x, src_y); 688 689 return 0; 690 } 691 692 static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 693 struct drm_plane_state *oldstate) 694 { 695 struct drm_plane_state *state = drm_plane->state; 696 struct sti_plane *plane = to_sti_plane(drm_plane); 697 struct sti_gdp *gdp = to_sti_gdp(plane); 698 struct drm_crtc *crtc = state->crtc; 699 struct drm_framebuffer *fb = state->fb; 700 struct drm_display_mode *mode; 701 int dst_x, dst_y, dst_w, dst_h; 702 int src_x, src_y, src_w, src_h; 703 struct drm_gem_cma_object *cma_obj; 704 struct sti_gdp_node_list *list; 705 struct sti_gdp_node_list *curr_list; 706 struct sti_gdp_node *top_field, *btm_field; 707 u32 dma_updated_top; 708 u32 dma_updated_btm; 709 int format; 710 unsigned int bpp; 711 u32 ydo, xdo, yds, xds; 712 713 if (!crtc || !fb) 714 return; 715 716 if ((oldstate->fb == state->fb) && 717 (oldstate->crtc_x == state->crtc_x) && 718 (oldstate->crtc_y == state->crtc_y) && 719 (oldstate->crtc_w == state->crtc_w) && 720 (oldstate->crtc_h == state->crtc_h) && 721 (oldstate->src_x == state->src_x) && 722 (oldstate->src_y == state->src_y) && 723 (oldstate->src_w == state->src_w) && 724 (oldstate->src_h == state->src_h)) { 725 /* No change since last update, do not post cmd */ 726 DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 727 plane->status = STI_PLANE_UPDATED; 728 return; 729 } 730 731 if (!gdp->vtg) { 732 struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 733 struct sti_mixer *mixer = to_sti_mixer(crtc); 734 735 /* Register gdp callback */ 736 gdp->vtg = compo->vtg[mixer->id]; 737 sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc); 738 clk_prepare_enable(gdp->clk_pix); 739 } 740 741 mode = &crtc->mode; 742 dst_x = state->crtc_x; 743 dst_y = state->crtc_y; 744 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 745 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 746 /* src_x are in 16.16 format */ 747 src_x = state->src_x >> 16; 748 src_y = state->src_y >> 16; 749 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 750 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 751 752 list = sti_gdp_get_free_nodes(gdp); 753 top_field = list->top_field; 754 btm_field = list->btm_field; 755 756 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 757 sti_plane_to_str(plane), top_field, btm_field); 758 759 /* build the top field */ 760 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 761 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 762 format = sti_gdp_fourcc2format(fb->format->format); 763 top_field->gam_gdp_ctl |= format; 764 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 765 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 766 767 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 768 769 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 770 (char *)&fb->format->format, 771 (unsigned long)cma_obj->paddr); 772 773 /* pixel memory location */ 774 bpp = fb->format->cpp[0]; 775 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 776 top_field->gam_gdp_pml += src_x * bpp; 777 top_field->gam_gdp_pml += src_y * fb->pitches[0]; 778 779 /* output parameters (clamped / cropped) */ 780 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 781 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 782 ydo = sti_vtg_get_line_number(*mode, dst_y); 783 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 784 xdo = sti_vtg_get_pixel_number(*mode, dst_x); 785 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 786 top_field->gam_gdp_vpo = (ydo << 16) | xdo; 787 top_field->gam_gdp_vps = (yds << 16) | xds; 788 789 /* input parameters */ 790 src_w = dst_w; 791 top_field->gam_gdp_pmp = fb->pitches[0]; 792 top_field->gam_gdp_size = src_h << 16 | src_w; 793 794 /* Same content and chained together */ 795 memcpy(btm_field, top_field, sizeof(*btm_field)); 796 top_field->gam_gdp_nvn = list->btm_field_paddr; 797 btm_field->gam_gdp_nvn = list->top_field_paddr; 798 799 /* Interlaced mode */ 800 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 801 btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 802 fb->pitches[0]; 803 804 /* Update the NVN field of the 'right' field of the current GDP node 805 * (being used by the HW) with the address of the updated ('free') top 806 * field GDP node. 807 * - In interlaced mode the 'right' field is the bottom field as we 808 * update frames starting from their top field 809 * - In progressive mode, we update both bottom and top fields which 810 * are equal nodes. 811 * At the next VSYNC, the updated node list will be used by the HW. 812 */ 813 curr_list = sti_gdp_get_current_nodes(gdp); 814 dma_updated_top = list->top_field_paddr; 815 dma_updated_btm = list->btm_field_paddr; 816 817 dev_dbg(gdp->dev, "Current NVN:0x%X\n", 818 readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 819 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 820 (unsigned long)cma_obj->paddr, 821 readl(gdp->regs + GAM_GDP_PML_OFFSET)); 822 823 if (!curr_list) { 824 /* First update or invalid node should directly write in the 825 * hw register */ 826 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n", 827 sti_plane_to_str(plane)); 828 829 writel(gdp->is_curr_top ? 830 dma_updated_btm : dma_updated_top, 831 gdp->regs + GAM_GDP_NVN_OFFSET); 832 goto end; 833 } 834 835 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 836 if (gdp->is_curr_top) { 837 /* Do not update in the middle of the frame, but 838 * postpone the update after the bottom field has 839 * been displayed */ 840 curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 841 } else { 842 /* Direct update to avoid one frame delay */ 843 writel(dma_updated_top, 844 gdp->regs + GAM_GDP_NVN_OFFSET); 845 } 846 } else { 847 /* Direct update for progressive to avoid one frame delay */ 848 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 849 } 850 851 end: 852 sti_plane_update_fps(plane, true, false); 853 854 plane->status = STI_PLANE_UPDATED; 855 } 856 857 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 858 struct drm_plane_state *oldstate) 859 { 860 struct sti_plane *plane = to_sti_plane(drm_plane); 861 862 if (!oldstate->crtc) { 863 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 864 drm_plane->base.id); 865 return; 866 } 867 868 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 869 oldstate->crtc->base.id, 870 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 871 drm_plane->base.id, sti_plane_to_str(plane)); 872 873 plane->status = STI_PLANE_DISABLING; 874 } 875 876 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 877 .atomic_check = sti_gdp_atomic_check, 878 .atomic_update = sti_gdp_atomic_update, 879 .atomic_disable = sti_gdp_atomic_disable, 880 }; 881 882 static void sti_gdp_destroy(struct drm_plane *drm_plane) 883 { 884 DRM_DEBUG_DRIVER("\n"); 885 886 drm_plane_helper_disable(drm_plane, NULL); 887 drm_plane_cleanup(drm_plane); 888 } 889 890 static int sti_gdp_late_register(struct drm_plane *drm_plane) 891 { 892 struct sti_plane *plane = to_sti_plane(drm_plane); 893 struct sti_gdp *gdp = to_sti_gdp(plane); 894 895 return gdp_debugfs_init(gdp, drm_plane->dev->primary); 896 } 897 898 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 899 .update_plane = drm_atomic_helper_update_plane, 900 .disable_plane = drm_atomic_helper_disable_plane, 901 .destroy = sti_gdp_destroy, 902 .reset = sti_plane_reset, 903 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 904 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 905 .late_register = sti_gdp_late_register, 906 }; 907 908 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 909 struct device *dev, int desc, 910 void __iomem *baseaddr, 911 unsigned int possible_crtcs, 912 enum drm_plane_type type) 913 { 914 struct sti_gdp *gdp; 915 int res; 916 917 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 918 if (!gdp) { 919 DRM_ERROR("Failed to allocate memory for GDP\n"); 920 return NULL; 921 } 922 923 gdp->dev = dev; 924 gdp->regs = baseaddr; 925 gdp->plane.desc = desc; 926 gdp->plane.status = STI_PLANE_DISABLED; 927 928 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 929 930 sti_gdp_init(gdp); 931 932 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 933 possible_crtcs, 934 &sti_gdp_plane_helpers_funcs, 935 gdp_supported_formats, 936 ARRAY_SIZE(gdp_supported_formats), 937 NULL, type, NULL); 938 if (res) { 939 DRM_ERROR("Failed to initialize universal plane\n"); 940 goto err; 941 } 942 943 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 944 945 sti_plane_init_property(&gdp->plane, type); 946 947 return &gdp->plane.drm_plane; 948 949 err: 950 devm_kfree(dev, gdp); 951 return NULL; 952 } 953