1ba2d53fbSBenjamin Gaignard /* 2ba2d53fbSBenjamin Gaignard * Copyright (C) STMicroelectronics SA 2014 3ba2d53fbSBenjamin Gaignard * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4ba2d53fbSBenjamin Gaignard * Fabien Dessenne <fabien.dessenne@st.com> 5ba2d53fbSBenjamin Gaignard * for STMicroelectronics. 6ba2d53fbSBenjamin Gaignard * License terms: GNU General Public License (GPL), version 2 7ba2d53fbSBenjamin Gaignard */ 80f3e1561SArnd Bergmann #include <linux/seq_file.h> 9ba2d53fbSBenjamin Gaignard 10dd86dc2fSVincent Abriou #include <drm/drm_atomic.h> 1129d1dc62SVincent Abriou #include <drm/drm_fb_cma_helper.h> 1229d1dc62SVincent Abriou #include <drm/drm_gem_cma_helper.h> 1329d1dc62SVincent Abriou 14d219673dSBenjamin Gaignard #include "sti_compositor.h" 15ba2d53fbSBenjamin Gaignard #include "sti_gdp.h" 169e1f05b2SVincent Abriou #include "sti_plane.h" 17ba2d53fbSBenjamin Gaignard #include "sti_vtg.h" 18ba2d53fbSBenjamin Gaignard 194af6b12aSBenjamin Gaignard #define ALPHASWITCH BIT(6) 20ba2d53fbSBenjamin Gaignard #define ENA_COLOR_FILL BIT(8) 214af6b12aSBenjamin Gaignard #define BIGNOTLITTLE BIT(23) 22ba2d53fbSBenjamin Gaignard #define WAIT_NEXT_VSYNC BIT(31) 23ba2d53fbSBenjamin Gaignard 24ba2d53fbSBenjamin Gaignard /* GDP color formats */ 25ba2d53fbSBenjamin Gaignard #define GDP_RGB565 0x00 26ba2d53fbSBenjamin Gaignard #define GDP_RGB888 0x01 27ba2d53fbSBenjamin Gaignard #define GDP_RGB888_32 0x02 288adb5776SFabien Dessenne #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 29ba2d53fbSBenjamin Gaignard #define GDP_ARGB8565 0x04 30ba2d53fbSBenjamin Gaignard #define GDP_ARGB8888 0x05 314af6b12aSBenjamin Gaignard #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 32ba2d53fbSBenjamin Gaignard #define GDP_ARGB1555 0x06 33ba2d53fbSBenjamin Gaignard #define GDP_ARGB4444 0x07 34ba2d53fbSBenjamin Gaignard 352d61f272SVincent Abriou #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 362d61f272SVincent Abriou 372d61f272SVincent Abriou static struct gdp_format_to_str { 382d61f272SVincent Abriou int format; 392d61f272SVincent Abriou char name[20]; 402d61f272SVincent Abriou } gdp_format_to_str[] = { 412d61f272SVincent Abriou GDP2STR(RGB565), 422d61f272SVincent Abriou GDP2STR(RGB888), 432d61f272SVincent Abriou GDP2STR(RGB888_32), 442d61f272SVincent Abriou GDP2STR(XBGR8888), 452d61f272SVincent Abriou GDP2STR(ARGB8565), 462d61f272SVincent Abriou GDP2STR(ARGB8888), 472d61f272SVincent Abriou GDP2STR(ABGR8888), 482d61f272SVincent Abriou GDP2STR(ARGB1555), 492d61f272SVincent Abriou GDP2STR(ARGB4444) 502d61f272SVincent Abriou }; 51ba2d53fbSBenjamin Gaignard 52ba2d53fbSBenjamin Gaignard #define GAM_GDP_CTL_OFFSET 0x00 53ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_OFFSET 0x04 54ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPO_OFFSET 0x0C 55ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPS_OFFSET 0x10 56ba2d53fbSBenjamin Gaignard #define GAM_GDP_PML_OFFSET 0x14 57ba2d53fbSBenjamin Gaignard #define GAM_GDP_PMP_OFFSET 0x18 58ba2d53fbSBenjamin Gaignard #define GAM_GDP_SIZE_OFFSET 0x1C 59ba2d53fbSBenjamin Gaignard #define GAM_GDP_NVN_OFFSET 0x24 60ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY1_OFFSET 0x28 61ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY2_OFFSET 0x2C 62ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_OFFSET 0x34 63ba2d53fbSBenjamin Gaignard #define GAM_GDP_CML_OFFSET 0x3C 64ba2d53fbSBenjamin Gaignard #define GAM_GDP_MST_OFFSET 0x68 65ba2d53fbSBenjamin Gaignard 66ba2d53fbSBenjamin Gaignard #define GAM_GDP_ALPHARANGE_255 BIT(5) 67ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_FULL_RANGE 0x00808080 68ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 69ba2d53fbSBenjamin Gaignard #define GAM_GDP_SIZE_MAX 0x7FF 70ba2d53fbSBenjamin Gaignard 71ba2d53fbSBenjamin Gaignard #define GDP_NODE_NB_BANK 2 72ba2d53fbSBenjamin Gaignard #define GDP_NODE_PER_FIELD 2 73ba2d53fbSBenjamin Gaignard 74ba2d53fbSBenjamin Gaignard struct sti_gdp_node { 75ba2d53fbSBenjamin Gaignard u32 gam_gdp_ctl; 76ba2d53fbSBenjamin Gaignard u32 gam_gdp_agc; 77ba2d53fbSBenjamin Gaignard u32 reserved1; 78ba2d53fbSBenjamin Gaignard u32 gam_gdp_vpo; 79ba2d53fbSBenjamin Gaignard u32 gam_gdp_vps; 80ba2d53fbSBenjamin Gaignard u32 gam_gdp_pml; 81ba2d53fbSBenjamin Gaignard u32 gam_gdp_pmp; 82ba2d53fbSBenjamin Gaignard u32 gam_gdp_size; 83ba2d53fbSBenjamin Gaignard u32 reserved2; 84ba2d53fbSBenjamin Gaignard u32 gam_gdp_nvn; 85ba2d53fbSBenjamin Gaignard u32 gam_gdp_key1; 86ba2d53fbSBenjamin Gaignard u32 gam_gdp_key2; 87ba2d53fbSBenjamin Gaignard u32 reserved3; 88ba2d53fbSBenjamin Gaignard u32 gam_gdp_ppt; 89ba2d53fbSBenjamin Gaignard u32 reserved4; 90ba2d53fbSBenjamin Gaignard u32 gam_gdp_cml; 91ba2d53fbSBenjamin Gaignard }; 92ba2d53fbSBenjamin Gaignard 93ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list { 94ba2d53fbSBenjamin Gaignard struct sti_gdp_node *top_field; 95a51fe84dSBenjamin Gaignard dma_addr_t top_field_paddr; 96ba2d53fbSBenjamin Gaignard struct sti_gdp_node *btm_field; 97a51fe84dSBenjamin Gaignard dma_addr_t btm_field_paddr; 98ba2d53fbSBenjamin Gaignard }; 99ba2d53fbSBenjamin Gaignard 100ba2d53fbSBenjamin Gaignard /** 101ba2d53fbSBenjamin Gaignard * STI GDP structure 102ba2d53fbSBenjamin Gaignard * 103871bcdfeSVincent Abriou * @sti_plane: sti_plane structure 104871bcdfeSVincent Abriou * @dev: driver device 105871bcdfeSVincent Abriou * @regs: gdp registers 106ba2d53fbSBenjamin Gaignard * @clk_pix: pixel clock for the current gdp 1075e03abc5SBenjamin Gaignard * @clk_main_parent: gdp parent clock if main path used 1085e03abc5SBenjamin Gaignard * @clk_aux_parent: gdp parent clock if aux path used 109ba2d53fbSBenjamin Gaignard * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 110ba2d53fbSBenjamin Gaignard * @is_curr_top: true if the current node processed is the top field 111ba2d53fbSBenjamin Gaignard * @node_list: array of node list 11220c47601Sbenjamin.gaignard@linaro.org * @vtg: registered vtg 113ba2d53fbSBenjamin Gaignard */ 114ba2d53fbSBenjamin Gaignard struct sti_gdp { 115871bcdfeSVincent Abriou struct sti_plane plane; 116871bcdfeSVincent Abriou struct device *dev; 117871bcdfeSVincent Abriou void __iomem *regs; 118ba2d53fbSBenjamin Gaignard struct clk *clk_pix; 1195e03abc5SBenjamin Gaignard struct clk *clk_main_parent; 1205e03abc5SBenjamin Gaignard struct clk *clk_aux_parent; 121ba2d53fbSBenjamin Gaignard struct notifier_block vtg_field_nb; 122ba2d53fbSBenjamin Gaignard bool is_curr_top; 123ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 12420c47601Sbenjamin.gaignard@linaro.org struct sti_vtg *vtg; 125ba2d53fbSBenjamin Gaignard }; 126ba2d53fbSBenjamin Gaignard 127871bcdfeSVincent Abriou #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 128ba2d53fbSBenjamin Gaignard 129ba2d53fbSBenjamin Gaignard static const uint32_t gdp_supported_formats[] = { 130ba2d53fbSBenjamin Gaignard DRM_FORMAT_XRGB8888, 1318adb5776SFabien Dessenne DRM_FORMAT_XBGR8888, 132ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB8888, 1334af6b12aSBenjamin Gaignard DRM_FORMAT_ABGR8888, 134ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB4444, 135ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB1555, 136ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB565, 137ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB888, 138ba2d53fbSBenjamin Gaignard }; 139ba2d53fbSBenjamin Gaignard 1402d61f272SVincent Abriou #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 1412d61f272SVincent Abriou readl(gdp->regs + reg ## _OFFSET)) 1422d61f272SVincent Abriou 1432d61f272SVincent Abriou static void gdp_dbg_ctl(struct seq_file *s, int val) 1442d61f272SVincent Abriou { 1452d61f272SVincent Abriou int i; 1462d61f272SVincent Abriou 1472d61f272SVincent Abriou seq_puts(s, "\tColor:"); 1482d61f272SVincent Abriou for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 1492d61f272SVincent Abriou if (gdp_format_to_str[i].format == (val & 0x1F)) { 1502d61f272SVincent Abriou seq_printf(s, gdp_format_to_str[i].name); 1512d61f272SVincent Abriou break; 1522d61f272SVincent Abriou } 1532d61f272SVincent Abriou } 1542d61f272SVincent Abriou if (i == ARRAY_SIZE(gdp_format_to_str)) 1552d61f272SVincent Abriou seq_puts(s, "<UNKNOWN>"); 1562d61f272SVincent Abriou 1572d61f272SVincent Abriou seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 1582d61f272SVincent Abriou } 1592d61f272SVincent Abriou 1602d61f272SVincent Abriou static void gdp_dbg_vpo(struct seq_file *s, int val) 1612d61f272SVincent Abriou { 1622d61f272SVincent Abriou seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 1632d61f272SVincent Abriou } 1642d61f272SVincent Abriou 1652d61f272SVincent Abriou static void gdp_dbg_vps(struct seq_file *s, int val) 1662d61f272SVincent Abriou { 1672d61f272SVincent Abriou seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 1682d61f272SVincent Abriou } 1692d61f272SVincent Abriou 1702d61f272SVincent Abriou static void gdp_dbg_size(struct seq_file *s, int val) 1712d61f272SVincent Abriou { 1722d61f272SVincent Abriou seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 1732d61f272SVincent Abriou } 1742d61f272SVincent Abriou 1752d61f272SVincent Abriou static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 1762d61f272SVincent Abriou { 1772d61f272SVincent Abriou void *base = NULL; 1782d61f272SVincent Abriou unsigned int i; 1792d61f272SVincent Abriou 1802d61f272SVincent Abriou for (i = 0; i < GDP_NODE_NB_BANK; i++) { 1812d61f272SVincent Abriou if (gdp->node_list[i].top_field_paddr == val) { 1822d61f272SVincent Abriou base = gdp->node_list[i].top_field; 1832d61f272SVincent Abriou break; 1842d61f272SVincent Abriou } 1852d61f272SVincent Abriou if (gdp->node_list[i].btm_field_paddr == val) { 1862d61f272SVincent Abriou base = gdp->node_list[i].btm_field; 1872d61f272SVincent Abriou break; 1882d61f272SVincent Abriou } 1892d61f272SVincent Abriou } 1902d61f272SVincent Abriou 1912d61f272SVincent Abriou if (base) 1922d61f272SVincent Abriou seq_printf(s, "\tVirt @: %p", base); 1932d61f272SVincent Abriou } 1942d61f272SVincent Abriou 1952d61f272SVincent Abriou static void gdp_dbg_ppt(struct seq_file *s, int val) 1962d61f272SVincent Abriou { 1972d61f272SVincent Abriou if (val & GAM_GDP_PPT_IGNORE) 1982d61f272SVincent Abriou seq_puts(s, "\tNot displayed on mixer!"); 1992d61f272SVincent Abriou } 2002d61f272SVincent Abriou 2012d61f272SVincent Abriou static void gdp_dbg_mst(struct seq_file *s, int val) 2022d61f272SVincent Abriou { 2032d61f272SVincent Abriou if (val & 1) 2042d61f272SVincent Abriou seq_puts(s, "\tBUFFER UNDERFLOW!"); 2052d61f272SVincent Abriou } 2062d61f272SVincent Abriou 2072d61f272SVincent Abriou static int gdp_dbg_show(struct seq_file *s, void *data) 2082d61f272SVincent Abriou { 2092d61f272SVincent Abriou struct drm_info_node *node = s->private; 2102d61f272SVincent Abriou struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 2112d61f272SVincent Abriou struct drm_plane *drm_plane = &gdp->plane.drm_plane; 2122d61f272SVincent Abriou struct drm_crtc *crtc = drm_plane->crtc; 2132d61f272SVincent Abriou 2142d61f272SVincent Abriou seq_printf(s, "%s: (vaddr = 0x%p)", 2152d61f272SVincent Abriou sti_plane_to_str(&gdp->plane), gdp->regs); 2162d61f272SVincent Abriou 2172d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_CTL); 2182d61f272SVincent Abriou gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 2192d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_AGC); 2202d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_VPO); 2212d61f272SVincent Abriou gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 2222d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_VPS); 2232d61f272SVincent Abriou gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 2242d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PML); 2252d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PMP); 2262d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_SIZE); 2272d61f272SVincent Abriou gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 2282d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_NVN); 2292d61f272SVincent Abriou gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 2302d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_KEY1); 2312d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_KEY2); 2322d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PPT); 2332d61f272SVincent Abriou gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 2342d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_CML); 2352d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_MST); 2362d61f272SVincent Abriou gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 2372d61f272SVincent Abriou 2382d61f272SVincent Abriou seq_puts(s, "\n\n"); 2392d61f272SVincent Abriou if (!crtc) 2402d61f272SVincent Abriou seq_puts(s, " Not connected to any DRM CRTC\n"); 2412d61f272SVincent Abriou else 2422d61f272SVincent Abriou seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 2432d61f272SVincent Abriou crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 2442d61f272SVincent Abriou 2452d61f272SVincent Abriou return 0; 2462d61f272SVincent Abriou } 2472d61f272SVincent Abriou 2482d61f272SVincent Abriou static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 2492d61f272SVincent Abriou { 2502d61f272SVincent Abriou seq_printf(s, "\t@:0x%p", node); 2512d61f272SVincent Abriou seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 2522d61f272SVincent Abriou gdp_dbg_ctl(s, node->gam_gdp_ctl); 2532d61f272SVincent Abriou seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 2542d61f272SVincent Abriou seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 2552d61f272SVincent Abriou gdp_dbg_vpo(s, node->gam_gdp_vpo); 2562d61f272SVincent Abriou seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 2572d61f272SVincent Abriou gdp_dbg_vps(s, node->gam_gdp_vps); 2582d61f272SVincent Abriou seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 2592d61f272SVincent Abriou seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 2602d61f272SVincent Abriou seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 2612d61f272SVincent Abriou gdp_dbg_size(s, node->gam_gdp_size); 2622d61f272SVincent Abriou seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 2632d61f272SVincent Abriou seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 2642d61f272SVincent Abriou seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 2652d61f272SVincent Abriou seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 2662d61f272SVincent Abriou gdp_dbg_ppt(s, node->gam_gdp_ppt); 2672d61f272SVincent Abriou seq_printf(s, "\n\tCML 0x%08X", node->gam_gdp_cml); 2682d61f272SVincent Abriou seq_puts(s, "\n"); 2692d61f272SVincent Abriou } 2702d61f272SVincent Abriou 2712d61f272SVincent Abriou static int gdp_node_dbg_show(struct seq_file *s, void *arg) 2722d61f272SVincent Abriou { 2732d61f272SVincent Abriou struct drm_info_node *node = s->private; 2742d61f272SVincent Abriou struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 2752d61f272SVincent Abriou unsigned int b; 2762d61f272SVincent Abriou 2772d61f272SVincent Abriou for (b = 0; b < GDP_NODE_NB_BANK; b++) { 2782d61f272SVincent Abriou seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 2792d61f272SVincent Abriou gdp_node_dump_node(s, gdp->node_list[b].top_field); 2802d61f272SVincent Abriou seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 2812d61f272SVincent Abriou gdp_node_dump_node(s, gdp->node_list[b].btm_field); 2822d61f272SVincent Abriou } 2832d61f272SVincent Abriou 2842d61f272SVincent Abriou return 0; 2852d61f272SVincent Abriou } 2862d61f272SVincent Abriou 2872d61f272SVincent Abriou static struct drm_info_list gdp0_debugfs_files[] = { 2882d61f272SVincent Abriou { "gdp0", gdp_dbg_show, 0, NULL }, 2892d61f272SVincent Abriou { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 2902d61f272SVincent Abriou }; 2912d61f272SVincent Abriou 2922d61f272SVincent Abriou static struct drm_info_list gdp1_debugfs_files[] = { 2932d61f272SVincent Abriou { "gdp1", gdp_dbg_show, 0, NULL }, 2942d61f272SVincent Abriou { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 2952d61f272SVincent Abriou }; 2962d61f272SVincent Abriou 2972d61f272SVincent Abriou static struct drm_info_list gdp2_debugfs_files[] = { 2982d61f272SVincent Abriou { "gdp2", gdp_dbg_show, 0, NULL }, 2992d61f272SVincent Abriou { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 3002d61f272SVincent Abriou }; 3012d61f272SVincent Abriou 3022d61f272SVincent Abriou static struct drm_info_list gdp3_debugfs_files[] = { 3032d61f272SVincent Abriou { "gdp3", gdp_dbg_show, 0, NULL }, 3042d61f272SVincent Abriou { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 3052d61f272SVincent Abriou }; 3062d61f272SVincent Abriou 3072d61f272SVincent Abriou static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 3082d61f272SVincent Abriou { 3092d61f272SVincent Abriou unsigned int i; 3102d61f272SVincent Abriou struct drm_info_list *gdp_debugfs_files; 3112d61f272SVincent Abriou int nb_files; 3122d61f272SVincent Abriou 3132d61f272SVincent Abriou switch (gdp->plane.desc) { 3142d61f272SVincent Abriou case STI_GDP_0: 3152d61f272SVincent Abriou gdp_debugfs_files = gdp0_debugfs_files; 3162d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp0_debugfs_files); 3172d61f272SVincent Abriou break; 3182d61f272SVincent Abriou case STI_GDP_1: 3192d61f272SVincent Abriou gdp_debugfs_files = gdp1_debugfs_files; 3202d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp1_debugfs_files); 3212d61f272SVincent Abriou break; 3222d61f272SVincent Abriou case STI_GDP_2: 3232d61f272SVincent Abriou gdp_debugfs_files = gdp2_debugfs_files; 3242d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp2_debugfs_files); 3252d61f272SVincent Abriou break; 3262d61f272SVincent Abriou case STI_GDP_3: 3272d61f272SVincent Abriou gdp_debugfs_files = gdp3_debugfs_files; 3282d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp3_debugfs_files); 3292d61f272SVincent Abriou break; 3302d61f272SVincent Abriou default: 3312d61f272SVincent Abriou return -EINVAL; 3322d61f272SVincent Abriou } 3332d61f272SVincent Abriou 3342d61f272SVincent Abriou for (i = 0; i < nb_files; i++) 3352d61f272SVincent Abriou gdp_debugfs_files[i].data = gdp; 3362d61f272SVincent Abriou 3372d61f272SVincent Abriou return drm_debugfs_create_files(gdp_debugfs_files, 3382d61f272SVincent Abriou nb_files, 3392d61f272SVincent Abriou minor->debugfs_root, minor); 3402d61f272SVincent Abriou } 3412d61f272SVincent Abriou 342ba2d53fbSBenjamin Gaignard static int sti_gdp_fourcc2format(int fourcc) 343ba2d53fbSBenjamin Gaignard { 344ba2d53fbSBenjamin Gaignard switch (fourcc) { 345ba2d53fbSBenjamin Gaignard case DRM_FORMAT_XRGB8888: 346ba2d53fbSBenjamin Gaignard return GDP_RGB888_32; 3478adb5776SFabien Dessenne case DRM_FORMAT_XBGR8888: 3488adb5776SFabien Dessenne return GDP_XBGR8888; 349ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB8888: 350ba2d53fbSBenjamin Gaignard return GDP_ARGB8888; 3514af6b12aSBenjamin Gaignard case DRM_FORMAT_ABGR8888: 3524af6b12aSBenjamin Gaignard return GDP_ABGR8888; 353ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB4444: 354ba2d53fbSBenjamin Gaignard return GDP_ARGB4444; 355ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB1555: 356ba2d53fbSBenjamin Gaignard return GDP_ARGB1555; 357ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB565: 358ba2d53fbSBenjamin Gaignard return GDP_RGB565; 359ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB888: 360ba2d53fbSBenjamin Gaignard return GDP_RGB888; 361ba2d53fbSBenjamin Gaignard } 362ba2d53fbSBenjamin Gaignard return -1; 363ba2d53fbSBenjamin Gaignard } 364ba2d53fbSBenjamin Gaignard 365ba2d53fbSBenjamin Gaignard static int sti_gdp_get_alpharange(int format) 366ba2d53fbSBenjamin Gaignard { 367ba2d53fbSBenjamin Gaignard switch (format) { 368ba2d53fbSBenjamin Gaignard case GDP_ARGB8565: 369ba2d53fbSBenjamin Gaignard case GDP_ARGB8888: 3704af6b12aSBenjamin Gaignard case GDP_ABGR8888: 371ba2d53fbSBenjamin Gaignard return GAM_GDP_ALPHARANGE_255; 372ba2d53fbSBenjamin Gaignard } 373ba2d53fbSBenjamin Gaignard return 0; 374ba2d53fbSBenjamin Gaignard } 375ba2d53fbSBenjamin Gaignard 376ba2d53fbSBenjamin Gaignard /** 377ba2d53fbSBenjamin Gaignard * sti_gdp_get_free_nodes 37829d1dc62SVincent Abriou * @gdp: gdp pointer 379ba2d53fbSBenjamin Gaignard * 380ba2d53fbSBenjamin Gaignard * Look for a GDP node list that is not currently read by the HW. 381ba2d53fbSBenjamin Gaignard * 382ba2d53fbSBenjamin Gaignard * RETURNS: 383ba2d53fbSBenjamin Gaignard * Pointer to the free GDP node list 384ba2d53fbSBenjamin Gaignard */ 38529d1dc62SVincent Abriou static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 386ba2d53fbSBenjamin Gaignard { 387ba2d53fbSBenjamin Gaignard int hw_nvn; 388ba2d53fbSBenjamin Gaignard unsigned int i; 389ba2d53fbSBenjamin Gaignard 390871bcdfeSVincent Abriou hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 391ba2d53fbSBenjamin Gaignard if (!hw_nvn) 392ba2d53fbSBenjamin Gaignard goto end; 393ba2d53fbSBenjamin Gaignard 394ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) 395a51fe84dSBenjamin Gaignard if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 396a51fe84dSBenjamin Gaignard (hw_nvn != gdp->node_list[i].top_field_paddr)) 397ba2d53fbSBenjamin Gaignard return &gdp->node_list[i]; 398ba2d53fbSBenjamin Gaignard 399d219673dSBenjamin Gaignard /* in hazardious cases restart with the first node */ 400d219673dSBenjamin Gaignard DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 40129d1dc62SVincent Abriou sti_plane_to_str(&gdp->plane), hw_nvn); 402d219673dSBenjamin Gaignard 403ba2d53fbSBenjamin Gaignard end: 404ba2d53fbSBenjamin Gaignard return &gdp->node_list[0]; 405ba2d53fbSBenjamin Gaignard } 406ba2d53fbSBenjamin Gaignard 407ba2d53fbSBenjamin Gaignard /** 408ba2d53fbSBenjamin Gaignard * sti_gdp_get_current_nodes 40929d1dc62SVincent Abriou * @gdp: gdp pointer 410ba2d53fbSBenjamin Gaignard * 411ba2d53fbSBenjamin Gaignard * Look for GDP nodes that are currently read by the HW. 412ba2d53fbSBenjamin Gaignard * 413ba2d53fbSBenjamin Gaignard * RETURNS: 414ba2d53fbSBenjamin Gaignard * Pointer to the current GDP node list 415ba2d53fbSBenjamin Gaignard */ 416ba2d53fbSBenjamin Gaignard static 41729d1dc62SVincent Abriou struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 418ba2d53fbSBenjamin Gaignard { 419ba2d53fbSBenjamin Gaignard int hw_nvn; 420ba2d53fbSBenjamin Gaignard unsigned int i; 421ba2d53fbSBenjamin Gaignard 422871bcdfeSVincent Abriou hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 423ba2d53fbSBenjamin Gaignard if (!hw_nvn) 424ba2d53fbSBenjamin Gaignard goto end; 425ba2d53fbSBenjamin Gaignard 426ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) 427a51fe84dSBenjamin Gaignard if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 428a51fe84dSBenjamin Gaignard (hw_nvn == gdp->node_list[i].top_field_paddr)) 429ba2d53fbSBenjamin Gaignard return &gdp->node_list[i]; 430ba2d53fbSBenjamin Gaignard 431ba2d53fbSBenjamin Gaignard end: 432d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 43329d1dc62SVincent Abriou hw_nvn, sti_plane_to_str(&gdp->plane)); 434d219673dSBenjamin Gaignard 435ba2d53fbSBenjamin Gaignard return NULL; 436ba2d53fbSBenjamin Gaignard } 437ba2d53fbSBenjamin Gaignard 438ba2d53fbSBenjamin Gaignard /** 439871bcdfeSVincent Abriou * sti_gdp_disable 44029d1dc62SVincent Abriou * @gdp: gdp pointer 441ba2d53fbSBenjamin Gaignard * 442ba2d53fbSBenjamin Gaignard * Disable a GDP. 443ba2d53fbSBenjamin Gaignard */ 44429d1dc62SVincent Abriou static void sti_gdp_disable(struct sti_gdp *gdp) 445ba2d53fbSBenjamin Gaignard { 44629d1dc62SVincent Abriou unsigned int i; 447d219673dSBenjamin Gaignard 44829d1dc62SVincent Abriou DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 449ba2d53fbSBenjamin Gaignard 450ba2d53fbSBenjamin Gaignard /* Set the nodes as 'to be ignored on mixer' */ 451ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) { 452ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 453ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 454ba2d53fbSBenjamin Gaignard } 455ba2d53fbSBenjamin Gaignard 45620c47601Sbenjamin.gaignard@linaro.org if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 457d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 458d219673dSBenjamin Gaignard 459ba2d53fbSBenjamin Gaignard if (gdp->clk_pix) 460ba2d53fbSBenjamin Gaignard clk_disable_unprepare(gdp->clk_pix); 461ba2d53fbSBenjamin Gaignard 46229d1dc62SVincent Abriou gdp->plane.status = STI_PLANE_DISABLED; 46300b517e5SFabien Dessenne gdp->vtg = NULL; 464ba2d53fbSBenjamin Gaignard } 465ba2d53fbSBenjamin Gaignard 466ba2d53fbSBenjamin Gaignard /** 467ba2d53fbSBenjamin Gaignard * sti_gdp_field_cb 468ba2d53fbSBenjamin Gaignard * @nb: notifier block 469ba2d53fbSBenjamin Gaignard * @event: event message 470ba2d53fbSBenjamin Gaignard * @data: private data 471ba2d53fbSBenjamin Gaignard * 472ba2d53fbSBenjamin Gaignard * Handle VTG top field and bottom field event. 473ba2d53fbSBenjamin Gaignard * 474ba2d53fbSBenjamin Gaignard * RETURNS: 475ba2d53fbSBenjamin Gaignard * 0 on success. 476ba2d53fbSBenjamin Gaignard */ 477bdfd36efSVille Syrjälä static int sti_gdp_field_cb(struct notifier_block *nb, 478ba2d53fbSBenjamin Gaignard unsigned long event, void *data) 479ba2d53fbSBenjamin Gaignard { 480ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 481ba2d53fbSBenjamin Gaignard 48229d1dc62SVincent Abriou if (gdp->plane.status == STI_PLANE_FLUSHING) { 48329d1dc62SVincent Abriou /* disable need to be synchronize on vsync event */ 48429d1dc62SVincent Abriou DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 48529d1dc62SVincent Abriou sti_plane_to_str(&gdp->plane)); 48629d1dc62SVincent Abriou 48729d1dc62SVincent Abriou sti_gdp_disable(gdp); 48829d1dc62SVincent Abriou } 48929d1dc62SVincent Abriou 490ba2d53fbSBenjamin Gaignard switch (event) { 491ba2d53fbSBenjamin Gaignard case VTG_TOP_FIELD_EVENT: 492ba2d53fbSBenjamin Gaignard gdp->is_curr_top = true; 493ba2d53fbSBenjamin Gaignard break; 494ba2d53fbSBenjamin Gaignard case VTG_BOTTOM_FIELD_EVENT: 495ba2d53fbSBenjamin Gaignard gdp->is_curr_top = false; 496ba2d53fbSBenjamin Gaignard break; 497ba2d53fbSBenjamin Gaignard default: 498ba2d53fbSBenjamin Gaignard DRM_ERROR("unsupported event: %lu\n", event); 499ba2d53fbSBenjamin Gaignard break; 500ba2d53fbSBenjamin Gaignard } 501ba2d53fbSBenjamin Gaignard 502ba2d53fbSBenjamin Gaignard return 0; 503ba2d53fbSBenjamin Gaignard } 504ba2d53fbSBenjamin Gaignard 505871bcdfeSVincent Abriou static void sti_gdp_init(struct sti_gdp *gdp) 506ba2d53fbSBenjamin Gaignard { 507871bcdfeSVincent Abriou struct device_node *np = gdp->dev->of_node; 508a51fe84dSBenjamin Gaignard dma_addr_t dma_addr; 509ba2d53fbSBenjamin Gaignard void *base; 510ba2d53fbSBenjamin Gaignard unsigned int i, size; 511ba2d53fbSBenjamin Gaignard 512ba2d53fbSBenjamin Gaignard /* Allocate all the nodes within a single memory page */ 513ba2d53fbSBenjamin Gaignard size = sizeof(struct sti_gdp_node) * 514ba2d53fbSBenjamin Gaignard GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 515f6e45661SLuis R. Rodriguez base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA); 516a51fe84dSBenjamin Gaignard 517ba2d53fbSBenjamin Gaignard if (!base) { 518ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP node\n"); 519ba2d53fbSBenjamin Gaignard return; 520ba2d53fbSBenjamin Gaignard } 521ba2d53fbSBenjamin Gaignard memset(base, 0, size); 522ba2d53fbSBenjamin Gaignard 523ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) { 524a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) { 525ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n"); 526ba2d53fbSBenjamin Gaignard return; 527ba2d53fbSBenjamin Gaignard } 528ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field = base; 529a51fe84dSBenjamin Gaignard gdp->node_list[i].top_field_paddr = dma_addr; 530a51fe84dSBenjamin Gaignard 531ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 532ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node); 533a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node); 534ba2d53fbSBenjamin Gaignard 535a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) { 536ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n"); 537ba2d53fbSBenjamin Gaignard return; 538ba2d53fbSBenjamin Gaignard } 539ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field = base; 540a51fe84dSBenjamin Gaignard gdp->node_list[i].btm_field_paddr = dma_addr; 541ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 542ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node); 543a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node); 544ba2d53fbSBenjamin Gaignard } 545ba2d53fbSBenjamin Gaignard 546ba2d53fbSBenjamin Gaignard if (of_device_is_compatible(np, "st,stih407-compositor")) { 547ba2d53fbSBenjamin Gaignard /* GDP of STiH407 chip have its own pixel clock */ 548ba2d53fbSBenjamin Gaignard char *clk_name; 549ba2d53fbSBenjamin Gaignard 550871bcdfeSVincent Abriou switch (gdp->plane.desc) { 551ba2d53fbSBenjamin Gaignard case STI_GDP_0: 552ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp1"; 553ba2d53fbSBenjamin Gaignard break; 554ba2d53fbSBenjamin Gaignard case STI_GDP_1: 555ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp2"; 556ba2d53fbSBenjamin Gaignard break; 557ba2d53fbSBenjamin Gaignard case STI_GDP_2: 558ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp3"; 559ba2d53fbSBenjamin Gaignard break; 560ba2d53fbSBenjamin Gaignard case STI_GDP_3: 561ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp4"; 562ba2d53fbSBenjamin Gaignard break; 563ba2d53fbSBenjamin Gaignard default: 564ba2d53fbSBenjamin Gaignard DRM_ERROR("GDP id not recognized\n"); 565ba2d53fbSBenjamin Gaignard return; 566ba2d53fbSBenjamin Gaignard } 567ba2d53fbSBenjamin Gaignard 568871bcdfeSVincent Abriou gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 569ba2d53fbSBenjamin Gaignard if (IS_ERR(gdp->clk_pix)) 570ba2d53fbSBenjamin Gaignard DRM_ERROR("Cannot get %s clock\n", clk_name); 5715e03abc5SBenjamin Gaignard 572871bcdfeSVincent Abriou gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 5735e03abc5SBenjamin Gaignard if (IS_ERR(gdp->clk_main_parent)) 5745e03abc5SBenjamin Gaignard DRM_ERROR("Cannot get main_parent clock\n"); 5755e03abc5SBenjamin Gaignard 576871bcdfeSVincent Abriou gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 5775e03abc5SBenjamin Gaignard if (IS_ERR(gdp->clk_aux_parent)) 5785e03abc5SBenjamin Gaignard DRM_ERROR("Cannot get aux_parent clock\n"); 579ba2d53fbSBenjamin Gaignard } 580ba2d53fbSBenjamin Gaignard } 581ba2d53fbSBenjamin Gaignard 582a5b9a713SBich Hemon /** 583a5b9a713SBich Hemon * sti_gdp_get_dst 584a5b9a713SBich Hemon * @dev: device 585a5b9a713SBich Hemon * @dst: requested destination size 586a5b9a713SBich Hemon * @src: source size 587a5b9a713SBich Hemon * 588a5b9a713SBich Hemon * Return the cropped / clamped destination size 589a5b9a713SBich Hemon * 590a5b9a713SBich Hemon * RETURNS: 591a5b9a713SBich Hemon * cropped / clamped destination size 592a5b9a713SBich Hemon */ 593a5b9a713SBich Hemon static int sti_gdp_get_dst(struct device *dev, int dst, int src) 59429d1dc62SVincent Abriou { 595a5b9a713SBich Hemon if (dst == src) 596a5b9a713SBich Hemon return dst; 597a5b9a713SBich Hemon 598a5b9a713SBich Hemon if (dst < src) { 599a5b9a713SBich Hemon dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 600a5b9a713SBich Hemon return dst; 601a5b9a713SBich Hemon } 602a5b9a713SBich Hemon 603a5b9a713SBich Hemon dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 604a5b9a713SBich Hemon return src; 605a5b9a713SBich Hemon } 606a5b9a713SBich Hemon 607dd86dc2fSVincent Abriou static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 608dd86dc2fSVincent Abriou struct drm_plane_state *state) 609dd86dc2fSVincent Abriou { 61029d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane); 61129d1dc62SVincent Abriou struct sti_gdp *gdp = to_sti_gdp(plane); 61229d1dc62SVincent Abriou struct drm_crtc *crtc = state->crtc; 61329d1dc62SVincent Abriou struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 61429d1dc62SVincent Abriou struct drm_framebuffer *fb = state->fb; 615dd86dc2fSVincent Abriou struct drm_crtc_state *crtc_state; 61629d1dc62SVincent Abriou struct sti_mixer *mixer; 61729d1dc62SVincent Abriou struct drm_display_mode *mode; 61829d1dc62SVincent Abriou int dst_x, dst_y, dst_w, dst_h; 61929d1dc62SVincent Abriou int src_x, src_y, src_w, src_h; 62029d1dc62SVincent Abriou int format; 62129d1dc62SVincent Abriou 622dd86dc2fSVincent Abriou /* no need for further checks if the plane is being disabled */ 623dd86dc2fSVincent Abriou if (!crtc || !fb) 624dd86dc2fSVincent Abriou return 0; 62529d1dc62SVincent Abriou 62629d1dc62SVincent Abriou mixer = to_sti_mixer(crtc); 627dd86dc2fSVincent Abriou crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 628dd86dc2fSVincent Abriou mode = &crtc_state->mode; 62929d1dc62SVincent Abriou dst_x = state->crtc_x; 63029d1dc62SVincent Abriou dst_y = state->crtc_y; 63129d1dc62SVincent Abriou dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 63229d1dc62SVincent Abriou dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 63329d1dc62SVincent Abriou /* src_x are in 16.16 format */ 63429d1dc62SVincent Abriou src_x = state->src_x >> 16; 63529d1dc62SVincent Abriou src_y = state->src_y >> 16; 636dd86dc2fSVincent Abriou src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); 637dd86dc2fSVincent Abriou src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); 63829d1dc62SVincent Abriou 63929d1dc62SVincent Abriou format = sti_gdp_fourcc2format(fb->pixel_format); 64029d1dc62SVincent Abriou if (format == -1) { 64129d1dc62SVincent Abriou DRM_ERROR("Format not supported by GDP %.4s\n", 64229d1dc62SVincent Abriou (char *)&fb->pixel_format); 643dd86dc2fSVincent Abriou return -EINVAL; 64429d1dc62SVincent Abriou } 64529d1dc62SVincent Abriou 646dd86dc2fSVincent Abriou if (!drm_fb_cma_get_gem_obj(fb, 0)) { 64729d1dc62SVincent Abriou DRM_ERROR("Can't get CMA GEM object for fb\n"); 648dd86dc2fSVincent Abriou return -EINVAL; 64929d1dc62SVincent Abriou } 65029d1dc62SVincent Abriou 65100b517e5SFabien Dessenne if (!gdp->vtg) { 65229d1dc62SVincent Abriou /* Register gdp callback */ 653ffdbb82cSFabien Dessenne gdp->vtg = compo->vtg[mixer->id]; 654dd86dc2fSVincent Abriou if (sti_vtg_register_client(gdp->vtg, 6552388693eSThierry Reding &gdp->vtg_field_nb, crtc)) { 65629d1dc62SVincent Abriou DRM_ERROR("Cannot register VTG notifier\n"); 657dd86dc2fSVincent Abriou return -EINVAL; 65829d1dc62SVincent Abriou } 65929d1dc62SVincent Abriou 66029d1dc62SVincent Abriou /* Set and enable gdp clock */ 66129d1dc62SVincent Abriou if (gdp->clk_pix) { 66229d1dc62SVincent Abriou struct clk *clkp; 66329d1dc62SVincent Abriou int rate = mode->clock * 1000; 664dd86dc2fSVincent Abriou int res; 66529d1dc62SVincent Abriou 666dd86dc2fSVincent Abriou /* 667dd86dc2fSVincent Abriou * According to the mixer used, the gdp pixel clock 668dd86dc2fSVincent Abriou * should have a different parent clock. 669dd86dc2fSVincent Abriou */ 67029d1dc62SVincent Abriou if (mixer->id == STI_MIXER_MAIN) 67129d1dc62SVincent Abriou clkp = gdp->clk_main_parent; 67229d1dc62SVincent Abriou else 67329d1dc62SVincent Abriou clkp = gdp->clk_aux_parent; 67429d1dc62SVincent Abriou 67529d1dc62SVincent Abriou if (clkp) 67629d1dc62SVincent Abriou clk_set_parent(gdp->clk_pix, clkp); 67729d1dc62SVincent Abriou 67829d1dc62SVincent Abriou res = clk_set_rate(gdp->clk_pix, rate); 67929d1dc62SVincent Abriou if (res < 0) { 68029d1dc62SVincent Abriou DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 68129d1dc62SVincent Abriou rate); 682dd86dc2fSVincent Abriou return -EINVAL; 68329d1dc62SVincent Abriou } 68429d1dc62SVincent Abriou 68529d1dc62SVincent Abriou if (clk_prepare_enable(gdp->clk_pix)) { 68629d1dc62SVincent Abriou DRM_ERROR("Failed to prepare/enable gdp\n"); 687dd86dc2fSVincent Abriou return -EINVAL; 688dd86dc2fSVincent Abriou } 689dd86dc2fSVincent Abriou } 690dd86dc2fSVincent Abriou } 691dd86dc2fSVincent Abriou 692dd86dc2fSVincent Abriou DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 693dd86dc2fSVincent Abriou crtc->base.id, sti_mixer_to_str(mixer), 694dd86dc2fSVincent Abriou drm_plane->base.id, sti_plane_to_str(plane)); 695dd86dc2fSVincent Abriou DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 696dd86dc2fSVincent Abriou sti_plane_to_str(plane), 697dd86dc2fSVincent Abriou dst_w, dst_h, dst_x, dst_y, 698dd86dc2fSVincent Abriou src_w, src_h, src_x, src_y); 699dd86dc2fSVincent Abriou 700dd86dc2fSVincent Abriou return 0; 701dd86dc2fSVincent Abriou } 702dd86dc2fSVincent Abriou 70329d1dc62SVincent Abriou static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 70429d1dc62SVincent Abriou struct drm_plane_state *oldstate) 70529d1dc62SVincent Abriou { 70629d1dc62SVincent Abriou struct drm_plane_state *state = drm_plane->state; 70729d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane); 70829d1dc62SVincent Abriou struct sti_gdp *gdp = to_sti_gdp(plane); 70929d1dc62SVincent Abriou struct drm_crtc *crtc = state->crtc; 71029d1dc62SVincent Abriou struct drm_framebuffer *fb = state->fb; 71129d1dc62SVincent Abriou struct drm_display_mode *mode; 71229d1dc62SVincent Abriou int dst_x, dst_y, dst_w, dst_h; 71329d1dc62SVincent Abriou int src_x, src_y, src_w, src_h; 71429d1dc62SVincent Abriou struct drm_gem_cma_object *cma_obj; 71529d1dc62SVincent Abriou struct sti_gdp_node_list *list; 71629d1dc62SVincent Abriou struct sti_gdp_node_list *curr_list; 71729d1dc62SVincent Abriou struct sti_gdp_node *top_field, *btm_field; 71829d1dc62SVincent Abriou u32 dma_updated_top; 71929d1dc62SVincent Abriou u32 dma_updated_btm; 72029d1dc62SVincent Abriou int format; 721d27cd40aSLaurent Pinchart unsigned int bpp; 72229d1dc62SVincent Abriou u32 ydo, xdo, yds, xds; 72329d1dc62SVincent Abriou 724dd86dc2fSVincent Abriou if (!crtc || !fb) 72529d1dc62SVincent Abriou return; 72629d1dc62SVincent Abriou 72729d1dc62SVincent Abriou mode = &crtc->mode; 72829d1dc62SVincent Abriou dst_x = state->crtc_x; 72929d1dc62SVincent Abriou dst_y = state->crtc_y; 73029d1dc62SVincent Abriou dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 73129d1dc62SVincent Abriou dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 73229d1dc62SVincent Abriou /* src_x are in 16.16 format */ 73329d1dc62SVincent Abriou src_x = state->src_x >> 16; 73429d1dc62SVincent Abriou src_y = state->src_y >> 16; 735a5b9a713SBich Hemon src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX); 736a5b9a713SBich Hemon src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX); 73729d1dc62SVincent Abriou 73829d1dc62SVincent Abriou list = sti_gdp_get_free_nodes(gdp); 73929d1dc62SVincent Abriou top_field = list->top_field; 74029d1dc62SVincent Abriou btm_field = list->btm_field; 74129d1dc62SVincent Abriou 74229d1dc62SVincent Abriou dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 74329d1dc62SVincent Abriou sti_plane_to_str(plane), top_field, btm_field); 74429d1dc62SVincent Abriou 74529d1dc62SVincent Abriou /* build the top field */ 74629d1dc62SVincent Abriou top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 74729d1dc62SVincent Abriou top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 74829d1dc62SVincent Abriou format = sti_gdp_fourcc2format(fb->pixel_format); 74929d1dc62SVincent Abriou top_field->gam_gdp_ctl |= format; 75029d1dc62SVincent Abriou top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 75129d1dc62SVincent Abriou top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 75229d1dc62SVincent Abriou 75329d1dc62SVincent Abriou cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 75429d1dc62SVincent Abriou 75529d1dc62SVincent Abriou DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 75629d1dc62SVincent Abriou (char *)&fb->pixel_format, 75729d1dc62SVincent Abriou (unsigned long)cma_obj->paddr); 75829d1dc62SVincent Abriou 75929d1dc62SVincent Abriou /* pixel memory location */ 760d27cd40aSLaurent Pinchart bpp = drm_format_plane_cpp(fb->pixel_format, 0); 76129d1dc62SVincent Abriou top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 762d27cd40aSLaurent Pinchart top_field->gam_gdp_pml += src_x * bpp; 76329d1dc62SVincent Abriou top_field->gam_gdp_pml += src_y * fb->pitches[0]; 76429d1dc62SVincent Abriou 765a5b9a713SBich Hemon /* output parameters (clamped / cropped) */ 766a5b9a713SBich Hemon dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 767a5b9a713SBich Hemon dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 76829d1dc62SVincent Abriou ydo = sti_vtg_get_line_number(*mode, dst_y); 76929d1dc62SVincent Abriou yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 77029d1dc62SVincent Abriou xdo = sti_vtg_get_pixel_number(*mode, dst_x); 77129d1dc62SVincent Abriou xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 77229d1dc62SVincent Abriou top_field->gam_gdp_vpo = (ydo << 16) | xdo; 77329d1dc62SVincent Abriou top_field->gam_gdp_vps = (yds << 16) | xds; 77429d1dc62SVincent Abriou 775704cb30cSVincent Abriou /* input parameters */ 776704cb30cSVincent Abriou src_w = dst_w; 777704cb30cSVincent Abriou top_field->gam_gdp_pmp = fb->pitches[0]; 778704cb30cSVincent Abriou top_field->gam_gdp_size = src_h << 16 | src_w; 779704cb30cSVincent Abriou 78029d1dc62SVincent Abriou /* Same content and chained together */ 78129d1dc62SVincent Abriou memcpy(btm_field, top_field, sizeof(*btm_field)); 78229d1dc62SVincent Abriou top_field->gam_gdp_nvn = list->btm_field_paddr; 78329d1dc62SVincent Abriou btm_field->gam_gdp_nvn = list->top_field_paddr; 78429d1dc62SVincent Abriou 78529d1dc62SVincent Abriou /* Interlaced mode */ 78629d1dc62SVincent Abriou if (mode->flags & DRM_MODE_FLAG_INTERLACE) 78729d1dc62SVincent Abriou btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 78829d1dc62SVincent Abriou fb->pitches[0]; 78929d1dc62SVincent Abriou 79029d1dc62SVincent Abriou /* Update the NVN field of the 'right' field of the current GDP node 79129d1dc62SVincent Abriou * (being used by the HW) with the address of the updated ('free') top 79229d1dc62SVincent Abriou * field GDP node. 79329d1dc62SVincent Abriou * - In interlaced mode the 'right' field is the bottom field as we 79429d1dc62SVincent Abriou * update frames starting from their top field 79529d1dc62SVincent Abriou * - In progressive mode, we update both bottom and top fields which 79629d1dc62SVincent Abriou * are equal nodes. 79729d1dc62SVincent Abriou * At the next VSYNC, the updated node list will be used by the HW. 79829d1dc62SVincent Abriou */ 79929d1dc62SVincent Abriou curr_list = sti_gdp_get_current_nodes(gdp); 80029d1dc62SVincent Abriou dma_updated_top = list->top_field_paddr; 80129d1dc62SVincent Abriou dma_updated_btm = list->btm_field_paddr; 80229d1dc62SVincent Abriou 80329d1dc62SVincent Abriou dev_dbg(gdp->dev, "Current NVN:0x%X\n", 80429d1dc62SVincent Abriou readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 80529d1dc62SVincent Abriou dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 80629d1dc62SVincent Abriou (unsigned long)cma_obj->paddr, 80729d1dc62SVincent Abriou readl(gdp->regs + GAM_GDP_PML_OFFSET)); 80829d1dc62SVincent Abriou 80929d1dc62SVincent Abriou if (!curr_list) { 81029d1dc62SVincent Abriou /* First update or invalid node should directly write in the 81129d1dc62SVincent Abriou * hw register */ 81229ffa776SFabien Dessenne DRM_DEBUG_DRIVER("%s first update (or invalid node)\n", 81329d1dc62SVincent Abriou sti_plane_to_str(plane)); 81429d1dc62SVincent Abriou 81529d1dc62SVincent Abriou writel(gdp->is_curr_top ? 81629d1dc62SVincent Abriou dma_updated_btm : dma_updated_top, 81729d1dc62SVincent Abriou gdp->regs + GAM_GDP_NVN_OFFSET); 81829d1dc62SVincent Abriou goto end; 81929d1dc62SVincent Abriou } 82029d1dc62SVincent Abriou 82129d1dc62SVincent Abriou if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 82229d1dc62SVincent Abriou if (gdp->is_curr_top) { 82329d1dc62SVincent Abriou /* Do not update in the middle of the frame, but 82429d1dc62SVincent Abriou * postpone the update after the bottom field has 82529d1dc62SVincent Abriou * been displayed */ 82629d1dc62SVincent Abriou curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 82729d1dc62SVincent Abriou } else { 82829d1dc62SVincent Abriou /* Direct update to avoid one frame delay */ 82929d1dc62SVincent Abriou writel(dma_updated_top, 83029d1dc62SVincent Abriou gdp->regs + GAM_GDP_NVN_OFFSET); 83129d1dc62SVincent Abriou } 83229d1dc62SVincent Abriou } else { 83329d1dc62SVincent Abriou /* Direct update for progressive to avoid one frame delay */ 83429d1dc62SVincent Abriou writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 83529d1dc62SVincent Abriou } 83629d1dc62SVincent Abriou 83729d1dc62SVincent Abriou end: 838bf8f9e4aSVincent Abriou sti_plane_update_fps(plane, true, false); 839bf8f9e4aSVincent Abriou 84029d1dc62SVincent Abriou plane->status = STI_PLANE_UPDATED; 84129d1dc62SVincent Abriou } 84229d1dc62SVincent Abriou 84329d1dc62SVincent Abriou static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 84429d1dc62SVincent Abriou struct drm_plane_state *oldstate) 84529d1dc62SVincent Abriou { 84629d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane); 84729d1dc62SVincent Abriou 8485552aad3SFabien Dessenne if (!oldstate->crtc) { 84929d1dc62SVincent Abriou DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 85029d1dc62SVincent Abriou drm_plane->base.id); 85129d1dc62SVincent Abriou return; 85229d1dc62SVincent Abriou } 85329d1dc62SVincent Abriou 85429d1dc62SVincent Abriou DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 8555552aad3SFabien Dessenne oldstate->crtc->base.id, 8565552aad3SFabien Dessenne sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 85729d1dc62SVincent Abriou drm_plane->base.id, sti_plane_to_str(plane)); 85829d1dc62SVincent Abriou 85929d1dc62SVincent Abriou plane->status = STI_PLANE_DISABLING; 86029d1dc62SVincent Abriou } 86129d1dc62SVincent Abriou 86229d1dc62SVincent Abriou static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 863dd86dc2fSVincent Abriou .atomic_check = sti_gdp_atomic_check, 86429d1dc62SVincent Abriou .atomic_update = sti_gdp_atomic_update, 86529d1dc62SVincent Abriou .atomic_disable = sti_gdp_atomic_disable, 866ba2d53fbSBenjamin Gaignard }; 867ba2d53fbSBenjamin Gaignard 86883af0a48SBenjamin Gaignard static void sti_gdp_destroy(struct drm_plane *drm_plane) 86983af0a48SBenjamin Gaignard { 87083af0a48SBenjamin Gaignard DRM_DEBUG_DRIVER("\n"); 87183af0a48SBenjamin Gaignard 87283af0a48SBenjamin Gaignard drm_plane_helper_disable(drm_plane); 87383af0a48SBenjamin Gaignard drm_plane_cleanup(drm_plane); 87483af0a48SBenjamin Gaignard } 87583af0a48SBenjamin Gaignard 87683af0a48SBenjamin Gaignard static int sti_gdp_late_register(struct drm_plane *drm_plane) 87783af0a48SBenjamin Gaignard { 87883af0a48SBenjamin Gaignard struct sti_plane *plane = to_sti_plane(drm_plane); 87983af0a48SBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(plane); 88083af0a48SBenjamin Gaignard 88183af0a48SBenjamin Gaignard return gdp_debugfs_init(gdp, drm_plane->dev->primary); 88283af0a48SBenjamin Gaignard } 88383af0a48SBenjamin Gaignard 884bdfd36efSVille Syrjälä static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 88583af0a48SBenjamin Gaignard .update_plane = drm_atomic_helper_update_plane, 88683af0a48SBenjamin Gaignard .disable_plane = drm_atomic_helper_disable_plane, 88783af0a48SBenjamin Gaignard .destroy = sti_gdp_destroy, 888bbd1e3a5SBenjamin Gaignard .set_property = drm_atomic_helper_plane_set_property, 889bbd1e3a5SBenjamin Gaignard .reset = sti_plane_reset, 89083af0a48SBenjamin Gaignard .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 89183af0a48SBenjamin Gaignard .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 89283af0a48SBenjamin Gaignard .late_register = sti_gdp_late_register, 89383af0a48SBenjamin Gaignard }; 89483af0a48SBenjamin Gaignard 89529d1dc62SVincent Abriou struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 89629d1dc62SVincent Abriou struct device *dev, int desc, 89729d1dc62SVincent Abriou void __iomem *baseaddr, 89829d1dc62SVincent Abriou unsigned int possible_crtcs, 89929d1dc62SVincent Abriou enum drm_plane_type type) 900ba2d53fbSBenjamin Gaignard { 901ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp; 90229d1dc62SVincent Abriou int res; 903ba2d53fbSBenjamin Gaignard 904ba2d53fbSBenjamin Gaignard gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 905ba2d53fbSBenjamin Gaignard if (!gdp) { 906ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP\n"); 907ba2d53fbSBenjamin Gaignard return NULL; 908ba2d53fbSBenjamin Gaignard } 909ba2d53fbSBenjamin Gaignard 910871bcdfeSVincent Abriou gdp->dev = dev; 911871bcdfeSVincent Abriou gdp->regs = baseaddr; 912871bcdfeSVincent Abriou gdp->plane.desc = desc; 91329d1dc62SVincent Abriou gdp->plane.status = STI_PLANE_DISABLED; 914871bcdfeSVincent Abriou 915ba2d53fbSBenjamin Gaignard gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 916ba2d53fbSBenjamin Gaignard 917871bcdfeSVincent Abriou sti_gdp_init(gdp); 918871bcdfeSVincent Abriou 91929d1dc62SVincent Abriou res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 92029d1dc62SVincent Abriou possible_crtcs, 92183af0a48SBenjamin Gaignard &sti_gdp_plane_helpers_funcs, 92229d1dc62SVincent Abriou gdp_supported_formats, 92329d1dc62SVincent Abriou ARRAY_SIZE(gdp_supported_formats), 924b0b3b795SVille Syrjälä type, NULL); 92529d1dc62SVincent Abriou if (res) { 92629d1dc62SVincent Abriou DRM_ERROR("Failed to initialize universal plane\n"); 92729d1dc62SVincent Abriou goto err; 92829d1dc62SVincent Abriou } 92929d1dc62SVincent Abriou 93029d1dc62SVincent Abriou drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 93129d1dc62SVincent Abriou 93229d1dc62SVincent Abriou sti_plane_init_property(&gdp->plane, type); 93329d1dc62SVincent Abriou 93429d1dc62SVincent Abriou return &gdp->plane.drm_plane; 93529d1dc62SVincent Abriou 93629d1dc62SVincent Abriou err: 93729d1dc62SVincent Abriou devm_kfree(dev, gdp); 93829d1dc62SVincent Abriou return NULL; 939ba2d53fbSBenjamin Gaignard } 940