1ba2d53fbSBenjamin Gaignard /* 2ba2d53fbSBenjamin Gaignard * Copyright (C) STMicroelectronics SA 2014 3ba2d53fbSBenjamin Gaignard * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4ba2d53fbSBenjamin Gaignard * Fabien Dessenne <fabien.dessenne@st.com> 5ba2d53fbSBenjamin Gaignard * for STMicroelectronics. 6ba2d53fbSBenjamin Gaignard * License terms: GNU General Public License (GPL), version 2 7ba2d53fbSBenjamin Gaignard */ 8ba2d53fbSBenjamin Gaignard 9ba2d53fbSBenjamin Gaignard #include <linux/clk.h> 10ba2d53fbSBenjamin Gaignard #include <linux/dma-mapping.h> 11ba2d53fbSBenjamin Gaignard 12d219673dSBenjamin Gaignard #include "sti_compositor.h" 13ba2d53fbSBenjamin Gaignard #include "sti_gdp.h" 14ba2d53fbSBenjamin Gaignard #include "sti_layer.h" 15ba2d53fbSBenjamin Gaignard #include "sti_vtg.h" 16ba2d53fbSBenjamin Gaignard 17ba2d53fbSBenjamin Gaignard #define ENA_COLOR_FILL BIT(8) 18ba2d53fbSBenjamin Gaignard #define WAIT_NEXT_VSYNC BIT(31) 19ba2d53fbSBenjamin Gaignard 20ba2d53fbSBenjamin Gaignard /* GDP color formats */ 21ba2d53fbSBenjamin Gaignard #define GDP_RGB565 0x00 22ba2d53fbSBenjamin Gaignard #define GDP_RGB888 0x01 23ba2d53fbSBenjamin Gaignard #define GDP_RGB888_32 0x02 24ba2d53fbSBenjamin Gaignard #define GDP_ARGB8565 0x04 25ba2d53fbSBenjamin Gaignard #define GDP_ARGB8888 0x05 26ba2d53fbSBenjamin Gaignard #define GDP_ARGB1555 0x06 27ba2d53fbSBenjamin Gaignard #define GDP_ARGB4444 0x07 28ba2d53fbSBenjamin Gaignard #define GDP_CLUT8 0x0B 29ba2d53fbSBenjamin Gaignard #define GDP_YCBR888 0x10 30ba2d53fbSBenjamin Gaignard #define GDP_YCBR422R 0x12 31ba2d53fbSBenjamin Gaignard #define GDP_AYCBR8888 0x15 32ba2d53fbSBenjamin Gaignard 33ba2d53fbSBenjamin Gaignard #define GAM_GDP_CTL_OFFSET 0x00 34ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_OFFSET 0x04 35ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPO_OFFSET 0x0C 36ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPS_OFFSET 0x10 37ba2d53fbSBenjamin Gaignard #define GAM_GDP_PML_OFFSET 0x14 38ba2d53fbSBenjamin Gaignard #define GAM_GDP_PMP_OFFSET 0x18 39ba2d53fbSBenjamin Gaignard #define GAM_GDP_SIZE_OFFSET 0x1C 40ba2d53fbSBenjamin Gaignard #define GAM_GDP_NVN_OFFSET 0x24 41ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY1_OFFSET 0x28 42ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY2_OFFSET 0x2C 43ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_OFFSET 0x34 44ba2d53fbSBenjamin Gaignard #define GAM_GDP_CML_OFFSET 0x3C 45ba2d53fbSBenjamin Gaignard #define GAM_GDP_MST_OFFSET 0x68 46ba2d53fbSBenjamin Gaignard 47ba2d53fbSBenjamin Gaignard #define GAM_GDP_ALPHARANGE_255 BIT(5) 48ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_FULL_RANGE 0x00808080 49ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 50ba2d53fbSBenjamin Gaignard #define GAM_GDP_SIZE_MAX 0x7FF 51ba2d53fbSBenjamin Gaignard 52ba2d53fbSBenjamin Gaignard #define GDP_NODE_NB_BANK 2 53ba2d53fbSBenjamin Gaignard #define GDP_NODE_PER_FIELD 2 54ba2d53fbSBenjamin Gaignard 55ba2d53fbSBenjamin Gaignard struct sti_gdp_node { 56ba2d53fbSBenjamin Gaignard u32 gam_gdp_ctl; 57ba2d53fbSBenjamin Gaignard u32 gam_gdp_agc; 58ba2d53fbSBenjamin Gaignard u32 reserved1; 59ba2d53fbSBenjamin Gaignard u32 gam_gdp_vpo; 60ba2d53fbSBenjamin Gaignard u32 gam_gdp_vps; 61ba2d53fbSBenjamin Gaignard u32 gam_gdp_pml; 62ba2d53fbSBenjamin Gaignard u32 gam_gdp_pmp; 63ba2d53fbSBenjamin Gaignard u32 gam_gdp_size; 64ba2d53fbSBenjamin Gaignard u32 reserved2; 65ba2d53fbSBenjamin Gaignard u32 gam_gdp_nvn; 66ba2d53fbSBenjamin Gaignard u32 gam_gdp_key1; 67ba2d53fbSBenjamin Gaignard u32 gam_gdp_key2; 68ba2d53fbSBenjamin Gaignard u32 reserved3; 69ba2d53fbSBenjamin Gaignard u32 gam_gdp_ppt; 70ba2d53fbSBenjamin Gaignard u32 reserved4; 71ba2d53fbSBenjamin Gaignard u32 gam_gdp_cml; 72ba2d53fbSBenjamin Gaignard }; 73ba2d53fbSBenjamin Gaignard 74ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list { 75ba2d53fbSBenjamin Gaignard struct sti_gdp_node *top_field; 76a51fe84dSBenjamin Gaignard dma_addr_t top_field_paddr; 77ba2d53fbSBenjamin Gaignard struct sti_gdp_node *btm_field; 78a51fe84dSBenjamin Gaignard dma_addr_t btm_field_paddr; 79ba2d53fbSBenjamin Gaignard }; 80ba2d53fbSBenjamin Gaignard 81ba2d53fbSBenjamin Gaignard /** 82ba2d53fbSBenjamin Gaignard * STI GDP structure 83ba2d53fbSBenjamin Gaignard * 84ba2d53fbSBenjamin Gaignard * @layer: layer structure 85ba2d53fbSBenjamin Gaignard * @clk_pix: pixel clock for the current gdp 86ba2d53fbSBenjamin Gaignard * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 87ba2d53fbSBenjamin Gaignard * @is_curr_top: true if the current node processed is the top field 88ba2d53fbSBenjamin Gaignard * @node_list: array of node list 89ba2d53fbSBenjamin Gaignard */ 90ba2d53fbSBenjamin Gaignard struct sti_gdp { 91ba2d53fbSBenjamin Gaignard struct sti_layer layer; 92ba2d53fbSBenjamin Gaignard struct clk *clk_pix; 93ba2d53fbSBenjamin Gaignard struct notifier_block vtg_field_nb; 94ba2d53fbSBenjamin Gaignard bool is_curr_top; 95ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 96ba2d53fbSBenjamin Gaignard }; 97ba2d53fbSBenjamin Gaignard 98ba2d53fbSBenjamin Gaignard #define to_sti_gdp(x) container_of(x, struct sti_gdp, layer) 99ba2d53fbSBenjamin Gaignard 100ba2d53fbSBenjamin Gaignard static const uint32_t gdp_supported_formats[] = { 101ba2d53fbSBenjamin Gaignard DRM_FORMAT_XRGB8888, 102ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB8888, 103ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB4444, 104ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB1555, 105ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB565, 106ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB888, 107ba2d53fbSBenjamin Gaignard DRM_FORMAT_AYUV, 108ba2d53fbSBenjamin Gaignard DRM_FORMAT_YUV444, 109ba2d53fbSBenjamin Gaignard DRM_FORMAT_VYUY, 110ba2d53fbSBenjamin Gaignard DRM_FORMAT_C8, 111ba2d53fbSBenjamin Gaignard }; 112ba2d53fbSBenjamin Gaignard 113ba2d53fbSBenjamin Gaignard static const uint32_t *sti_gdp_get_formats(struct sti_layer *layer) 114ba2d53fbSBenjamin Gaignard { 115ba2d53fbSBenjamin Gaignard return gdp_supported_formats; 116ba2d53fbSBenjamin Gaignard } 117ba2d53fbSBenjamin Gaignard 118ba2d53fbSBenjamin Gaignard static unsigned int sti_gdp_get_nb_formats(struct sti_layer *layer) 119ba2d53fbSBenjamin Gaignard { 120ba2d53fbSBenjamin Gaignard return ARRAY_SIZE(gdp_supported_formats); 121ba2d53fbSBenjamin Gaignard } 122ba2d53fbSBenjamin Gaignard 123ba2d53fbSBenjamin Gaignard static int sti_gdp_fourcc2format(int fourcc) 124ba2d53fbSBenjamin Gaignard { 125ba2d53fbSBenjamin Gaignard switch (fourcc) { 126ba2d53fbSBenjamin Gaignard case DRM_FORMAT_XRGB8888: 127ba2d53fbSBenjamin Gaignard return GDP_RGB888_32; 128ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB8888: 129ba2d53fbSBenjamin Gaignard return GDP_ARGB8888; 130ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB4444: 131ba2d53fbSBenjamin Gaignard return GDP_ARGB4444; 132ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB1555: 133ba2d53fbSBenjamin Gaignard return GDP_ARGB1555; 134ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB565: 135ba2d53fbSBenjamin Gaignard return GDP_RGB565; 136ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB888: 137ba2d53fbSBenjamin Gaignard return GDP_RGB888; 138ba2d53fbSBenjamin Gaignard case DRM_FORMAT_AYUV: 139ba2d53fbSBenjamin Gaignard return GDP_AYCBR8888; 140ba2d53fbSBenjamin Gaignard case DRM_FORMAT_YUV444: 141ba2d53fbSBenjamin Gaignard return GDP_YCBR888; 142ba2d53fbSBenjamin Gaignard case DRM_FORMAT_VYUY: 143ba2d53fbSBenjamin Gaignard return GDP_YCBR422R; 144ba2d53fbSBenjamin Gaignard case DRM_FORMAT_C8: 145ba2d53fbSBenjamin Gaignard return GDP_CLUT8; 146ba2d53fbSBenjamin Gaignard } 147ba2d53fbSBenjamin Gaignard return -1; 148ba2d53fbSBenjamin Gaignard } 149ba2d53fbSBenjamin Gaignard 150ba2d53fbSBenjamin Gaignard static int sti_gdp_get_alpharange(int format) 151ba2d53fbSBenjamin Gaignard { 152ba2d53fbSBenjamin Gaignard switch (format) { 153ba2d53fbSBenjamin Gaignard case GDP_ARGB8565: 154ba2d53fbSBenjamin Gaignard case GDP_ARGB8888: 155ba2d53fbSBenjamin Gaignard case GDP_AYCBR8888: 156ba2d53fbSBenjamin Gaignard return GAM_GDP_ALPHARANGE_255; 157ba2d53fbSBenjamin Gaignard } 158ba2d53fbSBenjamin Gaignard return 0; 159ba2d53fbSBenjamin Gaignard } 160ba2d53fbSBenjamin Gaignard 161ba2d53fbSBenjamin Gaignard /** 162ba2d53fbSBenjamin Gaignard * sti_gdp_get_free_nodes 163ba2d53fbSBenjamin Gaignard * @layer: gdp layer 164ba2d53fbSBenjamin Gaignard * 165ba2d53fbSBenjamin Gaignard * Look for a GDP node list that is not currently read by the HW. 166ba2d53fbSBenjamin Gaignard * 167ba2d53fbSBenjamin Gaignard * RETURNS: 168ba2d53fbSBenjamin Gaignard * Pointer to the free GDP node list 169ba2d53fbSBenjamin Gaignard */ 170ba2d53fbSBenjamin Gaignard static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_layer *layer) 171ba2d53fbSBenjamin Gaignard { 172ba2d53fbSBenjamin Gaignard int hw_nvn; 173ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(layer); 174ba2d53fbSBenjamin Gaignard unsigned int i; 175ba2d53fbSBenjamin Gaignard 176ba2d53fbSBenjamin Gaignard hw_nvn = readl(layer->regs + GAM_GDP_NVN_OFFSET); 177ba2d53fbSBenjamin Gaignard if (!hw_nvn) 178ba2d53fbSBenjamin Gaignard goto end; 179ba2d53fbSBenjamin Gaignard 180ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) 181a51fe84dSBenjamin Gaignard if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 182a51fe84dSBenjamin Gaignard (hw_nvn != gdp->node_list[i].top_field_paddr)) 183ba2d53fbSBenjamin Gaignard return &gdp->node_list[i]; 184ba2d53fbSBenjamin Gaignard 185d219673dSBenjamin Gaignard /* in hazardious cases restart with the first node */ 186d219673dSBenjamin Gaignard DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 187d219673dSBenjamin Gaignard sti_layer_to_str(layer), hw_nvn); 188d219673dSBenjamin Gaignard 189ba2d53fbSBenjamin Gaignard end: 190ba2d53fbSBenjamin Gaignard return &gdp->node_list[0]; 191ba2d53fbSBenjamin Gaignard } 192ba2d53fbSBenjamin Gaignard 193ba2d53fbSBenjamin Gaignard /** 194ba2d53fbSBenjamin Gaignard * sti_gdp_get_current_nodes 195ba2d53fbSBenjamin Gaignard * @layer: GDP layer 196ba2d53fbSBenjamin Gaignard * 197ba2d53fbSBenjamin Gaignard * Look for GDP nodes that are currently read by the HW. 198ba2d53fbSBenjamin Gaignard * 199ba2d53fbSBenjamin Gaignard * RETURNS: 200ba2d53fbSBenjamin Gaignard * Pointer to the current GDP node list 201ba2d53fbSBenjamin Gaignard */ 202ba2d53fbSBenjamin Gaignard static 203ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_layer *layer) 204ba2d53fbSBenjamin Gaignard { 205ba2d53fbSBenjamin Gaignard int hw_nvn; 206ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(layer); 207ba2d53fbSBenjamin Gaignard unsigned int i; 208ba2d53fbSBenjamin Gaignard 209ba2d53fbSBenjamin Gaignard hw_nvn = readl(layer->regs + GAM_GDP_NVN_OFFSET); 210ba2d53fbSBenjamin Gaignard if (!hw_nvn) 211ba2d53fbSBenjamin Gaignard goto end; 212ba2d53fbSBenjamin Gaignard 213ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) 214a51fe84dSBenjamin Gaignard if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 215a51fe84dSBenjamin Gaignard (hw_nvn == gdp->node_list[i].top_field_paddr)) 216ba2d53fbSBenjamin Gaignard return &gdp->node_list[i]; 217ba2d53fbSBenjamin Gaignard 218ba2d53fbSBenjamin Gaignard end: 219d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 220d219673dSBenjamin Gaignard hw_nvn, sti_layer_to_str(layer)); 221d219673dSBenjamin Gaignard 222ba2d53fbSBenjamin Gaignard return NULL; 223ba2d53fbSBenjamin Gaignard } 224ba2d53fbSBenjamin Gaignard 225ba2d53fbSBenjamin Gaignard /** 226ba2d53fbSBenjamin Gaignard * sti_gdp_prepare_layer 227ba2d53fbSBenjamin Gaignard * @lay: gdp layer 228ba2d53fbSBenjamin Gaignard * @first_prepare: true if it is the first time this function is called 229ba2d53fbSBenjamin Gaignard * 230ba2d53fbSBenjamin Gaignard * Update the free GDP node list according to the layer properties. 231ba2d53fbSBenjamin Gaignard * 232ba2d53fbSBenjamin Gaignard * RETURNS: 233ba2d53fbSBenjamin Gaignard * 0 on success. 234ba2d53fbSBenjamin Gaignard */ 235ba2d53fbSBenjamin Gaignard static int sti_gdp_prepare_layer(struct sti_layer *layer, bool first_prepare) 236ba2d53fbSBenjamin Gaignard { 237ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list *list; 238ba2d53fbSBenjamin Gaignard struct sti_gdp_node *top_field, *btm_field; 239ba2d53fbSBenjamin Gaignard struct drm_display_mode *mode = layer->mode; 240ba2d53fbSBenjamin Gaignard struct device *dev = layer->dev; 241ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(layer); 242d219673dSBenjamin Gaignard struct sti_compositor *compo = dev_get_drvdata(dev); 243ba2d53fbSBenjamin Gaignard int format; 244ba2d53fbSBenjamin Gaignard unsigned int depth, bpp; 245ba2d53fbSBenjamin Gaignard int rate = mode->clock * 1000; 246ba2d53fbSBenjamin Gaignard int res; 247ba2d53fbSBenjamin Gaignard u32 ydo, xdo, yds, xds; 248ba2d53fbSBenjamin Gaignard 249ba2d53fbSBenjamin Gaignard list = sti_gdp_get_free_nodes(layer); 250ba2d53fbSBenjamin Gaignard top_field = list->top_field; 251ba2d53fbSBenjamin Gaignard btm_field = list->btm_field; 252ba2d53fbSBenjamin Gaignard 253d219673dSBenjamin Gaignard dev_dbg(dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 254d219673dSBenjamin Gaignard sti_layer_to_str(layer), top_field, btm_field); 255d219673dSBenjamin Gaignard 256ba2d53fbSBenjamin Gaignard /* Build the top field from layer params */ 257ba2d53fbSBenjamin Gaignard top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 258ba2d53fbSBenjamin Gaignard top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 259ba2d53fbSBenjamin Gaignard format = sti_gdp_fourcc2format(layer->format); 260ba2d53fbSBenjamin Gaignard if (format == -1) { 261ba2d53fbSBenjamin Gaignard DRM_ERROR("Format not supported by GDP %.4s\n", 262ba2d53fbSBenjamin Gaignard (char *)&layer->format); 263ba2d53fbSBenjamin Gaignard return 1; 264ba2d53fbSBenjamin Gaignard } 265ba2d53fbSBenjamin Gaignard top_field->gam_gdp_ctl |= format; 266ba2d53fbSBenjamin Gaignard top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 267ba2d53fbSBenjamin Gaignard top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 268ba2d53fbSBenjamin Gaignard 269ba2d53fbSBenjamin Gaignard /* pixel memory location */ 270ba2d53fbSBenjamin Gaignard drm_fb_get_bpp_depth(layer->format, &depth, &bpp); 271ba2d53fbSBenjamin Gaignard top_field->gam_gdp_pml = (u32) layer->paddr + layer->offsets[0]; 272ba2d53fbSBenjamin Gaignard top_field->gam_gdp_pml += layer->src_x * (bpp >> 3); 273ba2d53fbSBenjamin Gaignard top_field->gam_gdp_pml += layer->src_y * layer->pitches[0]; 274ba2d53fbSBenjamin Gaignard 275ba2d53fbSBenjamin Gaignard /* input parameters */ 276ba2d53fbSBenjamin Gaignard top_field->gam_gdp_pmp = layer->pitches[0]; 277ba2d53fbSBenjamin Gaignard top_field->gam_gdp_size = 278ba2d53fbSBenjamin Gaignard clamp_val(layer->src_h, 0, GAM_GDP_SIZE_MAX) << 16 | 279ba2d53fbSBenjamin Gaignard clamp_val(layer->src_w, 0, GAM_GDP_SIZE_MAX); 280ba2d53fbSBenjamin Gaignard 281ba2d53fbSBenjamin Gaignard /* output parameters */ 282ba2d53fbSBenjamin Gaignard ydo = sti_vtg_get_line_number(*mode, layer->dst_y); 283ba2d53fbSBenjamin Gaignard yds = sti_vtg_get_line_number(*mode, layer->dst_y + layer->dst_h - 1); 284ba2d53fbSBenjamin Gaignard xdo = sti_vtg_get_pixel_number(*mode, layer->dst_x); 285ba2d53fbSBenjamin Gaignard xds = sti_vtg_get_pixel_number(*mode, layer->dst_x + layer->dst_w - 1); 286ba2d53fbSBenjamin Gaignard top_field->gam_gdp_vpo = (ydo << 16) | xdo; 287ba2d53fbSBenjamin Gaignard top_field->gam_gdp_vps = (yds << 16) | xds; 288ba2d53fbSBenjamin Gaignard 289ba2d53fbSBenjamin Gaignard /* Same content and chained together */ 290ba2d53fbSBenjamin Gaignard memcpy(btm_field, top_field, sizeof(*btm_field)); 291a51fe84dSBenjamin Gaignard top_field->gam_gdp_nvn = list->btm_field_paddr; 292a51fe84dSBenjamin Gaignard btm_field->gam_gdp_nvn = list->top_field_paddr; 293ba2d53fbSBenjamin Gaignard 294ba2d53fbSBenjamin Gaignard /* Interlaced mode */ 295ba2d53fbSBenjamin Gaignard if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE) 296ba2d53fbSBenjamin Gaignard btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 297ba2d53fbSBenjamin Gaignard layer->pitches[0]; 298ba2d53fbSBenjamin Gaignard 299ba2d53fbSBenjamin Gaignard if (first_prepare) { 300d219673dSBenjamin Gaignard /* Register gdp callback */ 301d219673dSBenjamin Gaignard if (sti_vtg_register_client(layer->mixer_id == STI_MIXER_MAIN ? 302d219673dSBenjamin Gaignard compo->vtg_main : compo->vtg_aux, 303d219673dSBenjamin Gaignard &gdp->vtg_field_nb, layer->mixer_id)) { 304d219673dSBenjamin Gaignard DRM_ERROR("Cannot register VTG notifier\n"); 305d219673dSBenjamin Gaignard return 1; 306d219673dSBenjamin Gaignard } 307d219673dSBenjamin Gaignard 308ba2d53fbSBenjamin Gaignard /* Set and enable gdp clock */ 309ba2d53fbSBenjamin Gaignard if (gdp->clk_pix) { 310ba2d53fbSBenjamin Gaignard res = clk_set_rate(gdp->clk_pix, rate); 311ba2d53fbSBenjamin Gaignard if (res < 0) { 312ba2d53fbSBenjamin Gaignard DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 313ba2d53fbSBenjamin Gaignard rate); 314ba2d53fbSBenjamin Gaignard return 1; 315ba2d53fbSBenjamin Gaignard } 316ba2d53fbSBenjamin Gaignard 317ba2d53fbSBenjamin Gaignard if (clk_prepare_enable(gdp->clk_pix)) { 318ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to prepare/enable gdp\n"); 319ba2d53fbSBenjamin Gaignard return 1; 320ba2d53fbSBenjamin Gaignard } 321ba2d53fbSBenjamin Gaignard } 322ba2d53fbSBenjamin Gaignard } 323ba2d53fbSBenjamin Gaignard 324ba2d53fbSBenjamin Gaignard return 0; 325ba2d53fbSBenjamin Gaignard } 326ba2d53fbSBenjamin Gaignard 327ba2d53fbSBenjamin Gaignard /** 328ba2d53fbSBenjamin Gaignard * sti_gdp_commit_layer 329ba2d53fbSBenjamin Gaignard * @lay: gdp layer 330ba2d53fbSBenjamin Gaignard * 331ba2d53fbSBenjamin Gaignard * Update the NVN field of the 'right' field of the current GDP node (being 332ba2d53fbSBenjamin Gaignard * used by the HW) with the address of the updated ('free') top field GDP node. 333ba2d53fbSBenjamin Gaignard * - In interlaced mode the 'right' field is the bottom field as we update 334ba2d53fbSBenjamin Gaignard * frames starting from their top field 335ba2d53fbSBenjamin Gaignard * - In progressive mode, we update both bottom and top fields which are 336ba2d53fbSBenjamin Gaignard * equal nodes. 337ba2d53fbSBenjamin Gaignard * At the next VSYNC, the updated node list will be used by the HW. 338ba2d53fbSBenjamin Gaignard * 339ba2d53fbSBenjamin Gaignard * RETURNS: 340ba2d53fbSBenjamin Gaignard * 0 on success. 341ba2d53fbSBenjamin Gaignard */ 342ba2d53fbSBenjamin Gaignard static int sti_gdp_commit_layer(struct sti_layer *layer) 343ba2d53fbSBenjamin Gaignard { 344ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list *updated_list = sti_gdp_get_free_nodes(layer); 345ba2d53fbSBenjamin Gaignard struct sti_gdp_node *updated_top_node = updated_list->top_field; 346ba2d53fbSBenjamin Gaignard struct sti_gdp_node *updated_btm_node = updated_list->btm_field; 347ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(layer); 348a51fe84dSBenjamin Gaignard u32 dma_updated_top = updated_list->top_field_paddr; 349a51fe84dSBenjamin Gaignard u32 dma_updated_btm = updated_list->btm_field_paddr; 350ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list *curr_list = sti_gdp_get_current_nodes(layer); 351ba2d53fbSBenjamin Gaignard 352d219673dSBenjamin Gaignard dev_dbg(layer->dev, "%s %s top/btm_node:0x%p/0x%p\n", __func__, 353d219673dSBenjamin Gaignard sti_layer_to_str(layer), 354d219673dSBenjamin Gaignard updated_top_node, updated_btm_node); 355ba2d53fbSBenjamin Gaignard dev_dbg(layer->dev, "Current NVN:0x%X\n", 356ba2d53fbSBenjamin Gaignard readl(layer->regs + GAM_GDP_NVN_OFFSET)); 357ba2d53fbSBenjamin Gaignard dev_dbg(layer->dev, "Posted buff: %lx current buff: %x\n", 358ba2d53fbSBenjamin Gaignard (unsigned long)layer->paddr, 359ba2d53fbSBenjamin Gaignard readl(layer->regs + GAM_GDP_PML_OFFSET)); 360ba2d53fbSBenjamin Gaignard 361ba2d53fbSBenjamin Gaignard if (curr_list == NULL) { 362ba2d53fbSBenjamin Gaignard /* First update or invalid node should directly write in the 363ba2d53fbSBenjamin Gaignard * hw register */ 364d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("%s first update (or invalid node)", 365d219673dSBenjamin Gaignard sti_layer_to_str(layer)); 366d219673dSBenjamin Gaignard 367ba2d53fbSBenjamin Gaignard writel(gdp->is_curr_top == true ? 368ba2d53fbSBenjamin Gaignard dma_updated_btm : dma_updated_top, 369ba2d53fbSBenjamin Gaignard layer->regs + GAM_GDP_NVN_OFFSET); 370ba2d53fbSBenjamin Gaignard return 0; 371ba2d53fbSBenjamin Gaignard } 372ba2d53fbSBenjamin Gaignard 373ba2d53fbSBenjamin Gaignard if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE) { 374ba2d53fbSBenjamin Gaignard if (gdp->is_curr_top == true) { 375ba2d53fbSBenjamin Gaignard /* Do not update in the middle of the frame, but 376ba2d53fbSBenjamin Gaignard * postpone the update after the bottom field has 377ba2d53fbSBenjamin Gaignard * been displayed */ 378ba2d53fbSBenjamin Gaignard curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 379ba2d53fbSBenjamin Gaignard } else { 380ba2d53fbSBenjamin Gaignard /* Direct update to avoid one frame delay */ 381ba2d53fbSBenjamin Gaignard writel(dma_updated_top, 382ba2d53fbSBenjamin Gaignard layer->regs + GAM_GDP_NVN_OFFSET); 383ba2d53fbSBenjamin Gaignard } 384ba2d53fbSBenjamin Gaignard } else { 385ba2d53fbSBenjamin Gaignard /* Direct update for progressive to avoid one frame delay */ 386ba2d53fbSBenjamin Gaignard writel(dma_updated_top, layer->regs + GAM_GDP_NVN_OFFSET); 387ba2d53fbSBenjamin Gaignard } 388ba2d53fbSBenjamin Gaignard 389ba2d53fbSBenjamin Gaignard return 0; 390ba2d53fbSBenjamin Gaignard } 391ba2d53fbSBenjamin Gaignard 392ba2d53fbSBenjamin Gaignard /** 393ba2d53fbSBenjamin Gaignard * sti_gdp_disable_layer 394ba2d53fbSBenjamin Gaignard * @lay: gdp layer 395ba2d53fbSBenjamin Gaignard * 396ba2d53fbSBenjamin Gaignard * Disable a GDP. 397ba2d53fbSBenjamin Gaignard * 398ba2d53fbSBenjamin Gaignard * RETURNS: 399ba2d53fbSBenjamin Gaignard * 0 on success. 400ba2d53fbSBenjamin Gaignard */ 401ba2d53fbSBenjamin Gaignard static int sti_gdp_disable_layer(struct sti_layer *layer) 402ba2d53fbSBenjamin Gaignard { 403ba2d53fbSBenjamin Gaignard unsigned int i; 404ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(layer); 405d219673dSBenjamin Gaignard struct sti_compositor *compo = dev_get_drvdata(layer->dev); 406d219673dSBenjamin Gaignard 407d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("%s\n", sti_layer_to_str(layer)); 408ba2d53fbSBenjamin Gaignard 409ba2d53fbSBenjamin Gaignard /* Set the nodes as 'to be ignored on mixer' */ 410ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) { 411ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 412ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 413ba2d53fbSBenjamin Gaignard } 414ba2d53fbSBenjamin Gaignard 415d219673dSBenjamin Gaignard if (sti_vtg_unregister_client(layer->mixer_id == STI_MIXER_MAIN ? 416d219673dSBenjamin Gaignard compo->vtg_main : compo->vtg_aux, &gdp->vtg_field_nb)) 417d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 418d219673dSBenjamin Gaignard 419ba2d53fbSBenjamin Gaignard if (gdp->clk_pix) 420ba2d53fbSBenjamin Gaignard clk_disable_unprepare(gdp->clk_pix); 421ba2d53fbSBenjamin Gaignard 422ba2d53fbSBenjamin Gaignard return 0; 423ba2d53fbSBenjamin Gaignard } 424ba2d53fbSBenjamin Gaignard 425ba2d53fbSBenjamin Gaignard /** 426ba2d53fbSBenjamin Gaignard * sti_gdp_field_cb 427ba2d53fbSBenjamin Gaignard * @nb: notifier block 428ba2d53fbSBenjamin Gaignard * @event: event message 429ba2d53fbSBenjamin Gaignard * @data: private data 430ba2d53fbSBenjamin Gaignard * 431ba2d53fbSBenjamin Gaignard * Handle VTG top field and bottom field event. 432ba2d53fbSBenjamin Gaignard * 433ba2d53fbSBenjamin Gaignard * RETURNS: 434ba2d53fbSBenjamin Gaignard * 0 on success. 435ba2d53fbSBenjamin Gaignard */ 436ba2d53fbSBenjamin Gaignard int sti_gdp_field_cb(struct notifier_block *nb, 437ba2d53fbSBenjamin Gaignard unsigned long event, void *data) 438ba2d53fbSBenjamin Gaignard { 439ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 440ba2d53fbSBenjamin Gaignard 441ba2d53fbSBenjamin Gaignard switch (event) { 442ba2d53fbSBenjamin Gaignard case VTG_TOP_FIELD_EVENT: 443ba2d53fbSBenjamin Gaignard gdp->is_curr_top = true; 444ba2d53fbSBenjamin Gaignard break; 445ba2d53fbSBenjamin Gaignard case VTG_BOTTOM_FIELD_EVENT: 446ba2d53fbSBenjamin Gaignard gdp->is_curr_top = false; 447ba2d53fbSBenjamin Gaignard break; 448ba2d53fbSBenjamin Gaignard default: 449ba2d53fbSBenjamin Gaignard DRM_ERROR("unsupported event: %lu\n", event); 450ba2d53fbSBenjamin Gaignard break; 451ba2d53fbSBenjamin Gaignard } 452ba2d53fbSBenjamin Gaignard 453ba2d53fbSBenjamin Gaignard return 0; 454ba2d53fbSBenjamin Gaignard } 455ba2d53fbSBenjamin Gaignard 456ba2d53fbSBenjamin Gaignard static void sti_gdp_init(struct sti_layer *layer) 457ba2d53fbSBenjamin Gaignard { 458ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(layer); 459ba2d53fbSBenjamin Gaignard struct device_node *np = layer->dev->of_node; 460a51fe84dSBenjamin Gaignard dma_addr_t dma_addr; 461ba2d53fbSBenjamin Gaignard void *base; 462ba2d53fbSBenjamin Gaignard unsigned int i, size; 463ba2d53fbSBenjamin Gaignard 464ba2d53fbSBenjamin Gaignard /* Allocate all the nodes within a single memory page */ 465ba2d53fbSBenjamin Gaignard size = sizeof(struct sti_gdp_node) * 466ba2d53fbSBenjamin Gaignard GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 467ba2d53fbSBenjamin Gaignard base = dma_alloc_writecombine(layer->dev, 468a51fe84dSBenjamin Gaignard size, &dma_addr, GFP_KERNEL | GFP_DMA); 469a51fe84dSBenjamin Gaignard 470ba2d53fbSBenjamin Gaignard if (!base) { 471ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP node\n"); 472ba2d53fbSBenjamin Gaignard return; 473ba2d53fbSBenjamin Gaignard } 474ba2d53fbSBenjamin Gaignard memset(base, 0, size); 475ba2d53fbSBenjamin Gaignard 476ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) { 477a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) { 478ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n"); 479ba2d53fbSBenjamin Gaignard return; 480ba2d53fbSBenjamin Gaignard } 481ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field = base; 482a51fe84dSBenjamin Gaignard gdp->node_list[i].top_field_paddr = dma_addr; 483a51fe84dSBenjamin Gaignard 484ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 485ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node); 486a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node); 487ba2d53fbSBenjamin Gaignard 488a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) { 489ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n"); 490ba2d53fbSBenjamin Gaignard return; 491ba2d53fbSBenjamin Gaignard } 492ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field = base; 493a51fe84dSBenjamin Gaignard gdp->node_list[i].btm_field_paddr = dma_addr; 494ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 495ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node); 496a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node); 497ba2d53fbSBenjamin Gaignard } 498ba2d53fbSBenjamin Gaignard 499ba2d53fbSBenjamin Gaignard if (of_device_is_compatible(np, "st,stih407-compositor")) { 500ba2d53fbSBenjamin Gaignard /* GDP of STiH407 chip have its own pixel clock */ 501ba2d53fbSBenjamin Gaignard char *clk_name; 502ba2d53fbSBenjamin Gaignard 503ba2d53fbSBenjamin Gaignard switch (layer->desc) { 504ba2d53fbSBenjamin Gaignard case STI_GDP_0: 505ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp1"; 506ba2d53fbSBenjamin Gaignard break; 507ba2d53fbSBenjamin Gaignard case STI_GDP_1: 508ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp2"; 509ba2d53fbSBenjamin Gaignard break; 510ba2d53fbSBenjamin Gaignard case STI_GDP_2: 511ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp3"; 512ba2d53fbSBenjamin Gaignard break; 513ba2d53fbSBenjamin Gaignard case STI_GDP_3: 514ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp4"; 515ba2d53fbSBenjamin Gaignard break; 516ba2d53fbSBenjamin Gaignard default: 517ba2d53fbSBenjamin Gaignard DRM_ERROR("GDP id not recognized\n"); 518ba2d53fbSBenjamin Gaignard return; 519ba2d53fbSBenjamin Gaignard } 520ba2d53fbSBenjamin Gaignard 521ba2d53fbSBenjamin Gaignard gdp->clk_pix = devm_clk_get(layer->dev, clk_name); 522ba2d53fbSBenjamin Gaignard if (IS_ERR(gdp->clk_pix)) 523ba2d53fbSBenjamin Gaignard DRM_ERROR("Cannot get %s clock\n", clk_name); 524ba2d53fbSBenjamin Gaignard } 525ba2d53fbSBenjamin Gaignard } 526ba2d53fbSBenjamin Gaignard 527ba2d53fbSBenjamin Gaignard static const struct sti_layer_funcs gdp_ops = { 528ba2d53fbSBenjamin Gaignard .get_formats = sti_gdp_get_formats, 529ba2d53fbSBenjamin Gaignard .get_nb_formats = sti_gdp_get_nb_formats, 530ba2d53fbSBenjamin Gaignard .init = sti_gdp_init, 531ba2d53fbSBenjamin Gaignard .prepare = sti_gdp_prepare_layer, 532ba2d53fbSBenjamin Gaignard .commit = sti_gdp_commit_layer, 533ba2d53fbSBenjamin Gaignard .disable = sti_gdp_disable_layer, 534ba2d53fbSBenjamin Gaignard }; 535ba2d53fbSBenjamin Gaignard 536ba2d53fbSBenjamin Gaignard struct sti_layer *sti_gdp_create(struct device *dev, int id) 537ba2d53fbSBenjamin Gaignard { 538ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp; 539ba2d53fbSBenjamin Gaignard 540ba2d53fbSBenjamin Gaignard gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 541ba2d53fbSBenjamin Gaignard if (!gdp) { 542ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP\n"); 543ba2d53fbSBenjamin Gaignard return NULL; 544ba2d53fbSBenjamin Gaignard } 545ba2d53fbSBenjamin Gaignard 546ba2d53fbSBenjamin Gaignard gdp->layer.ops = &gdp_ops; 547ba2d53fbSBenjamin Gaignard gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 548ba2d53fbSBenjamin Gaignard 549ba2d53fbSBenjamin Gaignard return (struct sti_layer *)gdp; 550ba2d53fbSBenjamin Gaignard } 551