1ba2d53fbSBenjamin Gaignard /* 2ba2d53fbSBenjamin Gaignard * Copyright (C) STMicroelectronics SA 2014 3ba2d53fbSBenjamin Gaignard * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4ba2d53fbSBenjamin Gaignard * Fabien Dessenne <fabien.dessenne@st.com> 5ba2d53fbSBenjamin Gaignard * for STMicroelectronics. 6ba2d53fbSBenjamin Gaignard * License terms: GNU General Public License (GPL), version 2 7ba2d53fbSBenjamin Gaignard */ 80f3e1561SArnd Bergmann #include <linux/seq_file.h> 9ba2d53fbSBenjamin Gaignard 10dd86dc2fSVincent Abriou #include <drm/drm_atomic.h> 1129d1dc62SVincent Abriou #include <drm/drm_fb_cma_helper.h> 1229d1dc62SVincent Abriou #include <drm/drm_gem_cma_helper.h> 1329d1dc62SVincent Abriou 14d219673dSBenjamin Gaignard #include "sti_compositor.h" 15ba2d53fbSBenjamin Gaignard #include "sti_gdp.h" 169e1f05b2SVincent Abriou #include "sti_plane.h" 17ba2d53fbSBenjamin Gaignard #include "sti_vtg.h" 18ba2d53fbSBenjamin Gaignard 194af6b12aSBenjamin Gaignard #define ALPHASWITCH BIT(6) 20ba2d53fbSBenjamin Gaignard #define ENA_COLOR_FILL BIT(8) 214af6b12aSBenjamin Gaignard #define BIGNOTLITTLE BIT(23) 22ba2d53fbSBenjamin Gaignard #define WAIT_NEXT_VSYNC BIT(31) 23ba2d53fbSBenjamin Gaignard 24ba2d53fbSBenjamin Gaignard /* GDP color formats */ 25ba2d53fbSBenjamin Gaignard #define GDP_RGB565 0x00 26ba2d53fbSBenjamin Gaignard #define GDP_RGB888 0x01 27ba2d53fbSBenjamin Gaignard #define GDP_RGB888_32 0x02 288adb5776SFabien Dessenne #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 29ba2d53fbSBenjamin Gaignard #define GDP_ARGB8565 0x04 30ba2d53fbSBenjamin Gaignard #define GDP_ARGB8888 0x05 314af6b12aSBenjamin Gaignard #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 32ba2d53fbSBenjamin Gaignard #define GDP_ARGB1555 0x06 33ba2d53fbSBenjamin Gaignard #define GDP_ARGB4444 0x07 34ba2d53fbSBenjamin Gaignard 352d61f272SVincent Abriou #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 362d61f272SVincent Abriou 372d61f272SVincent Abriou static struct gdp_format_to_str { 382d61f272SVincent Abriou int format; 392d61f272SVincent Abriou char name[20]; 402d61f272SVincent Abriou } gdp_format_to_str[] = { 412d61f272SVincent Abriou GDP2STR(RGB565), 422d61f272SVincent Abriou GDP2STR(RGB888), 432d61f272SVincent Abriou GDP2STR(RGB888_32), 442d61f272SVincent Abriou GDP2STR(XBGR8888), 452d61f272SVincent Abriou GDP2STR(ARGB8565), 462d61f272SVincent Abriou GDP2STR(ARGB8888), 472d61f272SVincent Abriou GDP2STR(ABGR8888), 482d61f272SVincent Abriou GDP2STR(ARGB1555), 492d61f272SVincent Abriou GDP2STR(ARGB4444) 502d61f272SVincent Abriou }; 51ba2d53fbSBenjamin Gaignard 52ba2d53fbSBenjamin Gaignard #define GAM_GDP_CTL_OFFSET 0x00 53ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_OFFSET 0x04 54ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPO_OFFSET 0x0C 55ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPS_OFFSET 0x10 56ba2d53fbSBenjamin Gaignard #define GAM_GDP_PML_OFFSET 0x14 57ba2d53fbSBenjamin Gaignard #define GAM_GDP_PMP_OFFSET 0x18 58ba2d53fbSBenjamin Gaignard #define GAM_GDP_SIZE_OFFSET 0x1C 59ba2d53fbSBenjamin Gaignard #define GAM_GDP_NVN_OFFSET 0x24 60ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY1_OFFSET 0x28 61ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY2_OFFSET 0x2C 62ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_OFFSET 0x34 63ba2d53fbSBenjamin Gaignard #define GAM_GDP_CML_OFFSET 0x3C 64ba2d53fbSBenjamin Gaignard #define GAM_GDP_MST_OFFSET 0x68 65ba2d53fbSBenjamin Gaignard 66ba2d53fbSBenjamin Gaignard #define GAM_GDP_ALPHARANGE_255 BIT(5) 67ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_FULL_RANGE 0x00808080 68ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 692f410f88SVincent Abriou 702f410f88SVincent Abriou #define GAM_GDP_SIZE_MAX_WIDTH 3840 712f410f88SVincent Abriou #define GAM_GDP_SIZE_MAX_HEIGHT 2160 72ba2d53fbSBenjamin Gaignard 73ba2d53fbSBenjamin Gaignard #define GDP_NODE_NB_BANK 2 74ba2d53fbSBenjamin Gaignard #define GDP_NODE_PER_FIELD 2 75ba2d53fbSBenjamin Gaignard 76ba2d53fbSBenjamin Gaignard struct sti_gdp_node { 77ba2d53fbSBenjamin Gaignard u32 gam_gdp_ctl; 78ba2d53fbSBenjamin Gaignard u32 gam_gdp_agc; 79ba2d53fbSBenjamin Gaignard u32 reserved1; 80ba2d53fbSBenjamin Gaignard u32 gam_gdp_vpo; 81ba2d53fbSBenjamin Gaignard u32 gam_gdp_vps; 82ba2d53fbSBenjamin Gaignard u32 gam_gdp_pml; 83ba2d53fbSBenjamin Gaignard u32 gam_gdp_pmp; 84ba2d53fbSBenjamin Gaignard u32 gam_gdp_size; 85ba2d53fbSBenjamin Gaignard u32 reserved2; 86ba2d53fbSBenjamin Gaignard u32 gam_gdp_nvn; 87ba2d53fbSBenjamin Gaignard u32 gam_gdp_key1; 88ba2d53fbSBenjamin Gaignard u32 gam_gdp_key2; 89ba2d53fbSBenjamin Gaignard u32 reserved3; 90ba2d53fbSBenjamin Gaignard u32 gam_gdp_ppt; 91ba2d53fbSBenjamin Gaignard u32 reserved4; 92ba2d53fbSBenjamin Gaignard u32 gam_gdp_cml; 93ba2d53fbSBenjamin Gaignard }; 94ba2d53fbSBenjamin Gaignard 95ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list { 96ba2d53fbSBenjamin Gaignard struct sti_gdp_node *top_field; 97a51fe84dSBenjamin Gaignard dma_addr_t top_field_paddr; 98ba2d53fbSBenjamin Gaignard struct sti_gdp_node *btm_field; 99a51fe84dSBenjamin Gaignard dma_addr_t btm_field_paddr; 100ba2d53fbSBenjamin Gaignard }; 101ba2d53fbSBenjamin Gaignard 102ba2d53fbSBenjamin Gaignard /** 103ba2d53fbSBenjamin Gaignard * STI GDP structure 104ba2d53fbSBenjamin Gaignard * 105871bcdfeSVincent Abriou * @sti_plane: sti_plane structure 106871bcdfeSVincent Abriou * @dev: driver device 107871bcdfeSVincent Abriou * @regs: gdp registers 108ba2d53fbSBenjamin Gaignard * @clk_pix: pixel clock for the current gdp 1095e03abc5SBenjamin Gaignard * @clk_main_parent: gdp parent clock if main path used 1105e03abc5SBenjamin Gaignard * @clk_aux_parent: gdp parent clock if aux path used 111ba2d53fbSBenjamin Gaignard * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 112ba2d53fbSBenjamin Gaignard * @is_curr_top: true if the current node processed is the top field 113ba2d53fbSBenjamin Gaignard * @node_list: array of node list 11420c47601Sbenjamin.gaignard@linaro.org * @vtg: registered vtg 115ba2d53fbSBenjamin Gaignard */ 116ba2d53fbSBenjamin Gaignard struct sti_gdp { 117871bcdfeSVincent Abriou struct sti_plane plane; 118871bcdfeSVincent Abriou struct device *dev; 119871bcdfeSVincent Abriou void __iomem *regs; 120ba2d53fbSBenjamin Gaignard struct clk *clk_pix; 1215e03abc5SBenjamin Gaignard struct clk *clk_main_parent; 1225e03abc5SBenjamin Gaignard struct clk *clk_aux_parent; 123ba2d53fbSBenjamin Gaignard struct notifier_block vtg_field_nb; 124ba2d53fbSBenjamin Gaignard bool is_curr_top; 125ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 12620c47601Sbenjamin.gaignard@linaro.org struct sti_vtg *vtg; 127ba2d53fbSBenjamin Gaignard }; 128ba2d53fbSBenjamin Gaignard 129871bcdfeSVincent Abriou #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 130ba2d53fbSBenjamin Gaignard 131ba2d53fbSBenjamin Gaignard static const uint32_t gdp_supported_formats[] = { 132ba2d53fbSBenjamin Gaignard DRM_FORMAT_XRGB8888, 1338adb5776SFabien Dessenne DRM_FORMAT_XBGR8888, 134ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB8888, 1354af6b12aSBenjamin Gaignard DRM_FORMAT_ABGR8888, 136ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB4444, 137ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB1555, 138ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB565, 139ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB888, 140ba2d53fbSBenjamin Gaignard }; 141ba2d53fbSBenjamin Gaignard 1422d61f272SVincent Abriou #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 1432d61f272SVincent Abriou readl(gdp->regs + reg ## _OFFSET)) 1442d61f272SVincent Abriou 1452d61f272SVincent Abriou static void gdp_dbg_ctl(struct seq_file *s, int val) 1462d61f272SVincent Abriou { 1472d61f272SVincent Abriou int i; 1482d61f272SVincent Abriou 1492d61f272SVincent Abriou seq_puts(s, "\tColor:"); 1502d61f272SVincent Abriou for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 1512d61f272SVincent Abriou if (gdp_format_to_str[i].format == (val & 0x1F)) { 1522d61f272SVincent Abriou seq_printf(s, gdp_format_to_str[i].name); 1532d61f272SVincent Abriou break; 1542d61f272SVincent Abriou } 1552d61f272SVincent Abriou } 1562d61f272SVincent Abriou if (i == ARRAY_SIZE(gdp_format_to_str)) 1572d61f272SVincent Abriou seq_puts(s, "<UNKNOWN>"); 1582d61f272SVincent Abriou 1592d61f272SVincent Abriou seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 1602d61f272SVincent Abriou } 1612d61f272SVincent Abriou 1622d61f272SVincent Abriou static void gdp_dbg_vpo(struct seq_file *s, int val) 1632d61f272SVincent Abriou { 1642d61f272SVincent Abriou seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 1652d61f272SVincent Abriou } 1662d61f272SVincent Abriou 1672d61f272SVincent Abriou static void gdp_dbg_vps(struct seq_file *s, int val) 1682d61f272SVincent Abriou { 1692d61f272SVincent Abriou seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 1702d61f272SVincent Abriou } 1712d61f272SVincent Abriou 1722d61f272SVincent Abriou static void gdp_dbg_size(struct seq_file *s, int val) 1732d61f272SVincent Abriou { 1742d61f272SVincent Abriou seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 1752d61f272SVincent Abriou } 1762d61f272SVincent Abriou 1772d61f272SVincent Abriou static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 1782d61f272SVincent Abriou { 1792d61f272SVincent Abriou void *base = NULL; 1802d61f272SVincent Abriou unsigned int i; 1812d61f272SVincent Abriou 1822d61f272SVincent Abriou for (i = 0; i < GDP_NODE_NB_BANK; i++) { 1832d61f272SVincent Abriou if (gdp->node_list[i].top_field_paddr == val) { 1842d61f272SVincent Abriou base = gdp->node_list[i].top_field; 1852d61f272SVincent Abriou break; 1862d61f272SVincent Abriou } 1872d61f272SVincent Abriou if (gdp->node_list[i].btm_field_paddr == val) { 1882d61f272SVincent Abriou base = gdp->node_list[i].btm_field; 1892d61f272SVincent Abriou break; 1902d61f272SVincent Abriou } 1912d61f272SVincent Abriou } 1922d61f272SVincent Abriou 1932d61f272SVincent Abriou if (base) 1942d61f272SVincent Abriou seq_printf(s, "\tVirt @: %p", base); 1952d61f272SVincent Abriou } 1962d61f272SVincent Abriou 1972d61f272SVincent Abriou static void gdp_dbg_ppt(struct seq_file *s, int val) 1982d61f272SVincent Abriou { 1992d61f272SVincent Abriou if (val & GAM_GDP_PPT_IGNORE) 2002d61f272SVincent Abriou seq_puts(s, "\tNot displayed on mixer!"); 2012d61f272SVincent Abriou } 2022d61f272SVincent Abriou 2032d61f272SVincent Abriou static void gdp_dbg_mst(struct seq_file *s, int val) 2042d61f272SVincent Abriou { 2052d61f272SVincent Abriou if (val & 1) 2062d61f272SVincent Abriou seq_puts(s, "\tBUFFER UNDERFLOW!"); 2072d61f272SVincent Abriou } 2082d61f272SVincent Abriou 2092d61f272SVincent Abriou static int gdp_dbg_show(struct seq_file *s, void *data) 2102d61f272SVincent Abriou { 2112d61f272SVincent Abriou struct drm_info_node *node = s->private; 2122d61f272SVincent Abriou struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 2132d61f272SVincent Abriou struct drm_plane *drm_plane = &gdp->plane.drm_plane; 2142d61f272SVincent Abriou struct drm_crtc *crtc = drm_plane->crtc; 2152d61f272SVincent Abriou 2162d61f272SVincent Abriou seq_printf(s, "%s: (vaddr = 0x%p)", 2172d61f272SVincent Abriou sti_plane_to_str(&gdp->plane), gdp->regs); 2182d61f272SVincent Abriou 2192d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_CTL); 2202d61f272SVincent Abriou gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 2212d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_AGC); 2222d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_VPO); 2232d61f272SVincent Abriou gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 2242d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_VPS); 2252d61f272SVincent Abriou gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 2262d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PML); 2272d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PMP); 2282d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_SIZE); 2292d61f272SVincent Abriou gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 2302d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_NVN); 2312d61f272SVincent Abriou gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 2322d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_KEY1); 2332d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_KEY2); 2342d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PPT); 2352d61f272SVincent Abriou gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 2362d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_CML); 2372d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_MST); 2382d61f272SVincent Abriou gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 2392d61f272SVincent Abriou 2402d61f272SVincent Abriou seq_puts(s, "\n\n"); 2412d61f272SVincent Abriou if (!crtc) 2422d61f272SVincent Abriou seq_puts(s, " Not connected to any DRM CRTC\n"); 2432d61f272SVincent Abriou else 2442d61f272SVincent Abriou seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 2452d61f272SVincent Abriou crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 2462d61f272SVincent Abriou 2472d61f272SVincent Abriou return 0; 2482d61f272SVincent Abriou } 2492d61f272SVincent Abriou 2502d61f272SVincent Abriou static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 2512d61f272SVincent Abriou { 2522d61f272SVincent Abriou seq_printf(s, "\t@:0x%p", node); 2532d61f272SVincent Abriou seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 2542d61f272SVincent Abriou gdp_dbg_ctl(s, node->gam_gdp_ctl); 2552d61f272SVincent Abriou seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 2562d61f272SVincent Abriou seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 2572d61f272SVincent Abriou gdp_dbg_vpo(s, node->gam_gdp_vpo); 2582d61f272SVincent Abriou seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 2592d61f272SVincent Abriou gdp_dbg_vps(s, node->gam_gdp_vps); 2602d61f272SVincent Abriou seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 2612d61f272SVincent Abriou seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 2622d61f272SVincent Abriou seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 2632d61f272SVincent Abriou gdp_dbg_size(s, node->gam_gdp_size); 2642d61f272SVincent Abriou seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 2652d61f272SVincent Abriou seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 2662d61f272SVincent Abriou seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 2672d61f272SVincent Abriou seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 2682d61f272SVincent Abriou gdp_dbg_ppt(s, node->gam_gdp_ppt); 2692d61f272SVincent Abriou seq_printf(s, "\n\tCML 0x%08X", node->gam_gdp_cml); 2702d61f272SVincent Abriou seq_puts(s, "\n"); 2712d61f272SVincent Abriou } 2722d61f272SVincent Abriou 2732d61f272SVincent Abriou static int gdp_node_dbg_show(struct seq_file *s, void *arg) 2742d61f272SVincent Abriou { 2752d61f272SVincent Abriou struct drm_info_node *node = s->private; 2762d61f272SVincent Abriou struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 2772d61f272SVincent Abriou unsigned int b; 2782d61f272SVincent Abriou 2792d61f272SVincent Abriou for (b = 0; b < GDP_NODE_NB_BANK; b++) { 2802d61f272SVincent Abriou seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 2812d61f272SVincent Abriou gdp_node_dump_node(s, gdp->node_list[b].top_field); 2822d61f272SVincent Abriou seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 2832d61f272SVincent Abriou gdp_node_dump_node(s, gdp->node_list[b].btm_field); 2842d61f272SVincent Abriou } 2852d61f272SVincent Abriou 2862d61f272SVincent Abriou return 0; 2872d61f272SVincent Abriou } 2882d61f272SVincent Abriou 2892d61f272SVincent Abriou static struct drm_info_list gdp0_debugfs_files[] = { 2902d61f272SVincent Abriou { "gdp0", gdp_dbg_show, 0, NULL }, 2912d61f272SVincent Abriou { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 2922d61f272SVincent Abriou }; 2932d61f272SVincent Abriou 2942d61f272SVincent Abriou static struct drm_info_list gdp1_debugfs_files[] = { 2952d61f272SVincent Abriou { "gdp1", gdp_dbg_show, 0, NULL }, 2962d61f272SVincent Abriou { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 2972d61f272SVincent Abriou }; 2982d61f272SVincent Abriou 2992d61f272SVincent Abriou static struct drm_info_list gdp2_debugfs_files[] = { 3002d61f272SVincent Abriou { "gdp2", gdp_dbg_show, 0, NULL }, 3012d61f272SVincent Abriou { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 3022d61f272SVincent Abriou }; 3032d61f272SVincent Abriou 3042d61f272SVincent Abriou static struct drm_info_list gdp3_debugfs_files[] = { 3052d61f272SVincent Abriou { "gdp3", gdp_dbg_show, 0, NULL }, 3062d61f272SVincent Abriou { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 3072d61f272SVincent Abriou }; 3082d61f272SVincent Abriou 3092d61f272SVincent Abriou static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 3102d61f272SVincent Abriou { 3112d61f272SVincent Abriou unsigned int i; 3122d61f272SVincent Abriou struct drm_info_list *gdp_debugfs_files; 3132d61f272SVincent Abriou int nb_files; 3142d61f272SVincent Abriou 3152d61f272SVincent Abriou switch (gdp->plane.desc) { 3162d61f272SVincent Abriou case STI_GDP_0: 3172d61f272SVincent Abriou gdp_debugfs_files = gdp0_debugfs_files; 3182d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp0_debugfs_files); 3192d61f272SVincent Abriou break; 3202d61f272SVincent Abriou case STI_GDP_1: 3212d61f272SVincent Abriou gdp_debugfs_files = gdp1_debugfs_files; 3222d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp1_debugfs_files); 3232d61f272SVincent Abriou break; 3242d61f272SVincent Abriou case STI_GDP_2: 3252d61f272SVincent Abriou gdp_debugfs_files = gdp2_debugfs_files; 3262d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp2_debugfs_files); 3272d61f272SVincent Abriou break; 3282d61f272SVincent Abriou case STI_GDP_3: 3292d61f272SVincent Abriou gdp_debugfs_files = gdp3_debugfs_files; 3302d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp3_debugfs_files); 3312d61f272SVincent Abriou break; 3322d61f272SVincent Abriou default: 3332d61f272SVincent Abriou return -EINVAL; 3342d61f272SVincent Abriou } 3352d61f272SVincent Abriou 3362d61f272SVincent Abriou for (i = 0; i < nb_files; i++) 3372d61f272SVincent Abriou gdp_debugfs_files[i].data = gdp; 3382d61f272SVincent Abriou 3392d61f272SVincent Abriou return drm_debugfs_create_files(gdp_debugfs_files, 3402d61f272SVincent Abriou nb_files, 3412d61f272SVincent Abriou minor->debugfs_root, minor); 3422d61f272SVincent Abriou } 3432d61f272SVincent Abriou 344ba2d53fbSBenjamin Gaignard static int sti_gdp_fourcc2format(int fourcc) 345ba2d53fbSBenjamin Gaignard { 346ba2d53fbSBenjamin Gaignard switch (fourcc) { 347ba2d53fbSBenjamin Gaignard case DRM_FORMAT_XRGB8888: 348ba2d53fbSBenjamin Gaignard return GDP_RGB888_32; 3498adb5776SFabien Dessenne case DRM_FORMAT_XBGR8888: 3508adb5776SFabien Dessenne return GDP_XBGR8888; 351ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB8888: 352ba2d53fbSBenjamin Gaignard return GDP_ARGB8888; 3534af6b12aSBenjamin Gaignard case DRM_FORMAT_ABGR8888: 3544af6b12aSBenjamin Gaignard return GDP_ABGR8888; 355ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB4444: 356ba2d53fbSBenjamin Gaignard return GDP_ARGB4444; 357ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB1555: 358ba2d53fbSBenjamin Gaignard return GDP_ARGB1555; 359ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB565: 360ba2d53fbSBenjamin Gaignard return GDP_RGB565; 361ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB888: 362ba2d53fbSBenjamin Gaignard return GDP_RGB888; 363ba2d53fbSBenjamin Gaignard } 364ba2d53fbSBenjamin Gaignard return -1; 365ba2d53fbSBenjamin Gaignard } 366ba2d53fbSBenjamin Gaignard 367ba2d53fbSBenjamin Gaignard static int sti_gdp_get_alpharange(int format) 368ba2d53fbSBenjamin Gaignard { 369ba2d53fbSBenjamin Gaignard switch (format) { 370ba2d53fbSBenjamin Gaignard case GDP_ARGB8565: 371ba2d53fbSBenjamin Gaignard case GDP_ARGB8888: 3724af6b12aSBenjamin Gaignard case GDP_ABGR8888: 373ba2d53fbSBenjamin Gaignard return GAM_GDP_ALPHARANGE_255; 374ba2d53fbSBenjamin Gaignard } 375ba2d53fbSBenjamin Gaignard return 0; 376ba2d53fbSBenjamin Gaignard } 377ba2d53fbSBenjamin Gaignard 378ba2d53fbSBenjamin Gaignard /** 379ba2d53fbSBenjamin Gaignard * sti_gdp_get_free_nodes 38029d1dc62SVincent Abriou * @gdp: gdp pointer 381ba2d53fbSBenjamin Gaignard * 382ba2d53fbSBenjamin Gaignard * Look for a GDP node list that is not currently read by the HW. 383ba2d53fbSBenjamin Gaignard * 384ba2d53fbSBenjamin Gaignard * RETURNS: 385ba2d53fbSBenjamin Gaignard * Pointer to the free GDP node list 386ba2d53fbSBenjamin Gaignard */ 38729d1dc62SVincent Abriou static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 388ba2d53fbSBenjamin Gaignard { 389ba2d53fbSBenjamin Gaignard int hw_nvn; 390ba2d53fbSBenjamin Gaignard unsigned int i; 391ba2d53fbSBenjamin Gaignard 392871bcdfeSVincent Abriou hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 393ba2d53fbSBenjamin Gaignard if (!hw_nvn) 394ba2d53fbSBenjamin Gaignard goto end; 395ba2d53fbSBenjamin Gaignard 396ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) 397a51fe84dSBenjamin Gaignard if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 398a51fe84dSBenjamin Gaignard (hw_nvn != gdp->node_list[i].top_field_paddr)) 399ba2d53fbSBenjamin Gaignard return &gdp->node_list[i]; 400ba2d53fbSBenjamin Gaignard 401d219673dSBenjamin Gaignard /* in hazardious cases restart with the first node */ 402d219673dSBenjamin Gaignard DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 40329d1dc62SVincent Abriou sti_plane_to_str(&gdp->plane), hw_nvn); 404d219673dSBenjamin Gaignard 405ba2d53fbSBenjamin Gaignard end: 406ba2d53fbSBenjamin Gaignard return &gdp->node_list[0]; 407ba2d53fbSBenjamin Gaignard } 408ba2d53fbSBenjamin Gaignard 409ba2d53fbSBenjamin Gaignard /** 410ba2d53fbSBenjamin Gaignard * sti_gdp_get_current_nodes 41129d1dc62SVincent Abriou * @gdp: gdp pointer 412ba2d53fbSBenjamin Gaignard * 413ba2d53fbSBenjamin Gaignard * Look for GDP nodes that are currently read by the HW. 414ba2d53fbSBenjamin Gaignard * 415ba2d53fbSBenjamin Gaignard * RETURNS: 416ba2d53fbSBenjamin Gaignard * Pointer to the current GDP node list 417ba2d53fbSBenjamin Gaignard */ 418ba2d53fbSBenjamin Gaignard static 41929d1dc62SVincent Abriou struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 420ba2d53fbSBenjamin Gaignard { 421ba2d53fbSBenjamin Gaignard int hw_nvn; 422ba2d53fbSBenjamin Gaignard unsigned int i; 423ba2d53fbSBenjamin Gaignard 424871bcdfeSVincent Abriou hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 425ba2d53fbSBenjamin Gaignard if (!hw_nvn) 426ba2d53fbSBenjamin Gaignard goto end; 427ba2d53fbSBenjamin Gaignard 428ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) 429a51fe84dSBenjamin Gaignard if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 430a51fe84dSBenjamin Gaignard (hw_nvn == gdp->node_list[i].top_field_paddr)) 431ba2d53fbSBenjamin Gaignard return &gdp->node_list[i]; 432ba2d53fbSBenjamin Gaignard 433ba2d53fbSBenjamin Gaignard end: 434d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 43529d1dc62SVincent Abriou hw_nvn, sti_plane_to_str(&gdp->plane)); 436d219673dSBenjamin Gaignard 437ba2d53fbSBenjamin Gaignard return NULL; 438ba2d53fbSBenjamin Gaignard } 439ba2d53fbSBenjamin Gaignard 440ba2d53fbSBenjamin Gaignard /** 441871bcdfeSVincent Abriou * sti_gdp_disable 44229d1dc62SVincent Abriou * @gdp: gdp pointer 443ba2d53fbSBenjamin Gaignard * 444ba2d53fbSBenjamin Gaignard * Disable a GDP. 445ba2d53fbSBenjamin Gaignard */ 44629d1dc62SVincent Abriou static void sti_gdp_disable(struct sti_gdp *gdp) 447ba2d53fbSBenjamin Gaignard { 44829d1dc62SVincent Abriou unsigned int i; 449d219673dSBenjamin Gaignard 45029d1dc62SVincent Abriou DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 451ba2d53fbSBenjamin Gaignard 452ba2d53fbSBenjamin Gaignard /* Set the nodes as 'to be ignored on mixer' */ 453ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) { 454ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 455ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 456ba2d53fbSBenjamin Gaignard } 457ba2d53fbSBenjamin Gaignard 45820c47601Sbenjamin.gaignard@linaro.org if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 459d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 460d219673dSBenjamin Gaignard 461ba2d53fbSBenjamin Gaignard if (gdp->clk_pix) 462ba2d53fbSBenjamin Gaignard clk_disable_unprepare(gdp->clk_pix); 463ba2d53fbSBenjamin Gaignard 46429d1dc62SVincent Abriou gdp->plane.status = STI_PLANE_DISABLED; 46500b517e5SFabien Dessenne gdp->vtg = NULL; 466ba2d53fbSBenjamin Gaignard } 467ba2d53fbSBenjamin Gaignard 468ba2d53fbSBenjamin Gaignard /** 469ba2d53fbSBenjamin Gaignard * sti_gdp_field_cb 470ba2d53fbSBenjamin Gaignard * @nb: notifier block 471ba2d53fbSBenjamin Gaignard * @event: event message 472ba2d53fbSBenjamin Gaignard * @data: private data 473ba2d53fbSBenjamin Gaignard * 474ba2d53fbSBenjamin Gaignard * Handle VTG top field and bottom field event. 475ba2d53fbSBenjamin Gaignard * 476ba2d53fbSBenjamin Gaignard * RETURNS: 477ba2d53fbSBenjamin Gaignard * 0 on success. 478ba2d53fbSBenjamin Gaignard */ 479bdfd36efSVille Syrjälä static int sti_gdp_field_cb(struct notifier_block *nb, 480ba2d53fbSBenjamin Gaignard unsigned long event, void *data) 481ba2d53fbSBenjamin Gaignard { 482ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 483ba2d53fbSBenjamin Gaignard 48429d1dc62SVincent Abriou if (gdp->plane.status == STI_PLANE_FLUSHING) { 48529d1dc62SVincent Abriou /* disable need to be synchronize on vsync event */ 48629d1dc62SVincent Abriou DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 48729d1dc62SVincent Abriou sti_plane_to_str(&gdp->plane)); 48829d1dc62SVincent Abriou 48929d1dc62SVincent Abriou sti_gdp_disable(gdp); 49029d1dc62SVincent Abriou } 49129d1dc62SVincent Abriou 492ba2d53fbSBenjamin Gaignard switch (event) { 493ba2d53fbSBenjamin Gaignard case VTG_TOP_FIELD_EVENT: 494ba2d53fbSBenjamin Gaignard gdp->is_curr_top = true; 495ba2d53fbSBenjamin Gaignard break; 496ba2d53fbSBenjamin Gaignard case VTG_BOTTOM_FIELD_EVENT: 497ba2d53fbSBenjamin Gaignard gdp->is_curr_top = false; 498ba2d53fbSBenjamin Gaignard break; 499ba2d53fbSBenjamin Gaignard default: 500ba2d53fbSBenjamin Gaignard DRM_ERROR("unsupported event: %lu\n", event); 501ba2d53fbSBenjamin Gaignard break; 502ba2d53fbSBenjamin Gaignard } 503ba2d53fbSBenjamin Gaignard 504ba2d53fbSBenjamin Gaignard return 0; 505ba2d53fbSBenjamin Gaignard } 506ba2d53fbSBenjamin Gaignard 507871bcdfeSVincent Abriou static void sti_gdp_init(struct sti_gdp *gdp) 508ba2d53fbSBenjamin Gaignard { 509871bcdfeSVincent Abriou struct device_node *np = gdp->dev->of_node; 510a51fe84dSBenjamin Gaignard dma_addr_t dma_addr; 511ba2d53fbSBenjamin Gaignard void *base; 512ba2d53fbSBenjamin Gaignard unsigned int i, size; 513ba2d53fbSBenjamin Gaignard 514ba2d53fbSBenjamin Gaignard /* Allocate all the nodes within a single memory page */ 515ba2d53fbSBenjamin Gaignard size = sizeof(struct sti_gdp_node) * 516ba2d53fbSBenjamin Gaignard GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 517f6e45661SLuis R. Rodriguez base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA); 518a51fe84dSBenjamin Gaignard 519ba2d53fbSBenjamin Gaignard if (!base) { 520ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP node\n"); 521ba2d53fbSBenjamin Gaignard return; 522ba2d53fbSBenjamin Gaignard } 523ba2d53fbSBenjamin Gaignard memset(base, 0, size); 524ba2d53fbSBenjamin Gaignard 525ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) { 526a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) { 527ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n"); 528ba2d53fbSBenjamin Gaignard return; 529ba2d53fbSBenjamin Gaignard } 530ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field = base; 531a51fe84dSBenjamin Gaignard gdp->node_list[i].top_field_paddr = dma_addr; 532a51fe84dSBenjamin Gaignard 533ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 534ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node); 535a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node); 536ba2d53fbSBenjamin Gaignard 537a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) { 538ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n"); 539ba2d53fbSBenjamin Gaignard return; 540ba2d53fbSBenjamin Gaignard } 541ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field = base; 542a51fe84dSBenjamin Gaignard gdp->node_list[i].btm_field_paddr = dma_addr; 543ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 544ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node); 545a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node); 546ba2d53fbSBenjamin Gaignard } 547ba2d53fbSBenjamin Gaignard 548ba2d53fbSBenjamin Gaignard if (of_device_is_compatible(np, "st,stih407-compositor")) { 549ba2d53fbSBenjamin Gaignard /* GDP of STiH407 chip have its own pixel clock */ 550ba2d53fbSBenjamin Gaignard char *clk_name; 551ba2d53fbSBenjamin Gaignard 552871bcdfeSVincent Abriou switch (gdp->plane.desc) { 553ba2d53fbSBenjamin Gaignard case STI_GDP_0: 554ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp1"; 555ba2d53fbSBenjamin Gaignard break; 556ba2d53fbSBenjamin Gaignard case STI_GDP_1: 557ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp2"; 558ba2d53fbSBenjamin Gaignard break; 559ba2d53fbSBenjamin Gaignard case STI_GDP_2: 560ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp3"; 561ba2d53fbSBenjamin Gaignard break; 562ba2d53fbSBenjamin Gaignard case STI_GDP_3: 563ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp4"; 564ba2d53fbSBenjamin Gaignard break; 565ba2d53fbSBenjamin Gaignard default: 566ba2d53fbSBenjamin Gaignard DRM_ERROR("GDP id not recognized\n"); 567ba2d53fbSBenjamin Gaignard return; 568ba2d53fbSBenjamin Gaignard } 569ba2d53fbSBenjamin Gaignard 570871bcdfeSVincent Abriou gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 571ba2d53fbSBenjamin Gaignard if (IS_ERR(gdp->clk_pix)) 572ba2d53fbSBenjamin Gaignard DRM_ERROR("Cannot get %s clock\n", clk_name); 5735e03abc5SBenjamin Gaignard 574871bcdfeSVincent Abriou gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 5755e03abc5SBenjamin Gaignard if (IS_ERR(gdp->clk_main_parent)) 5765e03abc5SBenjamin Gaignard DRM_ERROR("Cannot get main_parent clock\n"); 5775e03abc5SBenjamin Gaignard 578871bcdfeSVincent Abriou gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 5795e03abc5SBenjamin Gaignard if (IS_ERR(gdp->clk_aux_parent)) 5805e03abc5SBenjamin Gaignard DRM_ERROR("Cannot get aux_parent clock\n"); 581ba2d53fbSBenjamin Gaignard } 582ba2d53fbSBenjamin Gaignard } 583ba2d53fbSBenjamin Gaignard 584a5b9a713SBich Hemon /** 585a5b9a713SBich Hemon * sti_gdp_get_dst 586a5b9a713SBich Hemon * @dev: device 587a5b9a713SBich Hemon * @dst: requested destination size 588a5b9a713SBich Hemon * @src: source size 589a5b9a713SBich Hemon * 590a5b9a713SBich Hemon * Return the cropped / clamped destination size 591a5b9a713SBich Hemon * 592a5b9a713SBich Hemon * RETURNS: 593a5b9a713SBich Hemon * cropped / clamped destination size 594a5b9a713SBich Hemon */ 595a5b9a713SBich Hemon static int sti_gdp_get_dst(struct device *dev, int dst, int src) 59629d1dc62SVincent Abriou { 597a5b9a713SBich Hemon if (dst == src) 598a5b9a713SBich Hemon return dst; 599a5b9a713SBich Hemon 600a5b9a713SBich Hemon if (dst < src) { 601a5b9a713SBich Hemon dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 602a5b9a713SBich Hemon return dst; 603a5b9a713SBich Hemon } 604a5b9a713SBich Hemon 605a5b9a713SBich Hemon dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 606a5b9a713SBich Hemon return src; 607a5b9a713SBich Hemon } 608a5b9a713SBich Hemon 609dd86dc2fSVincent Abriou static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 610dd86dc2fSVincent Abriou struct drm_plane_state *state) 611dd86dc2fSVincent Abriou { 61229d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane); 61329d1dc62SVincent Abriou struct sti_gdp *gdp = to_sti_gdp(plane); 61429d1dc62SVincent Abriou struct drm_crtc *crtc = state->crtc; 61529d1dc62SVincent Abriou struct drm_framebuffer *fb = state->fb; 616dd86dc2fSVincent Abriou struct drm_crtc_state *crtc_state; 61729d1dc62SVincent Abriou struct sti_mixer *mixer; 61829d1dc62SVincent Abriou struct drm_display_mode *mode; 61929d1dc62SVincent Abriou int dst_x, dst_y, dst_w, dst_h; 62029d1dc62SVincent Abriou int src_x, src_y, src_w, src_h; 62129d1dc62SVincent Abriou int format; 62229d1dc62SVincent Abriou 623dd86dc2fSVincent Abriou /* no need for further checks if the plane is being disabled */ 624dd86dc2fSVincent Abriou if (!crtc || !fb) 625dd86dc2fSVincent Abriou return 0; 62629d1dc62SVincent Abriou 62729d1dc62SVincent Abriou mixer = to_sti_mixer(crtc); 628dd86dc2fSVincent Abriou crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 629dd86dc2fSVincent Abriou mode = &crtc_state->mode; 63029d1dc62SVincent Abriou dst_x = state->crtc_x; 63129d1dc62SVincent Abriou dst_y = state->crtc_y; 632f766c6c8SFabien Dessenne dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 633f766c6c8SFabien Dessenne dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 63429d1dc62SVincent Abriou /* src_x are in 16.16 format */ 63529d1dc62SVincent Abriou src_x = state->src_x >> 16; 63629d1dc62SVincent Abriou src_y = state->src_y >> 16; 6372f410f88SVincent Abriou src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 6382f410f88SVincent Abriou src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 63929d1dc62SVincent Abriou 640438b74a5SVille Syrjälä format = sti_gdp_fourcc2format(fb->format->format); 64129d1dc62SVincent Abriou if (format == -1) { 64229d1dc62SVincent Abriou DRM_ERROR("Format not supported by GDP %.4s\n", 643438b74a5SVille Syrjälä (char *)&fb->format->format); 644dd86dc2fSVincent Abriou return -EINVAL; 64529d1dc62SVincent Abriou } 64629d1dc62SVincent Abriou 647dd86dc2fSVincent Abriou if (!drm_fb_cma_get_gem_obj(fb, 0)) { 64829d1dc62SVincent Abriou DRM_ERROR("Can't get CMA GEM object for fb\n"); 649dd86dc2fSVincent Abriou return -EINVAL; 65029d1dc62SVincent Abriou } 65129d1dc62SVincent Abriou 6521b7f1451SVincent Abriou /* Set gdp clock */ 653c5649ee4SVincent Abriou if (mode->clock && gdp->clk_pix) { 65429d1dc62SVincent Abriou struct clk *clkp; 65529d1dc62SVincent Abriou int rate = mode->clock * 1000; 656dd86dc2fSVincent Abriou int res; 65729d1dc62SVincent Abriou 658dd86dc2fSVincent Abriou /* 659dd86dc2fSVincent Abriou * According to the mixer used, the gdp pixel clock 660dd86dc2fSVincent Abriou * should have a different parent clock. 661dd86dc2fSVincent Abriou */ 66229d1dc62SVincent Abriou if (mixer->id == STI_MIXER_MAIN) 66329d1dc62SVincent Abriou clkp = gdp->clk_main_parent; 66429d1dc62SVincent Abriou else 66529d1dc62SVincent Abriou clkp = gdp->clk_aux_parent; 66629d1dc62SVincent Abriou 66729d1dc62SVincent Abriou if (clkp) 66829d1dc62SVincent Abriou clk_set_parent(gdp->clk_pix, clkp); 66929d1dc62SVincent Abriou 67029d1dc62SVincent Abriou res = clk_set_rate(gdp->clk_pix, rate); 67129d1dc62SVincent Abriou if (res < 0) { 67229d1dc62SVincent Abriou DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 67329d1dc62SVincent Abriou rate); 674dd86dc2fSVincent Abriou return -EINVAL; 67529d1dc62SVincent Abriou } 676dd86dc2fSVincent Abriou } 677dd86dc2fSVincent Abriou 678dd86dc2fSVincent Abriou DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 679dd86dc2fSVincent Abriou crtc->base.id, sti_mixer_to_str(mixer), 680dd86dc2fSVincent Abriou drm_plane->base.id, sti_plane_to_str(plane)); 681dd86dc2fSVincent Abriou DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 682dd86dc2fSVincent Abriou sti_plane_to_str(plane), 683dd86dc2fSVincent Abriou dst_w, dst_h, dst_x, dst_y, 684dd86dc2fSVincent Abriou src_w, src_h, src_x, src_y); 685dd86dc2fSVincent Abriou 686dd86dc2fSVincent Abriou return 0; 687dd86dc2fSVincent Abriou } 688dd86dc2fSVincent Abriou 68929d1dc62SVincent Abriou static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 69029d1dc62SVincent Abriou struct drm_plane_state *oldstate) 69129d1dc62SVincent Abriou { 69229d1dc62SVincent Abriou struct drm_plane_state *state = drm_plane->state; 69329d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane); 69429d1dc62SVincent Abriou struct sti_gdp *gdp = to_sti_gdp(plane); 69529d1dc62SVincent Abriou struct drm_crtc *crtc = state->crtc; 69629d1dc62SVincent Abriou struct drm_framebuffer *fb = state->fb; 69729d1dc62SVincent Abriou struct drm_display_mode *mode; 69829d1dc62SVincent Abriou int dst_x, dst_y, dst_w, dst_h; 69929d1dc62SVincent Abriou int src_x, src_y, src_w, src_h; 70029d1dc62SVincent Abriou struct drm_gem_cma_object *cma_obj; 70129d1dc62SVincent Abriou struct sti_gdp_node_list *list; 70229d1dc62SVincent Abriou struct sti_gdp_node_list *curr_list; 70329d1dc62SVincent Abriou struct sti_gdp_node *top_field, *btm_field; 70429d1dc62SVincent Abriou u32 dma_updated_top; 70529d1dc62SVincent Abriou u32 dma_updated_btm; 70629d1dc62SVincent Abriou int format; 707d27cd40aSLaurent Pinchart unsigned int bpp; 70829d1dc62SVincent Abriou u32 ydo, xdo, yds, xds; 70929d1dc62SVincent Abriou 710dd86dc2fSVincent Abriou if (!crtc || !fb) 71129d1dc62SVincent Abriou return; 71229d1dc62SVincent Abriou 713e9f494d3SVincent Abriou if ((oldstate->fb == state->fb) && 714e9f494d3SVincent Abriou (oldstate->crtc_x == state->crtc_x) && 715e9f494d3SVincent Abriou (oldstate->crtc_y == state->crtc_y) && 716e9f494d3SVincent Abriou (oldstate->crtc_w == state->crtc_w) && 717e9f494d3SVincent Abriou (oldstate->crtc_h == state->crtc_h) && 718e9f494d3SVincent Abriou (oldstate->src_x == state->src_x) && 719e9f494d3SVincent Abriou (oldstate->src_y == state->src_y) && 720e9f494d3SVincent Abriou (oldstate->src_w == state->src_w) && 721e9f494d3SVincent Abriou (oldstate->src_h == state->src_h)) { 722e9f494d3SVincent Abriou /* No change since last update, do not post cmd */ 723e9f494d3SVincent Abriou DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 724e9f494d3SVincent Abriou plane->status = STI_PLANE_UPDATED; 725e9f494d3SVincent Abriou return; 726e9f494d3SVincent Abriou } 727e9f494d3SVincent Abriou 7281b7f1451SVincent Abriou if (!gdp->vtg) { 7291b7f1451SVincent Abriou struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 7301b7f1451SVincent Abriou struct sti_mixer *mixer = to_sti_mixer(crtc); 7311b7f1451SVincent Abriou 7321b7f1451SVincent Abriou /* Register gdp callback */ 7331b7f1451SVincent Abriou gdp->vtg = compo->vtg[mixer->id]; 7341b7f1451SVincent Abriou sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc); 7351b7f1451SVincent Abriou clk_prepare_enable(gdp->clk_pix); 7361b7f1451SVincent Abriou } 7371b7f1451SVincent Abriou 73829d1dc62SVincent Abriou mode = &crtc->mode; 73929d1dc62SVincent Abriou dst_x = state->crtc_x; 74029d1dc62SVincent Abriou dst_y = state->crtc_y; 741f766c6c8SFabien Dessenne dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 742f766c6c8SFabien Dessenne dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 74329d1dc62SVincent Abriou /* src_x are in 16.16 format */ 74429d1dc62SVincent Abriou src_x = state->src_x >> 16; 74529d1dc62SVincent Abriou src_y = state->src_y >> 16; 7462f410f88SVincent Abriou src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 7472f410f88SVincent Abriou src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 74829d1dc62SVincent Abriou 74929d1dc62SVincent Abriou list = sti_gdp_get_free_nodes(gdp); 75029d1dc62SVincent Abriou top_field = list->top_field; 75129d1dc62SVincent Abriou btm_field = list->btm_field; 75229d1dc62SVincent Abriou 75329d1dc62SVincent Abriou dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 75429d1dc62SVincent Abriou sti_plane_to_str(plane), top_field, btm_field); 75529d1dc62SVincent Abriou 75629d1dc62SVincent Abriou /* build the top field */ 75729d1dc62SVincent Abriou top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 75829d1dc62SVincent Abriou top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 759438b74a5SVille Syrjälä format = sti_gdp_fourcc2format(fb->format->format); 76029d1dc62SVincent Abriou top_field->gam_gdp_ctl |= format; 76129d1dc62SVincent Abriou top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 76229d1dc62SVincent Abriou top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 76329d1dc62SVincent Abriou 76429d1dc62SVincent Abriou cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 76529d1dc62SVincent Abriou 76629d1dc62SVincent Abriou DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 767438b74a5SVille Syrjälä (char *)&fb->format->format, 76829d1dc62SVincent Abriou (unsigned long)cma_obj->paddr); 76929d1dc62SVincent Abriou 77029d1dc62SVincent Abriou /* pixel memory location */ 771353c8598SVille Syrjälä bpp = fb->format->cpp[0]; 77229d1dc62SVincent Abriou top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 773d27cd40aSLaurent Pinchart top_field->gam_gdp_pml += src_x * bpp; 77429d1dc62SVincent Abriou top_field->gam_gdp_pml += src_y * fb->pitches[0]; 77529d1dc62SVincent Abriou 776a5b9a713SBich Hemon /* output parameters (clamped / cropped) */ 777a5b9a713SBich Hemon dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 778a5b9a713SBich Hemon dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 77929d1dc62SVincent Abriou ydo = sti_vtg_get_line_number(*mode, dst_y); 78029d1dc62SVincent Abriou yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 78129d1dc62SVincent Abriou xdo = sti_vtg_get_pixel_number(*mode, dst_x); 78229d1dc62SVincent Abriou xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 78329d1dc62SVincent Abriou top_field->gam_gdp_vpo = (ydo << 16) | xdo; 78429d1dc62SVincent Abriou top_field->gam_gdp_vps = (yds << 16) | xds; 78529d1dc62SVincent Abriou 786704cb30cSVincent Abriou /* input parameters */ 787704cb30cSVincent Abriou src_w = dst_w; 788704cb30cSVincent Abriou top_field->gam_gdp_pmp = fb->pitches[0]; 789704cb30cSVincent Abriou top_field->gam_gdp_size = src_h << 16 | src_w; 790704cb30cSVincent Abriou 79129d1dc62SVincent Abriou /* Same content and chained together */ 79229d1dc62SVincent Abriou memcpy(btm_field, top_field, sizeof(*btm_field)); 79329d1dc62SVincent Abriou top_field->gam_gdp_nvn = list->btm_field_paddr; 79429d1dc62SVincent Abriou btm_field->gam_gdp_nvn = list->top_field_paddr; 79529d1dc62SVincent Abriou 79629d1dc62SVincent Abriou /* Interlaced mode */ 79729d1dc62SVincent Abriou if (mode->flags & DRM_MODE_FLAG_INTERLACE) 79829d1dc62SVincent Abriou btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 79929d1dc62SVincent Abriou fb->pitches[0]; 80029d1dc62SVincent Abriou 80129d1dc62SVincent Abriou /* Update the NVN field of the 'right' field of the current GDP node 80229d1dc62SVincent Abriou * (being used by the HW) with the address of the updated ('free') top 80329d1dc62SVincent Abriou * field GDP node. 80429d1dc62SVincent Abriou * - In interlaced mode the 'right' field is the bottom field as we 80529d1dc62SVincent Abriou * update frames starting from their top field 80629d1dc62SVincent Abriou * - In progressive mode, we update both bottom and top fields which 80729d1dc62SVincent Abriou * are equal nodes. 80829d1dc62SVincent Abriou * At the next VSYNC, the updated node list will be used by the HW. 80929d1dc62SVincent Abriou */ 81029d1dc62SVincent Abriou curr_list = sti_gdp_get_current_nodes(gdp); 81129d1dc62SVincent Abriou dma_updated_top = list->top_field_paddr; 81229d1dc62SVincent Abriou dma_updated_btm = list->btm_field_paddr; 81329d1dc62SVincent Abriou 81429d1dc62SVincent Abriou dev_dbg(gdp->dev, "Current NVN:0x%X\n", 81529d1dc62SVincent Abriou readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 81629d1dc62SVincent Abriou dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 81729d1dc62SVincent Abriou (unsigned long)cma_obj->paddr, 81829d1dc62SVincent Abriou readl(gdp->regs + GAM_GDP_PML_OFFSET)); 81929d1dc62SVincent Abriou 82029d1dc62SVincent Abriou if (!curr_list) { 82129d1dc62SVincent Abriou /* First update or invalid node should directly write in the 82229d1dc62SVincent Abriou * hw register */ 82329ffa776SFabien Dessenne DRM_DEBUG_DRIVER("%s first update (or invalid node)\n", 82429d1dc62SVincent Abriou sti_plane_to_str(plane)); 82529d1dc62SVincent Abriou 82629d1dc62SVincent Abriou writel(gdp->is_curr_top ? 82729d1dc62SVincent Abriou dma_updated_btm : dma_updated_top, 82829d1dc62SVincent Abriou gdp->regs + GAM_GDP_NVN_OFFSET); 82929d1dc62SVincent Abriou goto end; 83029d1dc62SVincent Abriou } 83129d1dc62SVincent Abriou 83229d1dc62SVincent Abriou if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 83329d1dc62SVincent Abriou if (gdp->is_curr_top) { 83429d1dc62SVincent Abriou /* Do not update in the middle of the frame, but 83529d1dc62SVincent Abriou * postpone the update after the bottom field has 83629d1dc62SVincent Abriou * been displayed */ 83729d1dc62SVincent Abriou curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 83829d1dc62SVincent Abriou } else { 83929d1dc62SVincent Abriou /* Direct update to avoid one frame delay */ 84029d1dc62SVincent Abriou writel(dma_updated_top, 84129d1dc62SVincent Abriou gdp->regs + GAM_GDP_NVN_OFFSET); 84229d1dc62SVincent Abriou } 84329d1dc62SVincent Abriou } else { 84429d1dc62SVincent Abriou /* Direct update for progressive to avoid one frame delay */ 84529d1dc62SVincent Abriou writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 84629d1dc62SVincent Abriou } 84729d1dc62SVincent Abriou 84829d1dc62SVincent Abriou end: 849bf8f9e4aSVincent Abriou sti_plane_update_fps(plane, true, false); 850bf8f9e4aSVincent Abriou 85129d1dc62SVincent Abriou plane->status = STI_PLANE_UPDATED; 85229d1dc62SVincent Abriou } 85329d1dc62SVincent Abriou 85429d1dc62SVincent Abriou static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 85529d1dc62SVincent Abriou struct drm_plane_state *oldstate) 85629d1dc62SVincent Abriou { 85729d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane); 85829d1dc62SVincent Abriou 8595552aad3SFabien Dessenne if (!oldstate->crtc) { 86029d1dc62SVincent Abriou DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 86129d1dc62SVincent Abriou drm_plane->base.id); 86229d1dc62SVincent Abriou return; 86329d1dc62SVincent Abriou } 86429d1dc62SVincent Abriou 86529d1dc62SVincent Abriou DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 8665552aad3SFabien Dessenne oldstate->crtc->base.id, 8675552aad3SFabien Dessenne sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 86829d1dc62SVincent Abriou drm_plane->base.id, sti_plane_to_str(plane)); 86929d1dc62SVincent Abriou 87029d1dc62SVincent Abriou plane->status = STI_PLANE_DISABLING; 87129d1dc62SVincent Abriou } 87229d1dc62SVincent Abriou 87329d1dc62SVincent Abriou static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 874dd86dc2fSVincent Abriou .atomic_check = sti_gdp_atomic_check, 87529d1dc62SVincent Abriou .atomic_update = sti_gdp_atomic_update, 87629d1dc62SVincent Abriou .atomic_disable = sti_gdp_atomic_disable, 877ba2d53fbSBenjamin Gaignard }; 878ba2d53fbSBenjamin Gaignard 87983af0a48SBenjamin Gaignard static void sti_gdp_destroy(struct drm_plane *drm_plane) 88083af0a48SBenjamin Gaignard { 88183af0a48SBenjamin Gaignard DRM_DEBUG_DRIVER("\n"); 88283af0a48SBenjamin Gaignard 88383af0a48SBenjamin Gaignard drm_plane_helper_disable(drm_plane); 88483af0a48SBenjamin Gaignard drm_plane_cleanup(drm_plane); 88583af0a48SBenjamin Gaignard } 88683af0a48SBenjamin Gaignard 88783af0a48SBenjamin Gaignard static int sti_gdp_late_register(struct drm_plane *drm_plane) 88883af0a48SBenjamin Gaignard { 88983af0a48SBenjamin Gaignard struct sti_plane *plane = to_sti_plane(drm_plane); 89083af0a48SBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(plane); 89183af0a48SBenjamin Gaignard 89283af0a48SBenjamin Gaignard return gdp_debugfs_init(gdp, drm_plane->dev->primary); 89383af0a48SBenjamin Gaignard } 89483af0a48SBenjamin Gaignard 895bdfd36efSVille Syrjälä static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 89683af0a48SBenjamin Gaignard .update_plane = drm_atomic_helper_update_plane, 89783af0a48SBenjamin Gaignard .disable_plane = drm_atomic_helper_disable_plane, 89883af0a48SBenjamin Gaignard .destroy = sti_gdp_destroy, 899bbd1e3a5SBenjamin Gaignard .set_property = drm_atomic_helper_plane_set_property, 900bbd1e3a5SBenjamin Gaignard .reset = sti_plane_reset, 90183af0a48SBenjamin Gaignard .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 90283af0a48SBenjamin Gaignard .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 90383af0a48SBenjamin Gaignard .late_register = sti_gdp_late_register, 90483af0a48SBenjamin Gaignard }; 90583af0a48SBenjamin Gaignard 90629d1dc62SVincent Abriou struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 90729d1dc62SVincent Abriou struct device *dev, int desc, 90829d1dc62SVincent Abriou void __iomem *baseaddr, 90929d1dc62SVincent Abriou unsigned int possible_crtcs, 91029d1dc62SVincent Abriou enum drm_plane_type type) 911ba2d53fbSBenjamin Gaignard { 912ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp; 91329d1dc62SVincent Abriou int res; 914ba2d53fbSBenjamin Gaignard 915ba2d53fbSBenjamin Gaignard gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 916ba2d53fbSBenjamin Gaignard if (!gdp) { 917ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP\n"); 918ba2d53fbSBenjamin Gaignard return NULL; 919ba2d53fbSBenjamin Gaignard } 920ba2d53fbSBenjamin Gaignard 921871bcdfeSVincent Abriou gdp->dev = dev; 922871bcdfeSVincent Abriou gdp->regs = baseaddr; 923871bcdfeSVincent Abriou gdp->plane.desc = desc; 92429d1dc62SVincent Abriou gdp->plane.status = STI_PLANE_DISABLED; 925871bcdfeSVincent Abriou 926ba2d53fbSBenjamin Gaignard gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 927ba2d53fbSBenjamin Gaignard 928871bcdfeSVincent Abriou sti_gdp_init(gdp); 929871bcdfeSVincent Abriou 93029d1dc62SVincent Abriou res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 93129d1dc62SVincent Abriou possible_crtcs, 93283af0a48SBenjamin Gaignard &sti_gdp_plane_helpers_funcs, 93329d1dc62SVincent Abriou gdp_supported_formats, 93429d1dc62SVincent Abriou ARRAY_SIZE(gdp_supported_formats), 935b0b3b795SVille Syrjälä type, NULL); 93629d1dc62SVincent Abriou if (res) { 93729d1dc62SVincent Abriou DRM_ERROR("Failed to initialize universal plane\n"); 93829d1dc62SVincent Abriou goto err; 93929d1dc62SVincent Abriou } 94029d1dc62SVincent Abriou 94129d1dc62SVincent Abriou drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 94229d1dc62SVincent Abriou 94329d1dc62SVincent Abriou sti_plane_init_property(&gdp->plane, type); 94429d1dc62SVincent Abriou 94529d1dc62SVincent Abriou return &gdp->plane.drm_plane; 94629d1dc62SVincent Abriou 94729d1dc62SVincent Abriou err: 94829d1dc62SVincent Abriou devm_kfree(dev, gdp); 94929d1dc62SVincent Abriou return NULL; 950ba2d53fbSBenjamin Gaignard } 951