1e2842570SBenjamin Gaignard // SPDX-License-Identifier: GPL-2.0
2ba2d53fbSBenjamin Gaignard /*
3ba2d53fbSBenjamin Gaignard * Copyright (C) STMicroelectronics SA 2014
4ba2d53fbSBenjamin Gaignard * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
5ba2d53fbSBenjamin Gaignard * Fabien Dessenne <fabien.dessenne@st.com>
6ba2d53fbSBenjamin Gaignard * for STMicroelectronics.
7ba2d53fbSBenjamin Gaignard */
85e2f97a9SSam Ravnborg
95e2f97a9SSam Ravnborg #include <linux/dma-mapping.h>
1073289afeSVille Syrjälä #include <linux/of.h>
110f3e1561SArnd Bergmann #include <linux/seq_file.h>
12ba2d53fbSBenjamin Gaignard
13dd86dc2fSVincent Abriou #include <drm/drm_atomic.h>
145e2f97a9SSam Ravnborg #include <drm/drm_device.h>
156bcfe8eaSDanilo Krummrich #include <drm/drm_fb_dma_helper.h>
165e2f97a9SSam Ravnborg #include <drm/drm_fourcc.h>
17720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h>
184a83c26aSDanilo Krummrich #include <drm/drm_gem_dma_helper.h>
1929d1dc62SVincent Abriou
20d219673dSBenjamin Gaignard #include "sti_compositor.h"
21ba2d53fbSBenjamin Gaignard #include "sti_gdp.h"
229e1f05b2SVincent Abriou #include "sti_plane.h"
23ba2d53fbSBenjamin Gaignard #include "sti_vtg.h"
24ba2d53fbSBenjamin Gaignard
254af6b12aSBenjamin Gaignard #define ALPHASWITCH BIT(6)
26ba2d53fbSBenjamin Gaignard #define ENA_COLOR_FILL BIT(8)
274af6b12aSBenjamin Gaignard #define BIGNOTLITTLE BIT(23)
28ba2d53fbSBenjamin Gaignard #define WAIT_NEXT_VSYNC BIT(31)
29ba2d53fbSBenjamin Gaignard
30ba2d53fbSBenjamin Gaignard /* GDP color formats */
31ba2d53fbSBenjamin Gaignard #define GDP_RGB565 0x00
32ba2d53fbSBenjamin Gaignard #define GDP_RGB888 0x01
33ba2d53fbSBenjamin Gaignard #define GDP_RGB888_32 0x02
348adb5776SFabien Dessenne #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
35ba2d53fbSBenjamin Gaignard #define GDP_ARGB8565 0x04
36ba2d53fbSBenjamin Gaignard #define GDP_ARGB8888 0x05
374af6b12aSBenjamin Gaignard #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
38ba2d53fbSBenjamin Gaignard #define GDP_ARGB1555 0x06
39ba2d53fbSBenjamin Gaignard #define GDP_ARGB4444 0x07
40ba2d53fbSBenjamin Gaignard
412d61f272SVincent Abriou #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
422d61f272SVincent Abriou
432d61f272SVincent Abriou static struct gdp_format_to_str {
442d61f272SVincent Abriou int format;
452d61f272SVincent Abriou char name[20];
462d61f272SVincent Abriou } gdp_format_to_str[] = {
472d61f272SVincent Abriou GDP2STR(RGB565),
482d61f272SVincent Abriou GDP2STR(RGB888),
492d61f272SVincent Abriou GDP2STR(RGB888_32),
502d61f272SVincent Abriou GDP2STR(XBGR8888),
512d61f272SVincent Abriou GDP2STR(ARGB8565),
522d61f272SVincent Abriou GDP2STR(ARGB8888),
532d61f272SVincent Abriou GDP2STR(ABGR8888),
542d61f272SVincent Abriou GDP2STR(ARGB1555),
552d61f272SVincent Abriou GDP2STR(ARGB4444)
562d61f272SVincent Abriou };
57ba2d53fbSBenjamin Gaignard
58ba2d53fbSBenjamin Gaignard #define GAM_GDP_CTL_OFFSET 0x00
59ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_OFFSET 0x04
60ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPO_OFFSET 0x0C
61ba2d53fbSBenjamin Gaignard #define GAM_GDP_VPS_OFFSET 0x10
62ba2d53fbSBenjamin Gaignard #define GAM_GDP_PML_OFFSET 0x14
63ba2d53fbSBenjamin Gaignard #define GAM_GDP_PMP_OFFSET 0x18
64ba2d53fbSBenjamin Gaignard #define GAM_GDP_SIZE_OFFSET 0x1C
65ba2d53fbSBenjamin Gaignard #define GAM_GDP_NVN_OFFSET 0x24
66ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY1_OFFSET 0x28
67ba2d53fbSBenjamin Gaignard #define GAM_GDP_KEY2_OFFSET 0x2C
68ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_OFFSET 0x34
69ba2d53fbSBenjamin Gaignard #define GAM_GDP_CML_OFFSET 0x3C
70ba2d53fbSBenjamin Gaignard #define GAM_GDP_MST_OFFSET 0x68
71ba2d53fbSBenjamin Gaignard
72ba2d53fbSBenjamin Gaignard #define GAM_GDP_ALPHARANGE_255 BIT(5)
73ba2d53fbSBenjamin Gaignard #define GAM_GDP_AGC_FULL_RANGE 0x00808080
74ba2d53fbSBenjamin Gaignard #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
752f410f88SVincent Abriou
762f410f88SVincent Abriou #define GAM_GDP_SIZE_MAX_WIDTH 3840
772f410f88SVincent Abriou #define GAM_GDP_SIZE_MAX_HEIGHT 2160
78ba2d53fbSBenjamin Gaignard
79ba2d53fbSBenjamin Gaignard #define GDP_NODE_NB_BANK 2
80ba2d53fbSBenjamin Gaignard #define GDP_NODE_PER_FIELD 2
81ba2d53fbSBenjamin Gaignard
82ba2d53fbSBenjamin Gaignard struct sti_gdp_node {
83ba2d53fbSBenjamin Gaignard u32 gam_gdp_ctl;
84ba2d53fbSBenjamin Gaignard u32 gam_gdp_agc;
85ba2d53fbSBenjamin Gaignard u32 reserved1;
86ba2d53fbSBenjamin Gaignard u32 gam_gdp_vpo;
87ba2d53fbSBenjamin Gaignard u32 gam_gdp_vps;
88ba2d53fbSBenjamin Gaignard u32 gam_gdp_pml;
89ba2d53fbSBenjamin Gaignard u32 gam_gdp_pmp;
90ba2d53fbSBenjamin Gaignard u32 gam_gdp_size;
91ba2d53fbSBenjamin Gaignard u32 reserved2;
92ba2d53fbSBenjamin Gaignard u32 gam_gdp_nvn;
93ba2d53fbSBenjamin Gaignard u32 gam_gdp_key1;
94ba2d53fbSBenjamin Gaignard u32 gam_gdp_key2;
95ba2d53fbSBenjamin Gaignard u32 reserved3;
96ba2d53fbSBenjamin Gaignard u32 gam_gdp_ppt;
97ba2d53fbSBenjamin Gaignard u32 reserved4;
98ba2d53fbSBenjamin Gaignard u32 gam_gdp_cml;
99ba2d53fbSBenjamin Gaignard };
100ba2d53fbSBenjamin Gaignard
101ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list {
102ba2d53fbSBenjamin Gaignard struct sti_gdp_node *top_field;
103a51fe84dSBenjamin Gaignard dma_addr_t top_field_paddr;
104ba2d53fbSBenjamin Gaignard struct sti_gdp_node *btm_field;
105a51fe84dSBenjamin Gaignard dma_addr_t btm_field_paddr;
106ba2d53fbSBenjamin Gaignard };
107ba2d53fbSBenjamin Gaignard
1085dec1affSBenjamin Gaignard /*
109ba2d53fbSBenjamin Gaignard * STI GDP structure
110ba2d53fbSBenjamin Gaignard *
111871bcdfeSVincent Abriou * @sti_plane: sti_plane structure
112871bcdfeSVincent Abriou * @dev: driver device
113871bcdfeSVincent Abriou * @regs: gdp registers
114ba2d53fbSBenjamin Gaignard * @clk_pix: pixel clock for the current gdp
1155e03abc5SBenjamin Gaignard * @clk_main_parent: gdp parent clock if main path used
1165e03abc5SBenjamin Gaignard * @clk_aux_parent: gdp parent clock if aux path used
117ba2d53fbSBenjamin Gaignard * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
118ba2d53fbSBenjamin Gaignard * @is_curr_top: true if the current node processed is the top field
119ba2d53fbSBenjamin Gaignard * @node_list: array of node list
12020c47601Sbenjamin.gaignard@linaro.org * @vtg: registered vtg
121ba2d53fbSBenjamin Gaignard */
122ba2d53fbSBenjamin Gaignard struct sti_gdp {
123871bcdfeSVincent Abriou struct sti_plane plane;
124871bcdfeSVincent Abriou struct device *dev;
125871bcdfeSVincent Abriou void __iomem *regs;
126ba2d53fbSBenjamin Gaignard struct clk *clk_pix;
1275e03abc5SBenjamin Gaignard struct clk *clk_main_parent;
1285e03abc5SBenjamin Gaignard struct clk *clk_aux_parent;
129ba2d53fbSBenjamin Gaignard struct notifier_block vtg_field_nb;
130ba2d53fbSBenjamin Gaignard bool is_curr_top;
131ba2d53fbSBenjamin Gaignard struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
13220c47601Sbenjamin.gaignard@linaro.org struct sti_vtg *vtg;
133ba2d53fbSBenjamin Gaignard };
134ba2d53fbSBenjamin Gaignard
135871bcdfeSVincent Abriou #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
136ba2d53fbSBenjamin Gaignard
137ba2d53fbSBenjamin Gaignard static const uint32_t gdp_supported_formats[] = {
138ba2d53fbSBenjamin Gaignard DRM_FORMAT_XRGB8888,
1398adb5776SFabien Dessenne DRM_FORMAT_XBGR8888,
140ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB8888,
1414af6b12aSBenjamin Gaignard DRM_FORMAT_ABGR8888,
142ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB4444,
143ba2d53fbSBenjamin Gaignard DRM_FORMAT_ARGB1555,
144ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB565,
145ba2d53fbSBenjamin Gaignard DRM_FORMAT_RGB888,
146ba2d53fbSBenjamin Gaignard };
147ba2d53fbSBenjamin Gaignard
1482d61f272SVincent Abriou #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
1492d61f272SVincent Abriou readl(gdp->regs + reg ## _OFFSET))
1502d61f272SVincent Abriou
gdp_dbg_ctl(struct seq_file * s,int val)1512d61f272SVincent Abriou static void gdp_dbg_ctl(struct seq_file *s, int val)
1522d61f272SVincent Abriou {
1532d61f272SVincent Abriou int i;
1542d61f272SVincent Abriou
1552d61f272SVincent Abriou seq_puts(s, "\tColor:");
1562d61f272SVincent Abriou for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
1572d61f272SVincent Abriou if (gdp_format_to_str[i].format == (val & 0x1F)) {
158adea1db2SNicolas Iooss seq_puts(s, gdp_format_to_str[i].name);
1592d61f272SVincent Abriou break;
1602d61f272SVincent Abriou }
1612d61f272SVincent Abriou }
1622d61f272SVincent Abriou if (i == ARRAY_SIZE(gdp_format_to_str))
1632d61f272SVincent Abriou seq_puts(s, "<UNKNOWN>");
1642d61f272SVincent Abriou
1652d61f272SVincent Abriou seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
1662d61f272SVincent Abriou }
1672d61f272SVincent Abriou
gdp_dbg_vpo(struct seq_file * s,int val)1682d61f272SVincent Abriou static void gdp_dbg_vpo(struct seq_file *s, int val)
1692d61f272SVincent Abriou {
1702d61f272SVincent Abriou seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
1712d61f272SVincent Abriou }
1722d61f272SVincent Abriou
gdp_dbg_vps(struct seq_file * s,int val)1732d61f272SVincent Abriou static void gdp_dbg_vps(struct seq_file *s, int val)
1742d61f272SVincent Abriou {
1752d61f272SVincent Abriou seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
1762d61f272SVincent Abriou }
1772d61f272SVincent Abriou
gdp_dbg_size(struct seq_file * s,int val)1782d61f272SVincent Abriou static void gdp_dbg_size(struct seq_file *s, int val)
1792d61f272SVincent Abriou {
1802d61f272SVincent Abriou seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
1812d61f272SVincent Abriou }
1822d61f272SVincent Abriou
gdp_dbg_nvn(struct seq_file * s,struct sti_gdp * gdp,int val)1832d61f272SVincent Abriou static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
1842d61f272SVincent Abriou {
1852d61f272SVincent Abriou void *base = NULL;
1862d61f272SVincent Abriou unsigned int i;
1872d61f272SVincent Abriou
1882d61f272SVincent Abriou for (i = 0; i < GDP_NODE_NB_BANK; i++) {
1892d61f272SVincent Abriou if (gdp->node_list[i].top_field_paddr == val) {
1902d61f272SVincent Abriou base = gdp->node_list[i].top_field;
1912d61f272SVincent Abriou break;
1922d61f272SVincent Abriou }
1932d61f272SVincent Abriou if (gdp->node_list[i].btm_field_paddr == val) {
1942d61f272SVincent Abriou base = gdp->node_list[i].btm_field;
1952d61f272SVincent Abriou break;
1962d61f272SVincent Abriou }
1972d61f272SVincent Abriou }
1982d61f272SVincent Abriou
1992d61f272SVincent Abriou if (base)
2002d61f272SVincent Abriou seq_printf(s, "\tVirt @: %p", base);
2012d61f272SVincent Abriou }
2022d61f272SVincent Abriou
gdp_dbg_ppt(struct seq_file * s,int val)2032d61f272SVincent Abriou static void gdp_dbg_ppt(struct seq_file *s, int val)
2042d61f272SVincent Abriou {
2052d61f272SVincent Abriou if (val & GAM_GDP_PPT_IGNORE)
2062d61f272SVincent Abriou seq_puts(s, "\tNot displayed on mixer!");
2072d61f272SVincent Abriou }
2082d61f272SVincent Abriou
gdp_dbg_mst(struct seq_file * s,int val)2092d61f272SVincent Abriou static void gdp_dbg_mst(struct seq_file *s, int val)
2102d61f272SVincent Abriou {
2112d61f272SVincent Abriou if (val & 1)
2122d61f272SVincent Abriou seq_puts(s, "\tBUFFER UNDERFLOW!");
2132d61f272SVincent Abriou }
2142d61f272SVincent Abriou
gdp_dbg_show(struct seq_file * s,void * data)2152d61f272SVincent Abriou static int gdp_dbg_show(struct seq_file *s, void *data)
2162d61f272SVincent Abriou {
2172d61f272SVincent Abriou struct drm_info_node *node = s->private;
2182d61f272SVincent Abriou struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
2192d61f272SVincent Abriou struct drm_plane *drm_plane = &gdp->plane.drm_plane;
220df751849SVille Syrjälä struct drm_crtc *crtc;
221df751849SVille Syrjälä
222df751849SVille Syrjälä drm_modeset_lock(&drm_plane->mutex, NULL);
223df751849SVille Syrjälä crtc = drm_plane->state->crtc;
224df751849SVille Syrjälä drm_modeset_unlock(&drm_plane->mutex);
2252d61f272SVincent Abriou
2262d61f272SVincent Abriou seq_printf(s, "%s: (vaddr = 0x%p)",
2272d61f272SVincent Abriou sti_plane_to_str(&gdp->plane), gdp->regs);
2282d61f272SVincent Abriou
2292d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_CTL);
2302d61f272SVincent Abriou gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
2312d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_AGC);
2322d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_VPO);
2332d61f272SVincent Abriou gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
2342d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_VPS);
2352d61f272SVincent Abriou gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
2362d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PML);
2372d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PMP);
2382d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_SIZE);
2392d61f272SVincent Abriou gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
2402d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_NVN);
2412d61f272SVincent Abriou gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
2422d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_KEY1);
2432d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_KEY2);
2442d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_PPT);
2452d61f272SVincent Abriou gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
2462d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_CML);
2472d61f272SVincent Abriou DBGFS_DUMP(GAM_GDP_MST);
2482d61f272SVincent Abriou gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
2492d61f272SVincent Abriou
2502d61f272SVincent Abriou seq_puts(s, "\n\n");
2512d61f272SVincent Abriou if (!crtc)
2522d61f272SVincent Abriou seq_puts(s, " Not connected to any DRM CRTC\n");
2532d61f272SVincent Abriou else
2542d61f272SVincent Abriou seq_printf(s, " Connected to DRM CRTC #%d (%s)\n",
2552d61f272SVincent Abriou crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
2562d61f272SVincent Abriou
2572d61f272SVincent Abriou return 0;
2582d61f272SVincent Abriou }
2592d61f272SVincent Abriou
gdp_node_dump_node(struct seq_file * s,struct sti_gdp_node * node)2602d61f272SVincent Abriou static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
2612d61f272SVincent Abriou {
2622d61f272SVincent Abriou seq_printf(s, "\t@:0x%p", node);
2632d61f272SVincent Abriou seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl);
2642d61f272SVincent Abriou gdp_dbg_ctl(s, node->gam_gdp_ctl);
2652d61f272SVincent Abriou seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc);
2662d61f272SVincent Abriou seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo);
2672d61f272SVincent Abriou gdp_dbg_vpo(s, node->gam_gdp_vpo);
2682d61f272SVincent Abriou seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps);
2692d61f272SVincent Abriou gdp_dbg_vps(s, node->gam_gdp_vps);
2702d61f272SVincent Abriou seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml);
2712d61f272SVincent Abriou seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp);
2722d61f272SVincent Abriou seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
2732d61f272SVincent Abriou gdp_dbg_size(s, node->gam_gdp_size);
2742d61f272SVincent Abriou seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn);
2752d61f272SVincent Abriou seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
2762d61f272SVincent Abriou seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
2772d61f272SVincent Abriou seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt);
2782d61f272SVincent Abriou gdp_dbg_ppt(s, node->gam_gdp_ppt);
279ecf79d15SMarkus Elfring seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml);
2802d61f272SVincent Abriou }
2812d61f272SVincent Abriou
gdp_node_dbg_show(struct seq_file * s,void * arg)2822d61f272SVincent Abriou static int gdp_node_dbg_show(struct seq_file *s, void *arg)
2832d61f272SVincent Abriou {
2842d61f272SVincent Abriou struct drm_info_node *node = s->private;
2852d61f272SVincent Abriou struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
2862d61f272SVincent Abriou unsigned int b;
2872d61f272SVincent Abriou
2882d61f272SVincent Abriou for (b = 0; b < GDP_NODE_NB_BANK; b++) {
2892d61f272SVincent Abriou seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
2902d61f272SVincent Abriou gdp_node_dump_node(s, gdp->node_list[b].top_field);
2912d61f272SVincent Abriou seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
2922d61f272SVincent Abriou gdp_node_dump_node(s, gdp->node_list[b].btm_field);
2932d61f272SVincent Abriou }
2942d61f272SVincent Abriou
2952d61f272SVincent Abriou return 0;
2962d61f272SVincent Abriou }
2972d61f272SVincent Abriou
2982d61f272SVincent Abriou static struct drm_info_list gdp0_debugfs_files[] = {
2992d61f272SVincent Abriou { "gdp0", gdp_dbg_show, 0, NULL },
3002d61f272SVincent Abriou { "gdp0_node", gdp_node_dbg_show, 0, NULL },
3012d61f272SVincent Abriou };
3022d61f272SVincent Abriou
3032d61f272SVincent Abriou static struct drm_info_list gdp1_debugfs_files[] = {
3042d61f272SVincent Abriou { "gdp1", gdp_dbg_show, 0, NULL },
3052d61f272SVincent Abriou { "gdp1_node", gdp_node_dbg_show, 0, NULL },
3062d61f272SVincent Abriou };
3072d61f272SVincent Abriou
3082d61f272SVincent Abriou static struct drm_info_list gdp2_debugfs_files[] = {
3092d61f272SVincent Abriou { "gdp2", gdp_dbg_show, 0, NULL },
3102d61f272SVincent Abriou { "gdp2_node", gdp_node_dbg_show, 0, NULL },
3112d61f272SVincent Abriou };
3122d61f272SVincent Abriou
3132d61f272SVincent Abriou static struct drm_info_list gdp3_debugfs_files[] = {
3142d61f272SVincent Abriou { "gdp3", gdp_dbg_show, 0, NULL },
3152d61f272SVincent Abriou { "gdp3_node", gdp_node_dbg_show, 0, NULL },
3162d61f272SVincent Abriou };
3172d61f272SVincent Abriou
gdp_debugfs_init(struct sti_gdp * gdp,struct drm_minor * minor)3182d61f272SVincent Abriou static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
3192d61f272SVincent Abriou {
3202d61f272SVincent Abriou unsigned int i;
3212d61f272SVincent Abriou struct drm_info_list *gdp_debugfs_files;
3222d61f272SVincent Abriou int nb_files;
3232d61f272SVincent Abriou
3242d61f272SVincent Abriou switch (gdp->plane.desc) {
3252d61f272SVincent Abriou case STI_GDP_0:
3262d61f272SVincent Abriou gdp_debugfs_files = gdp0_debugfs_files;
3272d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp0_debugfs_files);
3282d61f272SVincent Abriou break;
3292d61f272SVincent Abriou case STI_GDP_1:
3302d61f272SVincent Abriou gdp_debugfs_files = gdp1_debugfs_files;
3312d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp1_debugfs_files);
3322d61f272SVincent Abriou break;
3332d61f272SVincent Abriou case STI_GDP_2:
3342d61f272SVincent Abriou gdp_debugfs_files = gdp2_debugfs_files;
3352d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp2_debugfs_files);
3362d61f272SVincent Abriou break;
3372d61f272SVincent Abriou case STI_GDP_3:
3382d61f272SVincent Abriou gdp_debugfs_files = gdp3_debugfs_files;
3392d61f272SVincent Abriou nb_files = ARRAY_SIZE(gdp3_debugfs_files);
3402d61f272SVincent Abriou break;
3412d61f272SVincent Abriou default:
3422d61f272SVincent Abriou return -EINVAL;
3432d61f272SVincent Abriou }
3442d61f272SVincent Abriou
3452d61f272SVincent Abriou for (i = 0; i < nb_files; i++)
3462d61f272SVincent Abriou gdp_debugfs_files[i].data = gdp;
3472d61f272SVincent Abriou
34854ac836bSWambui Karuga drm_debugfs_create_files(gdp_debugfs_files,
3492d61f272SVincent Abriou nb_files,
3502d61f272SVincent Abriou minor->debugfs_root, minor);
35154ac836bSWambui Karuga return 0;
3522d61f272SVincent Abriou }
3532d61f272SVincent Abriou
sti_gdp_fourcc2format(int fourcc)354ba2d53fbSBenjamin Gaignard static int sti_gdp_fourcc2format(int fourcc)
355ba2d53fbSBenjamin Gaignard {
356ba2d53fbSBenjamin Gaignard switch (fourcc) {
357ba2d53fbSBenjamin Gaignard case DRM_FORMAT_XRGB8888:
358ba2d53fbSBenjamin Gaignard return GDP_RGB888_32;
3598adb5776SFabien Dessenne case DRM_FORMAT_XBGR8888:
3608adb5776SFabien Dessenne return GDP_XBGR8888;
361ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB8888:
362ba2d53fbSBenjamin Gaignard return GDP_ARGB8888;
3634af6b12aSBenjamin Gaignard case DRM_FORMAT_ABGR8888:
3644af6b12aSBenjamin Gaignard return GDP_ABGR8888;
365ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB4444:
366ba2d53fbSBenjamin Gaignard return GDP_ARGB4444;
367ba2d53fbSBenjamin Gaignard case DRM_FORMAT_ARGB1555:
368ba2d53fbSBenjamin Gaignard return GDP_ARGB1555;
369ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB565:
370ba2d53fbSBenjamin Gaignard return GDP_RGB565;
371ba2d53fbSBenjamin Gaignard case DRM_FORMAT_RGB888:
372ba2d53fbSBenjamin Gaignard return GDP_RGB888;
373ba2d53fbSBenjamin Gaignard }
374ba2d53fbSBenjamin Gaignard return -1;
375ba2d53fbSBenjamin Gaignard }
376ba2d53fbSBenjamin Gaignard
sti_gdp_get_alpharange(int format)377ba2d53fbSBenjamin Gaignard static int sti_gdp_get_alpharange(int format)
378ba2d53fbSBenjamin Gaignard {
379ba2d53fbSBenjamin Gaignard switch (format) {
380ba2d53fbSBenjamin Gaignard case GDP_ARGB8565:
381ba2d53fbSBenjamin Gaignard case GDP_ARGB8888:
3824af6b12aSBenjamin Gaignard case GDP_ABGR8888:
383ba2d53fbSBenjamin Gaignard return GAM_GDP_ALPHARANGE_255;
384ba2d53fbSBenjamin Gaignard }
385ba2d53fbSBenjamin Gaignard return 0;
386ba2d53fbSBenjamin Gaignard }
387ba2d53fbSBenjamin Gaignard
388ba2d53fbSBenjamin Gaignard /**
389ba2d53fbSBenjamin Gaignard * sti_gdp_get_free_nodes
39029d1dc62SVincent Abriou * @gdp: gdp pointer
391ba2d53fbSBenjamin Gaignard *
392ba2d53fbSBenjamin Gaignard * Look for a GDP node list that is not currently read by the HW.
393ba2d53fbSBenjamin Gaignard *
394ba2d53fbSBenjamin Gaignard * RETURNS:
395ba2d53fbSBenjamin Gaignard * Pointer to the free GDP node list
396ba2d53fbSBenjamin Gaignard */
sti_gdp_get_free_nodes(struct sti_gdp * gdp)39729d1dc62SVincent Abriou static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
398ba2d53fbSBenjamin Gaignard {
399ba2d53fbSBenjamin Gaignard int hw_nvn;
400ba2d53fbSBenjamin Gaignard unsigned int i;
401ba2d53fbSBenjamin Gaignard
402871bcdfeSVincent Abriou hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
403ba2d53fbSBenjamin Gaignard if (!hw_nvn)
404ba2d53fbSBenjamin Gaignard goto end;
405ba2d53fbSBenjamin Gaignard
406ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++)
407a51fe84dSBenjamin Gaignard if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
408a51fe84dSBenjamin Gaignard (hw_nvn != gdp->node_list[i].top_field_paddr))
409ba2d53fbSBenjamin Gaignard return &gdp->node_list[i];
410ba2d53fbSBenjamin Gaignard
4116e87601bSJulia Lawall /* in hazardous cases restart with the first node */
412d219673dSBenjamin Gaignard DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
41329d1dc62SVincent Abriou sti_plane_to_str(&gdp->plane), hw_nvn);
414d219673dSBenjamin Gaignard
415ba2d53fbSBenjamin Gaignard end:
416ba2d53fbSBenjamin Gaignard return &gdp->node_list[0];
417ba2d53fbSBenjamin Gaignard }
418ba2d53fbSBenjamin Gaignard
419ba2d53fbSBenjamin Gaignard /**
420ba2d53fbSBenjamin Gaignard * sti_gdp_get_current_nodes
42129d1dc62SVincent Abriou * @gdp: gdp pointer
422ba2d53fbSBenjamin Gaignard *
423ba2d53fbSBenjamin Gaignard * Look for GDP nodes that are currently read by the HW.
424ba2d53fbSBenjamin Gaignard *
425ba2d53fbSBenjamin Gaignard * RETURNS:
426ba2d53fbSBenjamin Gaignard * Pointer to the current GDP node list
427ba2d53fbSBenjamin Gaignard */
428ba2d53fbSBenjamin Gaignard static
sti_gdp_get_current_nodes(struct sti_gdp * gdp)42929d1dc62SVincent Abriou struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
430ba2d53fbSBenjamin Gaignard {
431ba2d53fbSBenjamin Gaignard int hw_nvn;
432ba2d53fbSBenjamin Gaignard unsigned int i;
433ba2d53fbSBenjamin Gaignard
434871bcdfeSVincent Abriou hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
435ba2d53fbSBenjamin Gaignard if (!hw_nvn)
436ba2d53fbSBenjamin Gaignard goto end;
437ba2d53fbSBenjamin Gaignard
438ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++)
439a51fe84dSBenjamin Gaignard if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
440a51fe84dSBenjamin Gaignard (hw_nvn == gdp->node_list[i].top_field_paddr))
441ba2d53fbSBenjamin Gaignard return &gdp->node_list[i];
442ba2d53fbSBenjamin Gaignard
443ba2d53fbSBenjamin Gaignard end:
444d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
44529d1dc62SVincent Abriou hw_nvn, sti_plane_to_str(&gdp->plane));
446d219673dSBenjamin Gaignard
447ba2d53fbSBenjamin Gaignard return NULL;
448ba2d53fbSBenjamin Gaignard }
449ba2d53fbSBenjamin Gaignard
450ba2d53fbSBenjamin Gaignard /**
451871bcdfeSVincent Abriou * sti_gdp_disable
45229d1dc62SVincent Abriou * @gdp: gdp pointer
453ba2d53fbSBenjamin Gaignard *
454ba2d53fbSBenjamin Gaignard * Disable a GDP.
455ba2d53fbSBenjamin Gaignard */
sti_gdp_disable(struct sti_gdp * gdp)45629d1dc62SVincent Abriou static void sti_gdp_disable(struct sti_gdp *gdp)
457ba2d53fbSBenjamin Gaignard {
45829d1dc62SVincent Abriou unsigned int i;
459d219673dSBenjamin Gaignard
46029d1dc62SVincent Abriou DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
461ba2d53fbSBenjamin Gaignard
462ba2d53fbSBenjamin Gaignard /* Set the nodes as 'to be ignored on mixer' */
463ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) {
464ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
465ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
466ba2d53fbSBenjamin Gaignard }
467ba2d53fbSBenjamin Gaignard
46820c47601Sbenjamin.gaignard@linaro.org if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
469d219673dSBenjamin Gaignard DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
470d219673dSBenjamin Gaignard
471ba2d53fbSBenjamin Gaignard if (gdp->clk_pix)
472ba2d53fbSBenjamin Gaignard clk_disable_unprepare(gdp->clk_pix);
473ba2d53fbSBenjamin Gaignard
47429d1dc62SVincent Abriou gdp->plane.status = STI_PLANE_DISABLED;
47500b517e5SFabien Dessenne gdp->vtg = NULL;
476ba2d53fbSBenjamin Gaignard }
477ba2d53fbSBenjamin Gaignard
478ba2d53fbSBenjamin Gaignard /**
479ba2d53fbSBenjamin Gaignard * sti_gdp_field_cb
480ba2d53fbSBenjamin Gaignard * @nb: notifier block
481ba2d53fbSBenjamin Gaignard * @event: event message
482ba2d53fbSBenjamin Gaignard * @data: private data
483ba2d53fbSBenjamin Gaignard *
484ba2d53fbSBenjamin Gaignard * Handle VTG top field and bottom field event.
485ba2d53fbSBenjamin Gaignard *
486ba2d53fbSBenjamin Gaignard * RETURNS:
487ba2d53fbSBenjamin Gaignard * 0 on success.
488ba2d53fbSBenjamin Gaignard */
sti_gdp_field_cb(struct notifier_block * nb,unsigned long event,void * data)489bdfd36efSVille Syrjälä static int sti_gdp_field_cb(struct notifier_block *nb,
490ba2d53fbSBenjamin Gaignard unsigned long event, void *data)
491ba2d53fbSBenjamin Gaignard {
492ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
493ba2d53fbSBenjamin Gaignard
49429d1dc62SVincent Abriou if (gdp->plane.status == STI_PLANE_FLUSHING) {
49529d1dc62SVincent Abriou /* disable need to be synchronize on vsync event */
49629d1dc62SVincent Abriou DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
49729d1dc62SVincent Abriou sti_plane_to_str(&gdp->plane));
49829d1dc62SVincent Abriou
49929d1dc62SVincent Abriou sti_gdp_disable(gdp);
50029d1dc62SVincent Abriou }
50129d1dc62SVincent Abriou
502ba2d53fbSBenjamin Gaignard switch (event) {
503ba2d53fbSBenjamin Gaignard case VTG_TOP_FIELD_EVENT:
504ba2d53fbSBenjamin Gaignard gdp->is_curr_top = true;
505ba2d53fbSBenjamin Gaignard break;
506ba2d53fbSBenjamin Gaignard case VTG_BOTTOM_FIELD_EVENT:
507ba2d53fbSBenjamin Gaignard gdp->is_curr_top = false;
508ba2d53fbSBenjamin Gaignard break;
509ba2d53fbSBenjamin Gaignard default:
510ba2d53fbSBenjamin Gaignard DRM_ERROR("unsupported event: %lu\n", event);
511ba2d53fbSBenjamin Gaignard break;
512ba2d53fbSBenjamin Gaignard }
513ba2d53fbSBenjamin Gaignard
514ba2d53fbSBenjamin Gaignard return 0;
515ba2d53fbSBenjamin Gaignard }
516ba2d53fbSBenjamin Gaignard
sti_gdp_init(struct sti_gdp * gdp)517871bcdfeSVincent Abriou static void sti_gdp_init(struct sti_gdp *gdp)
518ba2d53fbSBenjamin Gaignard {
519871bcdfeSVincent Abriou struct device_node *np = gdp->dev->of_node;
520a51fe84dSBenjamin Gaignard dma_addr_t dma_addr;
521ba2d53fbSBenjamin Gaignard void *base;
522ba2d53fbSBenjamin Gaignard unsigned int i, size;
523ba2d53fbSBenjamin Gaignard
524ba2d53fbSBenjamin Gaignard /* Allocate all the nodes within a single memory page */
525ba2d53fbSBenjamin Gaignard size = sizeof(struct sti_gdp_node) *
526ba2d53fbSBenjamin Gaignard GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
5274035cc57SChristoph Hellwig base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL);
528a51fe84dSBenjamin Gaignard
529ba2d53fbSBenjamin Gaignard if (!base) {
530ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP node\n");
531ba2d53fbSBenjamin Gaignard return;
532ba2d53fbSBenjamin Gaignard }
533ba2d53fbSBenjamin Gaignard memset(base, 0, size);
534ba2d53fbSBenjamin Gaignard
535ba2d53fbSBenjamin Gaignard for (i = 0; i < GDP_NODE_NB_BANK; i++) {
536a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) {
537ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n");
538ba2d53fbSBenjamin Gaignard return;
539ba2d53fbSBenjamin Gaignard }
540ba2d53fbSBenjamin Gaignard gdp->node_list[i].top_field = base;
541a51fe84dSBenjamin Gaignard gdp->node_list[i].top_field_paddr = dma_addr;
542a51fe84dSBenjamin Gaignard
543ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
544ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node);
545a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node);
546ba2d53fbSBenjamin Gaignard
547a51fe84dSBenjamin Gaignard if (dma_addr & 0xF) {
548ba2d53fbSBenjamin Gaignard DRM_ERROR("Mem alignment failed\n");
549ba2d53fbSBenjamin Gaignard return;
550ba2d53fbSBenjamin Gaignard }
551ba2d53fbSBenjamin Gaignard gdp->node_list[i].btm_field = base;
552a51fe84dSBenjamin Gaignard gdp->node_list[i].btm_field_paddr = dma_addr;
553ba2d53fbSBenjamin Gaignard DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
554ba2d53fbSBenjamin Gaignard base += sizeof(struct sti_gdp_node);
555a51fe84dSBenjamin Gaignard dma_addr += sizeof(struct sti_gdp_node);
556ba2d53fbSBenjamin Gaignard }
557ba2d53fbSBenjamin Gaignard
558ba2d53fbSBenjamin Gaignard if (of_device_is_compatible(np, "st,stih407-compositor")) {
559ba2d53fbSBenjamin Gaignard /* GDP of STiH407 chip have its own pixel clock */
560ba2d53fbSBenjamin Gaignard char *clk_name;
561ba2d53fbSBenjamin Gaignard
562871bcdfeSVincent Abriou switch (gdp->plane.desc) {
563ba2d53fbSBenjamin Gaignard case STI_GDP_0:
564ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp1";
565ba2d53fbSBenjamin Gaignard break;
566ba2d53fbSBenjamin Gaignard case STI_GDP_1:
567ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp2";
568ba2d53fbSBenjamin Gaignard break;
569ba2d53fbSBenjamin Gaignard case STI_GDP_2:
570ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp3";
571ba2d53fbSBenjamin Gaignard break;
572ba2d53fbSBenjamin Gaignard case STI_GDP_3:
573ba2d53fbSBenjamin Gaignard clk_name = "pix_gdp4";
574ba2d53fbSBenjamin Gaignard break;
575ba2d53fbSBenjamin Gaignard default:
576ba2d53fbSBenjamin Gaignard DRM_ERROR("GDP id not recognized\n");
577ba2d53fbSBenjamin Gaignard return;
578ba2d53fbSBenjamin Gaignard }
579ba2d53fbSBenjamin Gaignard
580871bcdfeSVincent Abriou gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
581ba2d53fbSBenjamin Gaignard if (IS_ERR(gdp->clk_pix))
582ba2d53fbSBenjamin Gaignard DRM_ERROR("Cannot get %s clock\n", clk_name);
5835e03abc5SBenjamin Gaignard
584871bcdfeSVincent Abriou gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
5855e03abc5SBenjamin Gaignard if (IS_ERR(gdp->clk_main_parent))
5865e03abc5SBenjamin Gaignard DRM_ERROR("Cannot get main_parent clock\n");
5875e03abc5SBenjamin Gaignard
588871bcdfeSVincent Abriou gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
5895e03abc5SBenjamin Gaignard if (IS_ERR(gdp->clk_aux_parent))
5905e03abc5SBenjamin Gaignard DRM_ERROR("Cannot get aux_parent clock\n");
591ba2d53fbSBenjamin Gaignard }
592ba2d53fbSBenjamin Gaignard }
593ba2d53fbSBenjamin Gaignard
594a5b9a713SBich Hemon /**
595a5b9a713SBich Hemon * sti_gdp_get_dst
596a5b9a713SBich Hemon * @dev: device
597a5b9a713SBich Hemon * @dst: requested destination size
598a5b9a713SBich Hemon * @src: source size
599a5b9a713SBich Hemon *
600a5b9a713SBich Hemon * Return the cropped / clamped destination size
601a5b9a713SBich Hemon *
602a5b9a713SBich Hemon * RETURNS:
603a5b9a713SBich Hemon * cropped / clamped destination size
604a5b9a713SBich Hemon */
sti_gdp_get_dst(struct device * dev,int dst,int src)605a5b9a713SBich Hemon static int sti_gdp_get_dst(struct device *dev, int dst, int src)
60629d1dc62SVincent Abriou {
607a5b9a713SBich Hemon if (dst == src)
608a5b9a713SBich Hemon return dst;
609a5b9a713SBich Hemon
610a5b9a713SBich Hemon if (dst < src) {
611a5b9a713SBich Hemon dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
612a5b9a713SBich Hemon return dst;
613a5b9a713SBich Hemon }
614a5b9a713SBich Hemon
615a5b9a713SBich Hemon dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
616a5b9a713SBich Hemon return src;
617a5b9a713SBich Hemon }
618a5b9a713SBich Hemon
sti_gdp_atomic_check(struct drm_plane * drm_plane,struct drm_atomic_state * state)619dd86dc2fSVincent Abriou static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
6207c11b99aSMaxime Ripard struct drm_atomic_state *state)
621dd86dc2fSVincent Abriou {
6227c11b99aSMaxime Ripard struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
6237c11b99aSMaxime Ripard drm_plane);
62429d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane);
62529d1dc62SVincent Abriou struct sti_gdp *gdp = to_sti_gdp(plane);
626ba5c1649SMaxime Ripard struct drm_crtc *crtc = new_plane_state->crtc;
627ba5c1649SMaxime Ripard struct drm_framebuffer *fb = new_plane_state->fb;
628dd86dc2fSVincent Abriou struct drm_crtc_state *crtc_state;
62929d1dc62SVincent Abriou struct sti_mixer *mixer;
63029d1dc62SVincent Abriou struct drm_display_mode *mode;
63129d1dc62SVincent Abriou int dst_x, dst_y, dst_w, dst_h;
63229d1dc62SVincent Abriou int src_x, src_y, src_w, src_h;
63329d1dc62SVincent Abriou int format;
63429d1dc62SVincent Abriou
635dd86dc2fSVincent Abriou /* no need for further checks if the plane is being disabled */
636dd86dc2fSVincent Abriou if (!crtc || !fb)
637dd86dc2fSVincent Abriou return 0;
63829d1dc62SVincent Abriou
63929d1dc62SVincent Abriou mixer = to_sti_mixer(crtc);
640dec92020SMaxime Ripard crtc_state = drm_atomic_get_crtc_state(state, crtc);
641dd86dc2fSVincent Abriou mode = &crtc_state->mode;
642ba5c1649SMaxime Ripard dst_x = new_plane_state->crtc_x;
643ba5c1649SMaxime Ripard dst_y = new_plane_state->crtc_y;
644ba5c1649SMaxime Ripard dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x);
645ba5c1649SMaxime Ripard dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y);
64629d1dc62SVincent Abriou /* src_x are in 16.16 format */
647ba5c1649SMaxime Ripard src_x = new_plane_state->src_x >> 16;
648ba5c1649SMaxime Ripard src_y = new_plane_state->src_y >> 16;
649ba5c1649SMaxime Ripard src_w = clamp_val(new_plane_state->src_w >> 16, 0,
650ba5c1649SMaxime Ripard GAM_GDP_SIZE_MAX_WIDTH);
651ba5c1649SMaxime Ripard src_h = clamp_val(new_plane_state->src_h >> 16, 0,
652ba5c1649SMaxime Ripard GAM_GDP_SIZE_MAX_HEIGHT);
65329d1dc62SVincent Abriou
654438b74a5SVille Syrjälä format = sti_gdp_fourcc2format(fb->format->format);
65529d1dc62SVincent Abriou if (format == -1) {
65629d1dc62SVincent Abriou DRM_ERROR("Format not supported by GDP %.4s\n",
657438b74a5SVille Syrjälä (char *)&fb->format->format);
658dd86dc2fSVincent Abriou return -EINVAL;
65929d1dc62SVincent Abriou }
66029d1dc62SVincent Abriou
6616bcfe8eaSDanilo Krummrich if (!drm_fb_dma_get_gem_obj(fb, 0)) {
6624a83c26aSDanilo Krummrich DRM_ERROR("Can't get DMA GEM object for fb\n");
663dd86dc2fSVincent Abriou return -EINVAL;
66429d1dc62SVincent Abriou }
66529d1dc62SVincent Abriou
6661b7f1451SVincent Abriou /* Set gdp clock */
667c5649ee4SVincent Abriou if (mode->clock && gdp->clk_pix) {
66829d1dc62SVincent Abriou struct clk *clkp;
66929d1dc62SVincent Abriou int rate = mode->clock * 1000;
670dd86dc2fSVincent Abriou int res;
67129d1dc62SVincent Abriou
672dd86dc2fSVincent Abriou /*
673dd86dc2fSVincent Abriou * According to the mixer used, the gdp pixel clock
674dd86dc2fSVincent Abriou * should have a different parent clock.
675dd86dc2fSVincent Abriou */
67629d1dc62SVincent Abriou if (mixer->id == STI_MIXER_MAIN)
67729d1dc62SVincent Abriou clkp = gdp->clk_main_parent;
67829d1dc62SVincent Abriou else
67929d1dc62SVincent Abriou clkp = gdp->clk_aux_parent;
68029d1dc62SVincent Abriou
68129d1dc62SVincent Abriou if (clkp)
68229d1dc62SVincent Abriou clk_set_parent(gdp->clk_pix, clkp);
68329d1dc62SVincent Abriou
68429d1dc62SVincent Abriou res = clk_set_rate(gdp->clk_pix, rate);
68529d1dc62SVincent Abriou if (res < 0) {
68629d1dc62SVincent Abriou DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
68729d1dc62SVincent Abriou rate);
688dd86dc2fSVincent Abriou return -EINVAL;
68929d1dc62SVincent Abriou }
690dd86dc2fSVincent Abriou }
691dd86dc2fSVincent Abriou
692dd86dc2fSVincent Abriou DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
693dd86dc2fSVincent Abriou crtc->base.id, sti_mixer_to_str(mixer),
694dd86dc2fSVincent Abriou drm_plane->base.id, sti_plane_to_str(plane));
695dd86dc2fSVincent Abriou DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
696dd86dc2fSVincent Abriou sti_plane_to_str(plane),
697dd86dc2fSVincent Abriou dst_w, dst_h, dst_x, dst_y,
698dd86dc2fSVincent Abriou src_w, src_h, src_x, src_y);
699dd86dc2fSVincent Abriou
700dd86dc2fSVincent Abriou return 0;
701dd86dc2fSVincent Abriou }
702dd86dc2fSVincent Abriou
sti_gdp_atomic_update(struct drm_plane * drm_plane,struct drm_atomic_state * state)70329d1dc62SVincent Abriou static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
704977697e2SMaxime Ripard struct drm_atomic_state *state)
70529d1dc62SVincent Abriou {
706977697e2SMaxime Ripard struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
707977697e2SMaxime Ripard drm_plane);
70837418bf1SMaxime Ripard struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
70937418bf1SMaxime Ripard drm_plane);
71029d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane);
71129d1dc62SVincent Abriou struct sti_gdp *gdp = to_sti_gdp(plane);
71241016fe1SMaxime Ripard struct drm_crtc *crtc = newstate->crtc;
71341016fe1SMaxime Ripard struct drm_framebuffer *fb = newstate->fb;
71429d1dc62SVincent Abriou struct drm_display_mode *mode;
71529d1dc62SVincent Abriou int dst_x, dst_y, dst_w, dst_h;
71629d1dc62SVincent Abriou int src_x, src_y, src_w, src_h;
7174a83c26aSDanilo Krummrich struct drm_gem_dma_object *dma_obj;
71829d1dc62SVincent Abriou struct sti_gdp_node_list *list;
71929d1dc62SVincent Abriou struct sti_gdp_node_list *curr_list;
72029d1dc62SVincent Abriou struct sti_gdp_node *top_field, *btm_field;
72129d1dc62SVincent Abriou u32 dma_updated_top;
72229d1dc62SVincent Abriou u32 dma_updated_btm;
72329d1dc62SVincent Abriou int format;
724d27cd40aSLaurent Pinchart unsigned int bpp;
72529d1dc62SVincent Abriou u32 ydo, xdo, yds, xds;
72629d1dc62SVincent Abriou
727dd86dc2fSVincent Abriou if (!crtc || !fb)
72829d1dc62SVincent Abriou return;
72929d1dc62SVincent Abriou
73041016fe1SMaxime Ripard if ((oldstate->fb == newstate->fb) &&
73141016fe1SMaxime Ripard (oldstate->crtc_x == newstate->crtc_x) &&
73241016fe1SMaxime Ripard (oldstate->crtc_y == newstate->crtc_y) &&
73341016fe1SMaxime Ripard (oldstate->crtc_w == newstate->crtc_w) &&
73441016fe1SMaxime Ripard (oldstate->crtc_h == newstate->crtc_h) &&
73541016fe1SMaxime Ripard (oldstate->src_x == newstate->src_x) &&
73641016fe1SMaxime Ripard (oldstate->src_y == newstate->src_y) &&
73741016fe1SMaxime Ripard (oldstate->src_w == newstate->src_w) &&
73841016fe1SMaxime Ripard (oldstate->src_h == newstate->src_h)) {
739e9f494d3SVincent Abriou /* No change since last update, do not post cmd */
740e9f494d3SVincent Abriou DRM_DEBUG_DRIVER("No change, not posting cmd\n");
741e9f494d3SVincent Abriou plane->status = STI_PLANE_UPDATED;
742e9f494d3SVincent Abriou return;
743e9f494d3SVincent Abriou }
744e9f494d3SVincent Abriou
7451b7f1451SVincent Abriou if (!gdp->vtg) {
7461b7f1451SVincent Abriou struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
7471b7f1451SVincent Abriou struct sti_mixer *mixer = to_sti_mixer(crtc);
7481b7f1451SVincent Abriou
7491b7f1451SVincent Abriou /* Register gdp callback */
7501b7f1451SVincent Abriou gdp->vtg = compo->vtg[mixer->id];
7511b7f1451SVincent Abriou sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc);
7521b7f1451SVincent Abriou clk_prepare_enable(gdp->clk_pix);
7531b7f1451SVincent Abriou }
7541b7f1451SVincent Abriou
75529d1dc62SVincent Abriou mode = &crtc->mode;
75641016fe1SMaxime Ripard dst_x = newstate->crtc_x;
75741016fe1SMaxime Ripard dst_y = newstate->crtc_y;
75841016fe1SMaxime Ripard dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x);
75941016fe1SMaxime Ripard dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y);
76029d1dc62SVincent Abriou /* src_x are in 16.16 format */
76141016fe1SMaxime Ripard src_x = newstate->src_x >> 16;
76241016fe1SMaxime Ripard src_y = newstate->src_y >> 16;
76341016fe1SMaxime Ripard src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
76441016fe1SMaxime Ripard src_h = clamp_val(newstate->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
76529d1dc62SVincent Abriou
76629d1dc62SVincent Abriou list = sti_gdp_get_free_nodes(gdp);
76729d1dc62SVincent Abriou top_field = list->top_field;
76829d1dc62SVincent Abriou btm_field = list->btm_field;
76929d1dc62SVincent Abriou
77029d1dc62SVincent Abriou dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
77129d1dc62SVincent Abriou sti_plane_to_str(plane), top_field, btm_field);
77229d1dc62SVincent Abriou
77329d1dc62SVincent Abriou /* build the top field */
77429d1dc62SVincent Abriou top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
77529d1dc62SVincent Abriou top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
776438b74a5SVille Syrjälä format = sti_gdp_fourcc2format(fb->format->format);
77729d1dc62SVincent Abriou top_field->gam_gdp_ctl |= format;
77829d1dc62SVincent Abriou top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
77929d1dc62SVincent Abriou top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
78029d1dc62SVincent Abriou
7814a83c26aSDanilo Krummrich dma_obj = drm_fb_dma_get_gem_obj(fb, 0);
78229d1dc62SVincent Abriou
78329d1dc62SVincent Abriou DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
784438b74a5SVille Syrjälä (char *)&fb->format->format,
785*8c30eeccSDanilo Krummrich (unsigned long) dma_obj->dma_addr);
78629d1dc62SVincent Abriou
78729d1dc62SVincent Abriou /* pixel memory location */
788353c8598SVille Syrjälä bpp = fb->format->cpp[0];
789*8c30eeccSDanilo Krummrich top_field->gam_gdp_pml = (u32) dma_obj->dma_addr + fb->offsets[0];
790d27cd40aSLaurent Pinchart top_field->gam_gdp_pml += src_x * bpp;
79129d1dc62SVincent Abriou top_field->gam_gdp_pml += src_y * fb->pitches[0];
79229d1dc62SVincent Abriou
793a5b9a713SBich Hemon /* output parameters (clamped / cropped) */
794a5b9a713SBich Hemon dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
795a5b9a713SBich Hemon dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
79629d1dc62SVincent Abriou ydo = sti_vtg_get_line_number(*mode, dst_y);
79729d1dc62SVincent Abriou yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
79829d1dc62SVincent Abriou xdo = sti_vtg_get_pixel_number(*mode, dst_x);
79929d1dc62SVincent Abriou xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
80029d1dc62SVincent Abriou top_field->gam_gdp_vpo = (ydo << 16) | xdo;
80129d1dc62SVincent Abriou top_field->gam_gdp_vps = (yds << 16) | xds;
80229d1dc62SVincent Abriou
803704cb30cSVincent Abriou /* input parameters */
804704cb30cSVincent Abriou src_w = dst_w;
805704cb30cSVincent Abriou top_field->gam_gdp_pmp = fb->pitches[0];
806704cb30cSVincent Abriou top_field->gam_gdp_size = src_h << 16 | src_w;
807704cb30cSVincent Abriou
80829d1dc62SVincent Abriou /* Same content and chained together */
80929d1dc62SVincent Abriou memcpy(btm_field, top_field, sizeof(*btm_field));
81029d1dc62SVincent Abriou top_field->gam_gdp_nvn = list->btm_field_paddr;
81129d1dc62SVincent Abriou btm_field->gam_gdp_nvn = list->top_field_paddr;
81229d1dc62SVincent Abriou
81329d1dc62SVincent Abriou /* Interlaced mode */
81429d1dc62SVincent Abriou if (mode->flags & DRM_MODE_FLAG_INTERLACE)
81529d1dc62SVincent Abriou btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
81629d1dc62SVincent Abriou fb->pitches[0];
81729d1dc62SVincent Abriou
81829d1dc62SVincent Abriou /* Update the NVN field of the 'right' field of the current GDP node
81929d1dc62SVincent Abriou * (being used by the HW) with the address of the updated ('free') top
82029d1dc62SVincent Abriou * field GDP node.
82129d1dc62SVincent Abriou * - In interlaced mode the 'right' field is the bottom field as we
82229d1dc62SVincent Abriou * update frames starting from their top field
82329d1dc62SVincent Abriou * - In progressive mode, we update both bottom and top fields which
82429d1dc62SVincent Abriou * are equal nodes.
82529d1dc62SVincent Abriou * At the next VSYNC, the updated node list will be used by the HW.
82629d1dc62SVincent Abriou */
82729d1dc62SVincent Abriou curr_list = sti_gdp_get_current_nodes(gdp);
82829d1dc62SVincent Abriou dma_updated_top = list->top_field_paddr;
82929d1dc62SVincent Abriou dma_updated_btm = list->btm_field_paddr;
83029d1dc62SVincent Abriou
83129d1dc62SVincent Abriou dev_dbg(gdp->dev, "Current NVN:0x%X\n",
83229d1dc62SVincent Abriou readl(gdp->regs + GAM_GDP_NVN_OFFSET));
83329d1dc62SVincent Abriou dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
834*8c30eeccSDanilo Krummrich (unsigned long) dma_obj->dma_addr,
83529d1dc62SVincent Abriou readl(gdp->regs + GAM_GDP_PML_OFFSET));
83629d1dc62SVincent Abriou
83729d1dc62SVincent Abriou if (!curr_list) {
83829d1dc62SVincent Abriou /* First update or invalid node should directly write in the
83929d1dc62SVincent Abriou * hw register */
84029ffa776SFabien Dessenne DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
84129d1dc62SVincent Abriou sti_plane_to_str(plane));
84229d1dc62SVincent Abriou
84329d1dc62SVincent Abriou writel(gdp->is_curr_top ?
84429d1dc62SVincent Abriou dma_updated_btm : dma_updated_top,
84529d1dc62SVincent Abriou gdp->regs + GAM_GDP_NVN_OFFSET);
84629d1dc62SVincent Abriou goto end;
84729d1dc62SVincent Abriou }
84829d1dc62SVincent Abriou
84929d1dc62SVincent Abriou if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
85029d1dc62SVincent Abriou if (gdp->is_curr_top) {
85129d1dc62SVincent Abriou /* Do not update in the middle of the frame, but
85229d1dc62SVincent Abriou * postpone the update after the bottom field has
85329d1dc62SVincent Abriou * been displayed */
85429d1dc62SVincent Abriou curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
85529d1dc62SVincent Abriou } else {
85629d1dc62SVincent Abriou /* Direct update to avoid one frame delay */
85729d1dc62SVincent Abriou writel(dma_updated_top,
85829d1dc62SVincent Abriou gdp->regs + GAM_GDP_NVN_OFFSET);
85929d1dc62SVincent Abriou }
86029d1dc62SVincent Abriou } else {
86129d1dc62SVincent Abriou /* Direct update for progressive to avoid one frame delay */
86229d1dc62SVincent Abriou writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
86329d1dc62SVincent Abriou }
86429d1dc62SVincent Abriou
86529d1dc62SVincent Abriou end:
866bf8f9e4aSVincent Abriou sti_plane_update_fps(plane, true, false);
867bf8f9e4aSVincent Abriou
86829d1dc62SVincent Abriou plane->status = STI_PLANE_UPDATED;
86929d1dc62SVincent Abriou }
87029d1dc62SVincent Abriou
sti_gdp_atomic_disable(struct drm_plane * drm_plane,struct drm_atomic_state * state)87129d1dc62SVincent Abriou static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
872977697e2SMaxime Ripard struct drm_atomic_state *state)
87329d1dc62SVincent Abriou {
874977697e2SMaxime Ripard struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
875977697e2SMaxime Ripard drm_plane);
87629d1dc62SVincent Abriou struct sti_plane *plane = to_sti_plane(drm_plane);
87729d1dc62SVincent Abriou
8785552aad3SFabien Dessenne if (!oldstate->crtc) {
87929d1dc62SVincent Abriou DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
88029d1dc62SVincent Abriou drm_plane->base.id);
88129d1dc62SVincent Abriou return;
88229d1dc62SVincent Abriou }
88329d1dc62SVincent Abriou
88429d1dc62SVincent Abriou DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
8855552aad3SFabien Dessenne oldstate->crtc->base.id,
8865552aad3SFabien Dessenne sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
88729d1dc62SVincent Abriou drm_plane->base.id, sti_plane_to_str(plane));
88829d1dc62SVincent Abriou
88929d1dc62SVincent Abriou plane->status = STI_PLANE_DISABLING;
89029d1dc62SVincent Abriou }
89129d1dc62SVincent Abriou
89229d1dc62SVincent Abriou static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
893dd86dc2fSVincent Abriou .atomic_check = sti_gdp_atomic_check,
89429d1dc62SVincent Abriou .atomic_update = sti_gdp_atomic_update,
89529d1dc62SVincent Abriou .atomic_disable = sti_gdp_atomic_disable,
896ba2d53fbSBenjamin Gaignard };
897ba2d53fbSBenjamin Gaignard
sti_gdp_late_register(struct drm_plane * drm_plane)89883af0a48SBenjamin Gaignard static int sti_gdp_late_register(struct drm_plane *drm_plane)
89983af0a48SBenjamin Gaignard {
90083af0a48SBenjamin Gaignard struct sti_plane *plane = to_sti_plane(drm_plane);
90183af0a48SBenjamin Gaignard struct sti_gdp *gdp = to_sti_gdp(plane);
90283af0a48SBenjamin Gaignard
90383af0a48SBenjamin Gaignard return gdp_debugfs_init(gdp, drm_plane->dev->primary);
90483af0a48SBenjamin Gaignard }
90583af0a48SBenjamin Gaignard
906bdfd36efSVille Syrjälä static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
90783af0a48SBenjamin Gaignard .update_plane = drm_atomic_helper_update_plane,
90883af0a48SBenjamin Gaignard .disable_plane = drm_atomic_helper_disable_plane,
909739fac48SLaurent Pinchart .destroy = drm_plane_cleanup,
91067f0f2e4SMaxime Ripard .reset = drm_atomic_helper_plane_reset,
91183af0a48SBenjamin Gaignard .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
91283af0a48SBenjamin Gaignard .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
91383af0a48SBenjamin Gaignard .late_register = sti_gdp_late_register,
91483af0a48SBenjamin Gaignard };
91583af0a48SBenjamin Gaignard
sti_gdp_create(struct drm_device * drm_dev,struct device * dev,int desc,void __iomem * baseaddr,unsigned int possible_crtcs,enum drm_plane_type type)91629d1dc62SVincent Abriou struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
91729d1dc62SVincent Abriou struct device *dev, int desc,
91829d1dc62SVincent Abriou void __iomem *baseaddr,
91929d1dc62SVincent Abriou unsigned int possible_crtcs,
92029d1dc62SVincent Abriou enum drm_plane_type type)
921ba2d53fbSBenjamin Gaignard {
922ba2d53fbSBenjamin Gaignard struct sti_gdp *gdp;
92329d1dc62SVincent Abriou int res;
924ba2d53fbSBenjamin Gaignard
925ba2d53fbSBenjamin Gaignard gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
926ba2d53fbSBenjamin Gaignard if (!gdp) {
927ba2d53fbSBenjamin Gaignard DRM_ERROR("Failed to allocate memory for GDP\n");
928ba2d53fbSBenjamin Gaignard return NULL;
929ba2d53fbSBenjamin Gaignard }
930ba2d53fbSBenjamin Gaignard
931871bcdfeSVincent Abriou gdp->dev = dev;
932871bcdfeSVincent Abriou gdp->regs = baseaddr;
933871bcdfeSVincent Abriou gdp->plane.desc = desc;
93429d1dc62SVincent Abriou gdp->plane.status = STI_PLANE_DISABLED;
935871bcdfeSVincent Abriou
936ba2d53fbSBenjamin Gaignard gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
937ba2d53fbSBenjamin Gaignard
938871bcdfeSVincent Abriou sti_gdp_init(gdp);
939871bcdfeSVincent Abriou
94029d1dc62SVincent Abriou res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
94129d1dc62SVincent Abriou possible_crtcs,
94283af0a48SBenjamin Gaignard &sti_gdp_plane_helpers_funcs,
94329d1dc62SVincent Abriou gdp_supported_formats,
94429d1dc62SVincent Abriou ARRAY_SIZE(gdp_supported_formats),
945e6fc3b68SBen Widawsky NULL, type, NULL);
94629d1dc62SVincent Abriou if (res) {
94729d1dc62SVincent Abriou DRM_ERROR("Failed to initialize universal plane\n");
94829d1dc62SVincent Abriou goto err;
94929d1dc62SVincent Abriou }
95029d1dc62SVincent Abriou
95129d1dc62SVincent Abriou drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
95229d1dc62SVincent Abriou
95329d1dc62SVincent Abriou sti_plane_init_property(&gdp->plane, type);
95429d1dc62SVincent Abriou
95529d1dc62SVincent Abriou return &gdp->plane.drm_plane;
95629d1dc62SVincent Abriou
95729d1dc62SVincent Abriou err:
95829d1dc62SVincent Abriou devm_kfree(dev, gdp);
95929d1dc62SVincent Abriou return NULL;
960ba2d53fbSBenjamin Gaignard }
961