1 /* 2 * Copyright (C) STMicroelectronics SA 2014 3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 4 * Fabien Dessenne <fabien.dessenne@st.com> 5 * for STMicroelectronics. 6 * License terms: GNU General Public License (GPL), version 2 7 */ 8 9 #include <linux/clk.h> 10 11 #include <drm/drmP.h> 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_crtc_helper.h> 15 #include <drm/drm_plane_helper.h> 16 17 #include "sti_compositor.h" 18 #include "sti_crtc.h" 19 #include "sti_drv.h" 20 #include "sti_vid.h" 21 #include "sti_vtg.h" 22 23 static void sti_crtc_enable(struct drm_crtc *crtc) 24 { 25 struct sti_mixer *mixer = to_sti_mixer(crtc); 26 27 DRM_DEBUG_DRIVER("\n"); 28 29 mixer->status = STI_MIXER_READY; 30 31 drm_crtc_vblank_on(crtc); 32 } 33 34 static void sti_crtc_disabling(struct drm_crtc *crtc) 35 { 36 struct sti_mixer *mixer = to_sti_mixer(crtc); 37 38 DRM_DEBUG_DRIVER("\n"); 39 40 mixer->status = STI_MIXER_DISABLING; 41 } 42 43 static int 44 sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode) 45 { 46 struct sti_mixer *mixer = to_sti_mixer(crtc); 47 struct device *dev = mixer->dev; 48 struct sti_compositor *compo = dev_get_drvdata(dev); 49 struct clk *compo_clk, *pix_clk; 50 int rate = mode->clock * 1000; 51 52 DRM_DEBUG_KMS("CRTC:%d (%s) mode:%d (%s)\n", 53 crtc->base.id, sti_mixer_to_str(mixer), 54 mode->base.id, mode->name); 55 56 DRM_DEBUG_KMS("%d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n", 57 mode->vrefresh, mode->clock, 58 mode->hdisplay, 59 mode->hsync_start, mode->hsync_end, 60 mode->htotal, 61 mode->vdisplay, 62 mode->vsync_start, mode->vsync_end, 63 mode->vtotal, mode->type, mode->flags); 64 65 if (mixer->id == STI_MIXER_MAIN) { 66 compo_clk = compo->clk_compo_main; 67 pix_clk = compo->clk_pix_main; 68 } else { 69 compo_clk = compo->clk_compo_aux; 70 pix_clk = compo->clk_pix_aux; 71 } 72 73 /* Prepare and enable the compo IP clock */ 74 if (clk_prepare_enable(compo_clk)) { 75 DRM_INFO("Failed to prepare/enable compositor clk\n"); 76 goto compo_error; 77 } 78 79 /* Set rate and prepare/enable pixel clock */ 80 if (clk_set_rate(pix_clk, rate) < 0) { 81 DRM_ERROR("Cannot set rate (%dHz) for pix clk\n", rate); 82 goto pix_error; 83 } 84 if (clk_prepare_enable(pix_clk)) { 85 DRM_ERROR("Failed to prepare/enable pix clk\n"); 86 goto pix_error; 87 } 88 89 sti_vtg_set_config(compo->vtg[mixer->id], &crtc->mode); 90 91 if (sti_mixer_active_video_area(mixer, &crtc->mode)) { 92 DRM_ERROR("Can't set active video area\n"); 93 goto mixer_error; 94 } 95 96 return 0; 97 98 mixer_error: 99 clk_disable_unprepare(pix_clk); 100 pix_error: 101 clk_disable_unprepare(compo_clk); 102 compo_error: 103 return -EINVAL; 104 } 105 106 static void sti_crtc_disable(struct drm_crtc *crtc) 107 { 108 struct sti_mixer *mixer = to_sti_mixer(crtc); 109 struct device *dev = mixer->dev; 110 struct sti_compositor *compo = dev_get_drvdata(dev); 111 112 DRM_DEBUG_KMS("CRTC:%d (%s)\n", crtc->base.id, sti_mixer_to_str(mixer)); 113 114 /* Disable Background */ 115 sti_mixer_set_background_status(mixer, false); 116 117 drm_crtc_vblank_off(crtc); 118 119 /* Disable pixel clock and compo IP clocks */ 120 if (mixer->id == STI_MIXER_MAIN) { 121 clk_disable_unprepare(compo->clk_pix_main); 122 clk_disable_unprepare(compo->clk_compo_main); 123 } else { 124 clk_disable_unprepare(compo->clk_pix_aux); 125 clk_disable_unprepare(compo->clk_compo_aux); 126 } 127 128 mixer->status = STI_MIXER_DISABLED; 129 } 130 131 static void 132 sti_crtc_mode_set_nofb(struct drm_crtc *crtc) 133 { 134 sti_crtc_mode_set(crtc, &crtc->state->adjusted_mode); 135 } 136 137 static void sti_crtc_atomic_flush(struct drm_crtc *crtc, 138 struct drm_crtc_state *old_crtc_state) 139 { 140 struct drm_device *drm_dev = crtc->dev; 141 struct sti_mixer *mixer = to_sti_mixer(crtc); 142 struct sti_compositor *compo = dev_get_drvdata(mixer->dev); 143 struct drm_plane *p; 144 struct drm_pending_vblank_event *event; 145 unsigned long flags; 146 147 DRM_DEBUG_DRIVER("\n"); 148 149 /* perform plane actions */ 150 list_for_each_entry(p, &drm_dev->mode_config.plane_list, head) { 151 struct sti_plane *plane = to_sti_plane(p); 152 153 switch (plane->status) { 154 case STI_PLANE_UPDATED: 155 /* ignore update for other CRTC */ 156 if (p->state->crtc != crtc) 157 continue; 158 159 /* update planes tag as updated */ 160 DRM_DEBUG_DRIVER("update plane %s\n", 161 sti_plane_to_str(plane)); 162 163 if (sti_mixer_set_plane_depth(mixer, plane)) { 164 DRM_ERROR("Cannot set plane %s depth\n", 165 sti_plane_to_str(plane)); 166 break; 167 } 168 169 if (sti_mixer_set_plane_status(mixer, plane, true)) { 170 DRM_ERROR("Cannot enable plane %s at mixer\n", 171 sti_plane_to_str(plane)); 172 break; 173 } 174 175 /* if plane is HQVDP_0 then commit the vid[0] */ 176 if (plane->desc == STI_HQVDP_0) 177 sti_vid_commit(compo->vid[0], p->state); 178 179 plane->status = STI_PLANE_READY; 180 181 break; 182 case STI_PLANE_DISABLING: 183 /* disabling sequence for planes tag as disabling */ 184 DRM_DEBUG_DRIVER("disable plane %s from mixer\n", 185 sti_plane_to_str(plane)); 186 187 if (sti_mixer_set_plane_status(mixer, plane, false)) { 188 DRM_ERROR("Cannot disable plane %s at mixer\n", 189 sti_plane_to_str(plane)); 190 continue; 191 } 192 193 if (plane->desc == STI_CURSOR) 194 /* tag plane status for disabled */ 195 plane->status = STI_PLANE_DISABLED; 196 else 197 /* tag plane status for flushing */ 198 plane->status = STI_PLANE_FLUSHING; 199 200 /* if plane is HQVDP_0 then disable the vid[0] */ 201 if (plane->desc == STI_HQVDP_0) 202 sti_vid_disable(compo->vid[0]); 203 204 break; 205 default: 206 /* Other status case are not handled */ 207 break; 208 } 209 } 210 211 event = crtc->state->event; 212 if (event) { 213 crtc->state->event = NULL; 214 215 spin_lock_irqsave(&crtc->dev->event_lock, flags); 216 if (drm_crtc_vblank_get(crtc) == 0) 217 drm_crtc_arm_vblank_event(crtc, event); 218 else 219 drm_crtc_send_vblank_event(crtc, event); 220 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 221 } 222 } 223 224 static const struct drm_crtc_helper_funcs sti_crtc_helper_funcs = { 225 .enable = sti_crtc_enable, 226 .disable = sti_crtc_disabling, 227 .mode_set_nofb = sti_crtc_mode_set_nofb, 228 .atomic_flush = sti_crtc_atomic_flush, 229 }; 230 231 static void sti_crtc_destroy(struct drm_crtc *crtc) 232 { 233 DRM_DEBUG_KMS("\n"); 234 drm_crtc_cleanup(crtc); 235 } 236 237 static int sti_crtc_set_property(struct drm_crtc *crtc, 238 struct drm_property *property, 239 uint64_t val) 240 { 241 DRM_DEBUG_KMS("\n"); 242 return 0; 243 } 244 245 int sti_crtc_vblank_cb(struct notifier_block *nb, 246 unsigned long event, void *data) 247 { 248 struct sti_compositor *compo; 249 struct drm_crtc *crtc = data; 250 struct sti_mixer *mixer; 251 struct sti_private *priv; 252 unsigned int pipe; 253 254 priv = crtc->dev->dev_private; 255 pipe = drm_crtc_index(crtc); 256 compo = container_of(nb, struct sti_compositor, vtg_vblank_nb[pipe]); 257 mixer = compo->mixer[pipe]; 258 259 if ((event != VTG_TOP_FIELD_EVENT) && 260 (event != VTG_BOTTOM_FIELD_EVENT)) { 261 DRM_ERROR("unknown event: %lu\n", event); 262 return -EINVAL; 263 } 264 265 drm_crtc_handle_vblank(crtc); 266 267 if (mixer->status == STI_MIXER_DISABLING) { 268 struct drm_plane *p; 269 270 /* Disable mixer only if all overlay planes (GDP and VDP) 271 * are disabled */ 272 list_for_each_entry(p, &crtc->dev->mode_config.plane_list, 273 head) { 274 struct sti_plane *plane = to_sti_plane(p); 275 276 if ((plane->desc & STI_PLANE_TYPE_MASK) <= STI_VDP) 277 if (plane->status != STI_PLANE_DISABLED) 278 return 0; 279 } 280 sti_crtc_disable(crtc); 281 } 282 283 return 0; 284 } 285 286 int sti_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe) 287 { 288 struct sti_private *dev_priv = dev->dev_private; 289 struct sti_compositor *compo = dev_priv->compo; 290 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb[pipe]; 291 struct drm_crtc *crtc = &compo->mixer[pipe]->drm_crtc; 292 struct sti_vtg *vtg = compo->vtg[pipe]; 293 294 DRM_DEBUG_DRIVER("\n"); 295 296 if (sti_vtg_register_client(vtg, vtg_vblank_nb, crtc)) { 297 DRM_ERROR("Cannot register VTG notifier\n"); 298 return -EINVAL; 299 } 300 301 return 0; 302 } 303 304 void sti_crtc_disable_vblank(struct drm_device *drm_dev, unsigned int pipe) 305 { 306 struct sti_private *priv = drm_dev->dev_private; 307 struct sti_compositor *compo = priv->compo; 308 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb[pipe]; 309 struct sti_vtg *vtg = compo->vtg[pipe]; 310 311 DRM_DEBUG_DRIVER("\n"); 312 313 if (sti_vtg_unregister_client(vtg, vtg_vblank_nb)) 314 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 315 } 316 317 static int sti_crtc_late_register(struct drm_crtc *crtc) 318 { 319 struct sti_mixer *mixer = to_sti_mixer(crtc); 320 struct sti_compositor *compo = dev_get_drvdata(mixer->dev); 321 322 if (drm_crtc_index(crtc) == 0) 323 return sti_compositor_debugfs_init(compo, crtc->dev->primary); 324 325 return 0; 326 } 327 328 static const struct drm_crtc_funcs sti_crtc_funcs = { 329 .set_config = drm_atomic_helper_set_config, 330 .page_flip = drm_atomic_helper_page_flip, 331 .destroy = sti_crtc_destroy, 332 .set_property = sti_crtc_set_property, 333 .reset = drm_atomic_helper_crtc_reset, 334 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 335 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 336 .late_register = sti_crtc_late_register, 337 }; 338 339 bool sti_crtc_is_main(struct drm_crtc *crtc) 340 { 341 struct sti_mixer *mixer = to_sti_mixer(crtc); 342 343 if (mixer->id == STI_MIXER_MAIN) 344 return true; 345 346 return false; 347 } 348 349 int sti_crtc_init(struct drm_device *drm_dev, struct sti_mixer *mixer, 350 struct drm_plane *primary, struct drm_plane *cursor) 351 { 352 struct drm_crtc *crtc = &mixer->drm_crtc; 353 int res; 354 355 res = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 356 &sti_crtc_funcs, NULL); 357 if (res) { 358 DRM_ERROR("Can't initialze CRTC\n"); 359 return -EINVAL; 360 } 361 362 drm_crtc_helper_add(crtc, &sti_crtc_helper_funcs); 363 364 DRM_DEBUG_DRIVER("drm CRTC:%d mapped to %s\n", 365 crtc->base.id, sti_mixer_to_str(mixer)); 366 367 return 0; 368 } 369