1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Unisoc Inc. 4 */ 5 6 #ifndef __SPRD_DSI_H__ 7 #define __SPRD_DSI_H__ 8 9 #include <linux/of.h> 10 #include <linux/device.h> 11 #include <linux/regmap.h> 12 #include <video/videomode.h> 13 14 #include <drm/drm_bridge.h> 15 #include <drm/drm_connector.h> 16 #include <drm/drm_encoder.h> 17 #include <drm/drm_mipi_dsi.h> 18 #include <drm/drm_print.h> 19 #include <drm/drm_panel.h> 20 21 #define encoder_to_dsi(encoder) \ 22 container_of(encoder, struct sprd_dsi, encoder) 23 24 enum dsi_work_mode { 25 DSI_MODE_CMD = 0, 26 DSI_MODE_VIDEO 27 }; 28 29 enum video_burst_mode { 30 VIDEO_NON_BURST_WITH_SYNC_PULSES = 0, 31 VIDEO_NON_BURST_WITH_SYNC_EVENTS, 32 VIDEO_BURST_WITH_SYNC_PULSES 33 }; 34 35 enum dsi_color_coding { 36 COLOR_CODE_16BIT_CONFIG1 = 0, 37 COLOR_CODE_16BIT_CONFIG2, 38 COLOR_CODE_16BIT_CONFIG3, 39 COLOR_CODE_18BIT_CONFIG1, 40 COLOR_CODE_18BIT_CONFIG2, 41 COLOR_CODE_24BIT, 42 COLOR_CODE_20BIT_YCC422_LOOSELY, 43 COLOR_CODE_24BIT_YCC422, 44 COLOR_CODE_16BIT_YCC422, 45 COLOR_CODE_30BIT, 46 COLOR_CODE_36BIT, 47 COLOR_CODE_12BIT_YCC420, 48 COLOR_CODE_COMPRESSTION, 49 COLOR_CODE_MAX 50 }; 51 52 enum pll_timing { 53 NONE, 54 REQUEST_TIME, 55 PREPARE_TIME, 56 SETTLE_TIME, 57 ZERO_TIME, 58 TRAIL_TIME, 59 EXIT_TIME, 60 CLKPOST_TIME, 61 TA_GET, 62 TA_GO, 63 TA_SURE, 64 TA_WAIT, 65 }; 66 67 struct dphy_pll { 68 u8 refin; /* Pre-divider control signal */ 69 u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */ 70 u8 fdk_s; /* PLL mode control: integer or fraction */ 71 u8 sdm_en; 72 u8 div; 73 u8 int_n; /* integer N PLL */ 74 u32 ref_clk; /* dphy reference clock, unit: MHz */ 75 u32 freq; /* panel config, unit: KHz */ 76 u32 fvco; 77 u32 potential_fvco; 78 u32 nint; /* sigma delta modulator NINT control */ 79 u32 kint; /* sigma delta modulator KINT control */ 80 u8 lpf_sel; /* low pass filter control */ 81 u8 out_sel; /* post divider control */ 82 u8 vco_band; /* vco range */ 83 u8 det_delay; 84 }; 85 86 struct dsi_context { 87 void __iomem *base; 88 struct regmap *regmap; 89 struct dphy_pll pll; 90 struct videomode vm; 91 bool enabled; 92 93 u8 work_mode; 94 u8 burst_mode; 95 u32 int0_mask; 96 u32 int1_mask; 97 98 /* maximum time (ns) for data lanes from HS to LP */ 99 u16 data_hs2lp; 100 /* maximum time (ns) for data lanes from LP to HS */ 101 u16 data_lp2hs; 102 /* maximum time (ns) for clk lanes from HS to LP */ 103 u16 clk_hs2lp; 104 /* maximum time (ns) for clk lanes from LP to HS */ 105 u16 clk_lp2hs; 106 /* maximum time (ns) for BTA operation - REQUIRED */ 107 u16 max_rd_time; 108 /* enable receiving frame ack packets - for video mode */ 109 bool frame_ack_en; 110 /* enable receiving tear effect ack packets - for cmd mode */ 111 bool te_ack_en; 112 }; 113 114 struct sprd_dsi { 115 struct drm_device *drm; 116 struct mipi_dsi_host host; 117 struct mipi_dsi_device *slave; 118 struct drm_encoder encoder; 119 struct drm_bridge *panel_bridge; 120 struct dsi_context ctx; 121 }; 122 123 int dphy_pll_config(struct dsi_context *ctx); 124 void dphy_timing_config(struct dsi_context *ctx); 125 126 #endif /* __SPRD_DSI_H__ */ 127