1b07bcf34SKevin Tang // SPDX-License-Identifier: GPL-2.0
2b07bcf34SKevin Tang /*
3b07bcf34SKevin Tang * Copyright (C) 2020 Unisoc Inc.
4b07bcf34SKevin Tang */
5b07bcf34SKevin Tang
6b07bcf34SKevin Tang #include <linux/component.h>
7b07bcf34SKevin Tang #include <linux/delay.h>
8b07bcf34SKevin Tang #include <linux/dma-buf.h>
9b07bcf34SKevin Tang #include <linux/io.h>
10b07bcf34SKevin Tang #include <linux/module.h>
11b07bcf34SKevin Tang #include <linux/of.h>
12b07bcf34SKevin Tang #include <linux/of_graph.h>
13*722d4f06SRob Herring #include <linux/platform_device.h>
14b07bcf34SKevin Tang #include <linux/wait.h>
15b07bcf34SKevin Tang #include <linux/workqueue.h>
16b07bcf34SKevin Tang
17b07bcf34SKevin Tang #include <drm/drm_atomic_helper.h>
1890bb087fSVille Syrjälä #include <drm/drm_blend.h>
196bcfe8eaSDanilo Krummrich #include <drm/drm_fb_dma_helper.h>
20720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h>
214a83c26aSDanilo Krummrich #include <drm/drm_gem_dma_helper.h>
22b07bcf34SKevin Tang #include <drm/drm_gem_framebuffer_helper.h>
23b07bcf34SKevin Tang
24b07bcf34SKevin Tang #include "sprd_drm.h"
25b07bcf34SKevin Tang #include "sprd_dpu.h"
261c66496bSKevin Tang #include "sprd_dsi.h"
27b07bcf34SKevin Tang
28b07bcf34SKevin Tang /* Global control registers */
29b07bcf34SKevin Tang #define REG_DPU_CTRL 0x04
30b07bcf34SKevin Tang #define REG_DPU_CFG0 0x08
31b07bcf34SKevin Tang #define REG_PANEL_SIZE 0x20
32b07bcf34SKevin Tang #define REG_BLEND_SIZE 0x24
33b07bcf34SKevin Tang #define REG_BG_COLOR 0x2C
34b07bcf34SKevin Tang
35b07bcf34SKevin Tang /* Layer0 control registers */
36b07bcf34SKevin Tang #define REG_LAY_BASE_ADDR0 0x30
37b07bcf34SKevin Tang #define REG_LAY_BASE_ADDR1 0x34
38b07bcf34SKevin Tang #define REG_LAY_BASE_ADDR2 0x38
39b07bcf34SKevin Tang #define REG_LAY_CTRL 0x40
40b07bcf34SKevin Tang #define REG_LAY_SIZE 0x44
41b07bcf34SKevin Tang #define REG_LAY_PITCH 0x48
42b07bcf34SKevin Tang #define REG_LAY_POS 0x4C
43b07bcf34SKevin Tang #define REG_LAY_ALPHA 0x50
44b07bcf34SKevin Tang #define REG_LAY_CROP_START 0x5C
45b07bcf34SKevin Tang
46b07bcf34SKevin Tang /* Interrupt control registers */
47b07bcf34SKevin Tang #define REG_DPU_INT_EN 0x1E0
48b07bcf34SKevin Tang #define REG_DPU_INT_CLR 0x1E4
49b07bcf34SKevin Tang #define REG_DPU_INT_STS 0x1E8
50b07bcf34SKevin Tang
51b07bcf34SKevin Tang /* DPI control registers */
52b07bcf34SKevin Tang #define REG_DPI_CTRL 0x1F0
53b07bcf34SKevin Tang #define REG_DPI_H_TIMING 0x1F4
54b07bcf34SKevin Tang #define REG_DPI_V_TIMING 0x1F8
55b07bcf34SKevin Tang
56b07bcf34SKevin Tang /* MMU control registers */
57b07bcf34SKevin Tang #define REG_MMU_EN 0x800
58b07bcf34SKevin Tang #define REG_MMU_VPN_RANGE 0x80C
59b07bcf34SKevin Tang #define REG_MMU_PPN1 0x83C
60b07bcf34SKevin Tang #define REG_MMU_RANGE1 0x840
61b07bcf34SKevin Tang #define REG_MMU_PPN2 0x844
62b07bcf34SKevin Tang #define REG_MMU_RANGE2 0x848
63b07bcf34SKevin Tang
64b07bcf34SKevin Tang /* Global control bits */
65b07bcf34SKevin Tang #define BIT_DPU_RUN BIT(0)
66b07bcf34SKevin Tang #define BIT_DPU_STOP BIT(1)
67b07bcf34SKevin Tang #define BIT_DPU_REG_UPDATE BIT(2)
68b07bcf34SKevin Tang #define BIT_DPU_IF_EDPI BIT(0)
69b07bcf34SKevin Tang
70b07bcf34SKevin Tang /* Layer control bits */
71b07bcf34SKevin Tang #define BIT_DPU_LAY_EN BIT(0)
72b07bcf34SKevin Tang #define BIT_DPU_LAY_LAYER_ALPHA (0x01 << 2)
73b07bcf34SKevin Tang #define BIT_DPU_LAY_COMBO_ALPHA (0x02 << 2)
74b07bcf34SKevin Tang #define BIT_DPU_LAY_FORMAT_YUV422_2PLANE (0x00 << 4)
75b07bcf34SKevin Tang #define BIT_DPU_LAY_FORMAT_YUV420_2PLANE (0x01 << 4)
76b07bcf34SKevin Tang #define BIT_DPU_LAY_FORMAT_YUV420_3PLANE (0x02 << 4)
77b07bcf34SKevin Tang #define BIT_DPU_LAY_FORMAT_ARGB8888 (0x03 << 4)
78b07bcf34SKevin Tang #define BIT_DPU_LAY_FORMAT_RGB565 (0x04 << 4)
79b07bcf34SKevin Tang #define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3 (0x00 << 8)
80b07bcf34SKevin Tang #define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0 (0x01 << 8)
81b07bcf34SKevin Tang #define BIT_DPU_LAY_NO_SWITCH (0x00 << 10)
82b07bcf34SKevin Tang #define BIT_DPU_LAY_RB_OR_UV_SWITCH (0x01 << 10)
83b07bcf34SKevin Tang #define BIT_DPU_LAY_MODE_BLEND_NORMAL (0x00 << 16)
84b07bcf34SKevin Tang #define BIT_DPU_LAY_MODE_BLEND_PREMULT (0x01 << 16)
85b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_0 (0x00 << 20)
86b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_90 (0x01 << 20)
87b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_180 (0x02 << 20)
88b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_270 (0x03 << 20)
89b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_0_M (0x04 << 20)
90b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_90_M (0x05 << 20)
91b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_180_M (0x06 << 20)
92b07bcf34SKevin Tang #define BIT_DPU_LAY_ROTATION_270_M (0x07 << 20)
93b07bcf34SKevin Tang
94b07bcf34SKevin Tang /* Interrupt control & status bits */
95b07bcf34SKevin Tang #define BIT_DPU_INT_DONE BIT(0)
96b07bcf34SKevin Tang #define BIT_DPU_INT_TE BIT(1)
97b07bcf34SKevin Tang #define BIT_DPU_INT_ERR BIT(2)
98b07bcf34SKevin Tang #define BIT_DPU_INT_UPDATE_DONE BIT(4)
99b07bcf34SKevin Tang #define BIT_DPU_INT_VSYNC BIT(5)
100b07bcf34SKevin Tang
101b07bcf34SKevin Tang /* DPI control bits */
102b07bcf34SKevin Tang #define BIT_DPU_EDPI_TE_EN BIT(8)
103b07bcf34SKevin Tang #define BIT_DPU_EDPI_FROM_EXTERNAL_PAD BIT(10)
104b07bcf34SKevin Tang #define BIT_DPU_DPI_HALT_EN BIT(16)
105b07bcf34SKevin Tang
106b07bcf34SKevin Tang static const u32 layer_fmts[] = {
107b07bcf34SKevin Tang DRM_FORMAT_XRGB8888,
108b07bcf34SKevin Tang DRM_FORMAT_XBGR8888,
109b07bcf34SKevin Tang DRM_FORMAT_ARGB8888,
110b07bcf34SKevin Tang DRM_FORMAT_ABGR8888,
111b07bcf34SKevin Tang DRM_FORMAT_RGBA8888,
112b07bcf34SKevin Tang DRM_FORMAT_BGRA8888,
113b07bcf34SKevin Tang DRM_FORMAT_RGBX8888,
114b07bcf34SKevin Tang DRM_FORMAT_RGB565,
115b07bcf34SKevin Tang DRM_FORMAT_BGR565,
116b07bcf34SKevin Tang DRM_FORMAT_NV12,
117b07bcf34SKevin Tang DRM_FORMAT_NV21,
118b07bcf34SKevin Tang DRM_FORMAT_NV16,
119b07bcf34SKevin Tang DRM_FORMAT_NV61,
120b07bcf34SKevin Tang DRM_FORMAT_YUV420,
121b07bcf34SKevin Tang DRM_FORMAT_YVU420,
122b07bcf34SKevin Tang };
123b07bcf34SKevin Tang
124b07bcf34SKevin Tang struct sprd_plane {
125b07bcf34SKevin Tang struct drm_plane base;
126b07bcf34SKevin Tang };
127b07bcf34SKevin Tang
dpu_wait_stop_done(struct sprd_dpu * dpu)128b07bcf34SKevin Tang static int dpu_wait_stop_done(struct sprd_dpu *dpu)
129b07bcf34SKevin Tang {
130b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
131b07bcf34SKevin Tang int rc;
132b07bcf34SKevin Tang
133b07bcf34SKevin Tang if (ctx->stopped)
134b07bcf34SKevin Tang return 0;
135b07bcf34SKevin Tang
136b07bcf34SKevin Tang rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
137b07bcf34SKevin Tang msecs_to_jiffies(500));
138b07bcf34SKevin Tang ctx->evt_stop = false;
139b07bcf34SKevin Tang
140b07bcf34SKevin Tang ctx->stopped = true;
141b07bcf34SKevin Tang
142b07bcf34SKevin Tang if (!rc) {
143b07bcf34SKevin Tang drm_err(dpu->drm, "dpu wait for stop done time out!\n");
144b07bcf34SKevin Tang return -ETIMEDOUT;
145b07bcf34SKevin Tang }
146b07bcf34SKevin Tang
147b07bcf34SKevin Tang return 0;
148b07bcf34SKevin Tang }
149b07bcf34SKevin Tang
dpu_wait_update_done(struct sprd_dpu * dpu)150b07bcf34SKevin Tang static int dpu_wait_update_done(struct sprd_dpu *dpu)
151b07bcf34SKevin Tang {
152b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
153b07bcf34SKevin Tang int rc;
154b07bcf34SKevin Tang
155b07bcf34SKevin Tang ctx->evt_update = false;
156b07bcf34SKevin Tang
157b07bcf34SKevin Tang rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
158b07bcf34SKevin Tang msecs_to_jiffies(500));
159b07bcf34SKevin Tang
160b07bcf34SKevin Tang if (!rc) {
161b07bcf34SKevin Tang drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
162b07bcf34SKevin Tang return -ETIMEDOUT;
163b07bcf34SKevin Tang }
164b07bcf34SKevin Tang
165b07bcf34SKevin Tang return 0;
166b07bcf34SKevin Tang }
167b07bcf34SKevin Tang
drm_format_to_dpu(struct drm_framebuffer * fb)168b07bcf34SKevin Tang static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
169b07bcf34SKevin Tang {
170b07bcf34SKevin Tang u32 format = 0;
171b07bcf34SKevin Tang
172b07bcf34SKevin Tang switch (fb->format->format) {
173b07bcf34SKevin Tang case DRM_FORMAT_BGRA8888:
174b07bcf34SKevin Tang /* BGRA8888 -> ARGB8888 */
175b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
176b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_ARGB8888;
177b07bcf34SKevin Tang break;
178b07bcf34SKevin Tang case DRM_FORMAT_RGBX8888:
179b07bcf34SKevin Tang case DRM_FORMAT_RGBA8888:
180b07bcf34SKevin Tang /* RGBA8888 -> ABGR8888 */
181b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
182b07bcf34SKevin Tang fallthrough;
183b07bcf34SKevin Tang case DRM_FORMAT_ABGR8888:
184b07bcf34SKevin Tang /* RB switch */
185b07bcf34SKevin Tang format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
186b07bcf34SKevin Tang fallthrough;
187b07bcf34SKevin Tang case DRM_FORMAT_ARGB8888:
188b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_ARGB8888;
189b07bcf34SKevin Tang break;
190b07bcf34SKevin Tang case DRM_FORMAT_XBGR8888:
191b07bcf34SKevin Tang /* RB switch */
192b07bcf34SKevin Tang format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
193b07bcf34SKevin Tang fallthrough;
194b07bcf34SKevin Tang case DRM_FORMAT_XRGB8888:
195b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_ARGB8888;
196b07bcf34SKevin Tang break;
197b07bcf34SKevin Tang case DRM_FORMAT_BGR565:
198b07bcf34SKevin Tang /* RB switch */
199b07bcf34SKevin Tang format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
200b07bcf34SKevin Tang fallthrough;
201b07bcf34SKevin Tang case DRM_FORMAT_RGB565:
202b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_RGB565;
203b07bcf34SKevin Tang break;
204b07bcf34SKevin Tang case DRM_FORMAT_NV12:
205b07bcf34SKevin Tang /* 2-Lane: Yuv420 */
206b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
207b07bcf34SKevin Tang /* Y endian */
208b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
209b07bcf34SKevin Tang /* UV endian */
210b07bcf34SKevin Tang format |= BIT_DPU_LAY_NO_SWITCH;
211b07bcf34SKevin Tang break;
212b07bcf34SKevin Tang case DRM_FORMAT_NV21:
213b07bcf34SKevin Tang /* 2-Lane: Yuv420 */
214b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
215b07bcf34SKevin Tang /* Y endian */
216b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
217b07bcf34SKevin Tang /* UV endian */
218b07bcf34SKevin Tang format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
219b07bcf34SKevin Tang break;
220b07bcf34SKevin Tang case DRM_FORMAT_NV16:
221b07bcf34SKevin Tang /* 2-Lane: Yuv422 */
222b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
223b07bcf34SKevin Tang /* Y endian */
224b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
225b07bcf34SKevin Tang /* UV endian */
226b07bcf34SKevin Tang format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
227b07bcf34SKevin Tang break;
228b07bcf34SKevin Tang case DRM_FORMAT_NV61:
229b07bcf34SKevin Tang /* 2-Lane: Yuv422 */
230b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
231b07bcf34SKevin Tang /* Y endian */
232b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
233b07bcf34SKevin Tang /* UV endian */
234b07bcf34SKevin Tang format |= BIT_DPU_LAY_NO_SWITCH;
235b07bcf34SKevin Tang break;
236b07bcf34SKevin Tang case DRM_FORMAT_YUV420:
237b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
238b07bcf34SKevin Tang /* Y endian */
239b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
240b07bcf34SKevin Tang /* UV endian */
241b07bcf34SKevin Tang format |= BIT_DPU_LAY_NO_SWITCH;
242b07bcf34SKevin Tang break;
243b07bcf34SKevin Tang case DRM_FORMAT_YVU420:
244b07bcf34SKevin Tang format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
245b07bcf34SKevin Tang /* Y endian */
246b07bcf34SKevin Tang format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
247b07bcf34SKevin Tang /* UV endian */
248b07bcf34SKevin Tang format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
249b07bcf34SKevin Tang break;
250b07bcf34SKevin Tang default:
251b07bcf34SKevin Tang break;
252b07bcf34SKevin Tang }
253b07bcf34SKevin Tang
254b07bcf34SKevin Tang return format;
255b07bcf34SKevin Tang }
256b07bcf34SKevin Tang
drm_rotation_to_dpu(struct drm_plane_state * state)257b07bcf34SKevin Tang static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
258b07bcf34SKevin Tang {
259b07bcf34SKevin Tang u32 rotation = 0;
260b07bcf34SKevin Tang
261b07bcf34SKevin Tang switch (state->rotation) {
262b07bcf34SKevin Tang default:
263b07bcf34SKevin Tang case DRM_MODE_ROTATE_0:
264b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_0;
265b07bcf34SKevin Tang break;
266b07bcf34SKevin Tang case DRM_MODE_ROTATE_90:
267b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_90;
268b07bcf34SKevin Tang break;
269b07bcf34SKevin Tang case DRM_MODE_ROTATE_180:
270b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_180;
271b07bcf34SKevin Tang break;
272b07bcf34SKevin Tang case DRM_MODE_ROTATE_270:
273b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_270;
274b07bcf34SKevin Tang break;
275b07bcf34SKevin Tang case DRM_MODE_REFLECT_Y:
276b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_180_M;
277b07bcf34SKevin Tang break;
278b07bcf34SKevin Tang case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
279b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_90_M;
280b07bcf34SKevin Tang break;
281b07bcf34SKevin Tang case DRM_MODE_REFLECT_X:
282b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_0_M;
283b07bcf34SKevin Tang break;
284b07bcf34SKevin Tang case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
285b07bcf34SKevin Tang rotation = BIT_DPU_LAY_ROTATION_270_M;
286b07bcf34SKevin Tang break;
287b07bcf34SKevin Tang }
288b07bcf34SKevin Tang
289b07bcf34SKevin Tang return rotation;
290b07bcf34SKevin Tang }
291b07bcf34SKevin Tang
drm_blend_to_dpu(struct drm_plane_state * state)292b07bcf34SKevin Tang static u32 drm_blend_to_dpu(struct drm_plane_state *state)
293b07bcf34SKevin Tang {
294b07bcf34SKevin Tang u32 blend = 0;
295b07bcf34SKevin Tang
296b07bcf34SKevin Tang switch (state->pixel_blend_mode) {
297b07bcf34SKevin Tang case DRM_MODE_BLEND_COVERAGE:
298b07bcf34SKevin Tang /* alpha mode select - combo alpha */
299b07bcf34SKevin Tang blend |= BIT_DPU_LAY_COMBO_ALPHA;
300b07bcf34SKevin Tang /* Normal mode */
301b07bcf34SKevin Tang blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
302b07bcf34SKevin Tang break;
303b07bcf34SKevin Tang case DRM_MODE_BLEND_PREMULTI:
304b07bcf34SKevin Tang /* alpha mode select - combo alpha */
305b07bcf34SKevin Tang blend |= BIT_DPU_LAY_COMBO_ALPHA;
306b07bcf34SKevin Tang /* Pre-mult mode */
307b07bcf34SKevin Tang blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
308b07bcf34SKevin Tang break;
309b07bcf34SKevin Tang case DRM_MODE_BLEND_PIXEL_NONE:
310b07bcf34SKevin Tang default:
311b07bcf34SKevin Tang /* don't do blending, maybe RGBX */
312b07bcf34SKevin Tang /* alpha mode select - layer alpha */
313b07bcf34SKevin Tang blend |= BIT_DPU_LAY_LAYER_ALPHA;
314b07bcf34SKevin Tang break;
315b07bcf34SKevin Tang }
316b07bcf34SKevin Tang
317b07bcf34SKevin Tang return blend;
318b07bcf34SKevin Tang }
319b07bcf34SKevin Tang
sprd_dpu_layer(struct sprd_dpu * dpu,struct drm_plane_state * state)320b07bcf34SKevin Tang static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state)
321b07bcf34SKevin Tang {
322b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
3234a83c26aSDanilo Krummrich struct drm_gem_dma_object *dma_obj;
324b07bcf34SKevin Tang struct drm_framebuffer *fb = state->fb;
325b07bcf34SKevin Tang u32 addr, size, offset, pitch, blend, format, rotation;
326b07bcf34SKevin Tang u32 src_x = state->src_x >> 16;
327b07bcf34SKevin Tang u32 src_y = state->src_y >> 16;
328b07bcf34SKevin Tang u32 src_w = state->src_w >> 16;
329b07bcf34SKevin Tang u32 src_h = state->src_h >> 16;
330b07bcf34SKevin Tang u32 dst_x = state->crtc_x;
331b07bcf34SKevin Tang u32 dst_y = state->crtc_y;
332b07bcf34SKevin Tang u32 alpha = state->alpha;
333b07bcf34SKevin Tang u32 index = state->zpos;
334b07bcf34SKevin Tang int i;
335b07bcf34SKevin Tang
336b07bcf34SKevin Tang offset = (dst_x & 0xffff) | (dst_y << 16);
337b07bcf34SKevin Tang size = (src_w & 0xffff) | (src_h << 16);
338b07bcf34SKevin Tang
339b07bcf34SKevin Tang for (i = 0; i < fb->format->num_planes; i++) {
3404a83c26aSDanilo Krummrich dma_obj = drm_fb_dma_get_gem_obj(fb, i);
3418c30eeccSDanilo Krummrich addr = dma_obj->dma_addr + fb->offsets[i];
342b07bcf34SKevin Tang
343b07bcf34SKevin Tang if (i == 0)
344b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
345b07bcf34SKevin Tang else if (i == 1)
346b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);
347b07bcf34SKevin Tang else
348b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);
349b07bcf34SKevin Tang }
350b07bcf34SKevin Tang
351b07bcf34SKevin Tang if (fb->format->num_planes == 3) {
352b07bcf34SKevin Tang /* UV pitch is 1/2 of Y pitch */
353b07bcf34SKevin Tang pitch = (fb->pitches[0] / fb->format->cpp[0]) |
354b07bcf34SKevin Tang (fb->pitches[0] / fb->format->cpp[0] << 15);
355b07bcf34SKevin Tang } else {
356b07bcf34SKevin Tang pitch = fb->pitches[0] / fb->format->cpp[0];
357b07bcf34SKevin Tang }
358b07bcf34SKevin Tang
359b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_POS, offset, index);
360b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_SIZE, size, index);
361b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_CROP_START,
362b07bcf34SKevin Tang src_y << 16 | src_x, index);
363b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);
364b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);
365b07bcf34SKevin Tang
366b07bcf34SKevin Tang format = drm_format_to_dpu(fb);
367b07bcf34SKevin Tang blend = drm_blend_to_dpu(state);
368b07bcf34SKevin Tang rotation = drm_rotation_to_dpu(state);
369b07bcf34SKevin Tang
370b07bcf34SKevin Tang layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
371b07bcf34SKevin Tang format |
372b07bcf34SKevin Tang blend |
373b07bcf34SKevin Tang rotation,
374b07bcf34SKevin Tang index);
375b07bcf34SKevin Tang }
376b07bcf34SKevin Tang
sprd_dpu_flip(struct sprd_dpu * dpu)377b07bcf34SKevin Tang static void sprd_dpu_flip(struct sprd_dpu *dpu)
378b07bcf34SKevin Tang {
379b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
380b07bcf34SKevin Tang
381b07bcf34SKevin Tang /*
382b07bcf34SKevin Tang * Make sure the dpu is in stop status. DPU has no shadow
383b07bcf34SKevin Tang * registers in EDPI mode. So the config registers can only be
384b07bcf34SKevin Tang * updated in the rising edge of DPU_RUN bit.
385b07bcf34SKevin Tang */
386b07bcf34SKevin Tang if (ctx->if_type == SPRD_DPU_IF_EDPI)
387b07bcf34SKevin Tang dpu_wait_stop_done(dpu);
388b07bcf34SKevin Tang
389b07bcf34SKevin Tang /* update trigger and wait */
390b07bcf34SKevin Tang if (ctx->if_type == SPRD_DPU_IF_DPI) {
391b07bcf34SKevin Tang if (!ctx->stopped) {
392b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
393b07bcf34SKevin Tang dpu_wait_update_done(dpu);
394b07bcf34SKevin Tang }
395b07bcf34SKevin Tang
396b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
397b07bcf34SKevin Tang } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
398b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
399b07bcf34SKevin Tang
400b07bcf34SKevin Tang ctx->stopped = false;
401b07bcf34SKevin Tang }
402b07bcf34SKevin Tang }
403b07bcf34SKevin Tang
sprd_dpu_init(struct sprd_dpu * dpu)404b07bcf34SKevin Tang static void sprd_dpu_init(struct sprd_dpu *dpu)
405b07bcf34SKevin Tang {
406b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
407b07bcf34SKevin Tang u32 int_mask = 0;
408b07bcf34SKevin Tang
409b07bcf34SKevin Tang writel(0x00, ctx->base + REG_BG_COLOR);
410b07bcf34SKevin Tang writel(0x00, ctx->base + REG_MMU_EN);
411b07bcf34SKevin Tang writel(0x00, ctx->base + REG_MMU_PPN1);
412b07bcf34SKevin Tang writel(0xffff, ctx->base + REG_MMU_RANGE1);
413b07bcf34SKevin Tang writel(0x00, ctx->base + REG_MMU_PPN2);
414b07bcf34SKevin Tang writel(0xffff, ctx->base + REG_MMU_RANGE2);
415b07bcf34SKevin Tang writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
416b07bcf34SKevin Tang
417b07bcf34SKevin Tang if (ctx->if_type == SPRD_DPU_IF_DPI) {
418b07bcf34SKevin Tang /* use dpi as interface */
419b07bcf34SKevin Tang dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
420b07bcf34SKevin Tang /* disable Halt function for SPRD DSI */
421b07bcf34SKevin Tang dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
422b07bcf34SKevin Tang /* select te from external pad */
423b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
424b07bcf34SKevin Tang
425b07bcf34SKevin Tang /* enable dpu update done INT */
426b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_UPDATE_DONE;
427b07bcf34SKevin Tang /* enable dpu done INT */
428b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_DONE;
429b07bcf34SKevin Tang /* enable dpu dpi vsync */
430b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_VSYNC;
431b07bcf34SKevin Tang /* enable dpu TE INT */
432b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_TE;
433b07bcf34SKevin Tang /* enable underflow err INT */
434b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_ERR;
435b07bcf34SKevin Tang } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
436b07bcf34SKevin Tang /* use edpi as interface */
437b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
438b07bcf34SKevin Tang /* use external te */
439b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
440b07bcf34SKevin Tang /* enable te */
441b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
442b07bcf34SKevin Tang
443b07bcf34SKevin Tang /* enable stop done INT */
444b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_DONE;
445b07bcf34SKevin Tang /* enable TE INT */
446b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_TE;
447b07bcf34SKevin Tang }
448b07bcf34SKevin Tang
449b07bcf34SKevin Tang writel(int_mask, ctx->base + REG_DPU_INT_EN);
450b07bcf34SKevin Tang }
451b07bcf34SKevin Tang
sprd_dpu_fini(struct sprd_dpu * dpu)452b07bcf34SKevin Tang static void sprd_dpu_fini(struct sprd_dpu *dpu)
453b07bcf34SKevin Tang {
454b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
455b07bcf34SKevin Tang
456b07bcf34SKevin Tang writel(0x00, ctx->base + REG_DPU_INT_EN);
457b07bcf34SKevin Tang writel(0xff, ctx->base + REG_DPU_INT_CLR);
458b07bcf34SKevin Tang }
459b07bcf34SKevin Tang
sprd_dpi_init(struct sprd_dpu * dpu)460b07bcf34SKevin Tang static void sprd_dpi_init(struct sprd_dpu *dpu)
461b07bcf34SKevin Tang {
462b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
463b07bcf34SKevin Tang u32 reg_val;
464b07bcf34SKevin Tang u32 size;
465b07bcf34SKevin Tang
466b07bcf34SKevin Tang size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
467b07bcf34SKevin Tang writel(size, ctx->base + REG_PANEL_SIZE);
468b07bcf34SKevin Tang writel(size, ctx->base + REG_BLEND_SIZE);
469b07bcf34SKevin Tang
470b07bcf34SKevin Tang if (ctx->if_type == SPRD_DPU_IF_DPI) {
471b07bcf34SKevin Tang /* set dpi timing */
472b07bcf34SKevin Tang reg_val = ctx->vm.hsync_len << 0 |
473b07bcf34SKevin Tang ctx->vm.hback_porch << 8 |
474b07bcf34SKevin Tang ctx->vm.hfront_porch << 20;
475b07bcf34SKevin Tang writel(reg_val, ctx->base + REG_DPI_H_TIMING);
476b07bcf34SKevin Tang
477b07bcf34SKevin Tang reg_val = ctx->vm.vsync_len << 0 |
478b07bcf34SKevin Tang ctx->vm.vback_porch << 8 |
479b07bcf34SKevin Tang ctx->vm.vfront_porch << 20;
480b07bcf34SKevin Tang writel(reg_val, ctx->base + REG_DPI_V_TIMING);
481b07bcf34SKevin Tang }
482b07bcf34SKevin Tang }
483b07bcf34SKevin Tang
sprd_dpu_run(struct sprd_dpu * dpu)484b07bcf34SKevin Tang void sprd_dpu_run(struct sprd_dpu *dpu)
485b07bcf34SKevin Tang {
486b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
487b07bcf34SKevin Tang
488b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
489b07bcf34SKevin Tang
490b07bcf34SKevin Tang ctx->stopped = false;
491b07bcf34SKevin Tang }
492b07bcf34SKevin Tang
sprd_dpu_stop(struct sprd_dpu * dpu)493b07bcf34SKevin Tang void sprd_dpu_stop(struct sprd_dpu *dpu)
494b07bcf34SKevin Tang {
495b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
496b07bcf34SKevin Tang
497b07bcf34SKevin Tang if (ctx->if_type == SPRD_DPU_IF_DPI)
498b07bcf34SKevin Tang dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
499b07bcf34SKevin Tang
500b07bcf34SKevin Tang dpu_wait_stop_done(dpu);
501b07bcf34SKevin Tang }
502b07bcf34SKevin Tang
sprd_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)503b07bcf34SKevin Tang static int sprd_plane_atomic_check(struct drm_plane *plane,
504b07bcf34SKevin Tang struct drm_atomic_state *state)
505b07bcf34SKevin Tang {
506b07bcf34SKevin Tang struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
507b07bcf34SKevin Tang plane);
508b07bcf34SKevin Tang struct drm_crtc_state *crtc_state;
509b07bcf34SKevin Tang u32 fmt;
510b07bcf34SKevin Tang
511b07bcf34SKevin Tang if (!plane_state->fb || !plane_state->crtc)
512b07bcf34SKevin Tang return 0;
513b07bcf34SKevin Tang
514b07bcf34SKevin Tang fmt = drm_format_to_dpu(plane_state->fb);
515b07bcf34SKevin Tang if (!fmt)
516b07bcf34SKevin Tang return -EINVAL;
517b07bcf34SKevin Tang
518b07bcf34SKevin Tang crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);
519b07bcf34SKevin Tang if (IS_ERR(crtc_state))
520b07bcf34SKevin Tang return PTR_ERR(crtc_state);
521b07bcf34SKevin Tang
522b07bcf34SKevin Tang return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
523cce32e4eSThomas Zimmermann DRM_PLANE_NO_SCALING,
524cce32e4eSThomas Zimmermann DRM_PLANE_NO_SCALING,
525b07bcf34SKevin Tang true, true);
526b07bcf34SKevin Tang }
527b07bcf34SKevin Tang
sprd_plane_atomic_update(struct drm_plane * drm_plane,struct drm_atomic_state * state)528b07bcf34SKevin Tang static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
529b07bcf34SKevin Tang struct drm_atomic_state *state)
530b07bcf34SKevin Tang {
531b07bcf34SKevin Tang struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
532b07bcf34SKevin Tang drm_plane);
533b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(new_state->crtc);
534b07bcf34SKevin Tang
535b07bcf34SKevin Tang /* start configure dpu layers */
536b07bcf34SKevin Tang sprd_dpu_layer(dpu, new_state);
537b07bcf34SKevin Tang }
538b07bcf34SKevin Tang
sprd_plane_atomic_disable(struct drm_plane * drm_plane,struct drm_atomic_state * state)539b07bcf34SKevin Tang static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
540b07bcf34SKevin Tang struct drm_atomic_state *state)
541b07bcf34SKevin Tang {
542b07bcf34SKevin Tang struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
543b07bcf34SKevin Tang drm_plane);
544b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
545b07bcf34SKevin Tang
546b07bcf34SKevin Tang layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);
547b07bcf34SKevin Tang }
548b07bcf34SKevin Tang
sprd_plane_create_properties(struct sprd_plane * plane,int index)549b07bcf34SKevin Tang static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
550b07bcf34SKevin Tang {
551b07bcf34SKevin Tang unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
552b07bcf34SKevin Tang BIT(DRM_MODE_BLEND_PREMULTI) |
553b07bcf34SKevin Tang BIT(DRM_MODE_BLEND_COVERAGE);
554b07bcf34SKevin Tang
555b07bcf34SKevin Tang /* create rotation property */
556b07bcf34SKevin Tang drm_plane_create_rotation_property(&plane->base,
557b07bcf34SKevin Tang DRM_MODE_ROTATE_0,
558b07bcf34SKevin Tang DRM_MODE_ROTATE_MASK |
559b07bcf34SKevin Tang DRM_MODE_REFLECT_MASK);
560b07bcf34SKevin Tang
561b07bcf34SKevin Tang /* create alpha property */
562b07bcf34SKevin Tang drm_plane_create_alpha_property(&plane->base);
563b07bcf34SKevin Tang
564b07bcf34SKevin Tang /* create blend mode property */
565b07bcf34SKevin Tang drm_plane_create_blend_mode_property(&plane->base, supported_modes);
566b07bcf34SKevin Tang
567b07bcf34SKevin Tang /* create zpos property */
568b07bcf34SKevin Tang drm_plane_create_zpos_immutable_property(&plane->base, index);
569b07bcf34SKevin Tang }
570b07bcf34SKevin Tang
571b07bcf34SKevin Tang static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
572b07bcf34SKevin Tang .atomic_check = sprd_plane_atomic_check,
573b07bcf34SKevin Tang .atomic_update = sprd_plane_atomic_update,
574b07bcf34SKevin Tang .atomic_disable = sprd_plane_atomic_disable,
575b07bcf34SKevin Tang };
576b07bcf34SKevin Tang
577b07bcf34SKevin Tang static const struct drm_plane_funcs sprd_plane_funcs = {
578b07bcf34SKevin Tang .update_plane = drm_atomic_helper_update_plane,
579b07bcf34SKevin Tang .disable_plane = drm_atomic_helper_disable_plane,
580b07bcf34SKevin Tang .destroy = drm_plane_cleanup,
581b07bcf34SKevin Tang .reset = drm_atomic_helper_plane_reset,
582b07bcf34SKevin Tang .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
583b07bcf34SKevin Tang .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
584b07bcf34SKevin Tang };
585b07bcf34SKevin Tang
sprd_planes_init(struct drm_device * drm)586b07bcf34SKevin Tang static struct sprd_plane *sprd_planes_init(struct drm_device *drm)
587b07bcf34SKevin Tang {
588b07bcf34SKevin Tang struct sprd_plane *plane, *primary;
589b07bcf34SKevin Tang enum drm_plane_type plane_type;
590b07bcf34SKevin Tang int i;
591b07bcf34SKevin Tang
592b07bcf34SKevin Tang for (i = 0; i < 6; i++) {
593b07bcf34SKevin Tang plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
594b07bcf34SKevin Tang DRM_PLANE_TYPE_OVERLAY;
595b07bcf34SKevin Tang
596b07bcf34SKevin Tang plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
597b07bcf34SKevin Tang 1, &sprd_plane_funcs,
598b07bcf34SKevin Tang layer_fmts, ARRAY_SIZE(layer_fmts),
599b07bcf34SKevin Tang NULL, plane_type, NULL);
600b07bcf34SKevin Tang if (IS_ERR(plane)) {
601b07bcf34SKevin Tang drm_err(drm, "failed to init drm plane: %d\n", i);
602b07bcf34SKevin Tang return plane;
603b07bcf34SKevin Tang }
604b07bcf34SKevin Tang
605b07bcf34SKevin Tang drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
606b07bcf34SKevin Tang
607b07bcf34SKevin Tang sprd_plane_create_properties(plane, i);
608b07bcf34SKevin Tang
609b07bcf34SKevin Tang if (i == 0)
610b07bcf34SKevin Tang primary = plane;
611b07bcf34SKevin Tang }
612b07bcf34SKevin Tang
613b07bcf34SKevin Tang return primary;
614b07bcf34SKevin Tang }
615b07bcf34SKevin Tang
sprd_crtc_mode_set_nofb(struct drm_crtc * crtc)616b07bcf34SKevin Tang static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
617b07bcf34SKevin Tang {
618b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(crtc);
619b07bcf34SKevin Tang struct drm_display_mode *mode = &crtc->state->adjusted_mode;
6201c66496bSKevin Tang struct drm_encoder *encoder;
6211c66496bSKevin Tang struct sprd_dsi *dsi;
622b07bcf34SKevin Tang
623b07bcf34SKevin Tang drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
624b07bcf34SKevin Tang
6251c66496bSKevin Tang drm_for_each_encoder_mask(encoder, crtc->dev,
6261c66496bSKevin Tang crtc->state->encoder_mask) {
6271c66496bSKevin Tang dsi = encoder_to_dsi(encoder);
6281c66496bSKevin Tang
6291c66496bSKevin Tang if (dsi->slave->mode_flags & MIPI_DSI_MODE_VIDEO)
6301c66496bSKevin Tang dpu->ctx.if_type = SPRD_DPU_IF_DPI;
6311c66496bSKevin Tang else
6321c66496bSKevin Tang dpu->ctx.if_type = SPRD_DPU_IF_EDPI;
6331c66496bSKevin Tang }
6341c66496bSKevin Tang
635b07bcf34SKevin Tang sprd_dpi_init(dpu);
636b07bcf34SKevin Tang }
637b07bcf34SKevin Tang
sprd_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)638b07bcf34SKevin Tang static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
639b07bcf34SKevin Tang struct drm_atomic_state *state)
640b07bcf34SKevin Tang {
641b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(crtc);
642b07bcf34SKevin Tang
643b07bcf34SKevin Tang sprd_dpu_init(dpu);
644b07bcf34SKevin Tang
645b07bcf34SKevin Tang drm_crtc_vblank_on(&dpu->base);
646b07bcf34SKevin Tang }
647b07bcf34SKevin Tang
sprd_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)648b07bcf34SKevin Tang static void sprd_crtc_atomic_disable(struct drm_crtc *crtc,
649b07bcf34SKevin Tang struct drm_atomic_state *state)
650b07bcf34SKevin Tang {
651b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(crtc);
652b07bcf34SKevin Tang struct drm_device *drm = dpu->base.dev;
653b07bcf34SKevin Tang
654b07bcf34SKevin Tang drm_crtc_vblank_off(&dpu->base);
655b07bcf34SKevin Tang
656b07bcf34SKevin Tang sprd_dpu_fini(dpu);
657b07bcf34SKevin Tang
658b07bcf34SKevin Tang spin_lock_irq(&drm->event_lock);
659b07bcf34SKevin Tang if (crtc->state->event) {
660b07bcf34SKevin Tang drm_crtc_send_vblank_event(crtc, crtc->state->event);
661b07bcf34SKevin Tang crtc->state->event = NULL;
662b07bcf34SKevin Tang }
663b07bcf34SKevin Tang spin_unlock_irq(&drm->event_lock);
664b07bcf34SKevin Tang }
665b07bcf34SKevin Tang
sprd_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)666b07bcf34SKevin Tang static void sprd_crtc_atomic_flush(struct drm_crtc *crtc,
667b07bcf34SKevin Tang struct drm_atomic_state *state)
668b07bcf34SKevin Tang
669b07bcf34SKevin Tang {
670b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(crtc);
671b07bcf34SKevin Tang struct drm_device *drm = dpu->base.dev;
672b07bcf34SKevin Tang
673b07bcf34SKevin Tang sprd_dpu_flip(dpu);
674b07bcf34SKevin Tang
675b07bcf34SKevin Tang spin_lock_irq(&drm->event_lock);
676b07bcf34SKevin Tang if (crtc->state->event) {
677b07bcf34SKevin Tang drm_crtc_send_vblank_event(crtc, crtc->state->event);
678b07bcf34SKevin Tang crtc->state->event = NULL;
679b07bcf34SKevin Tang }
680b07bcf34SKevin Tang spin_unlock_irq(&drm->event_lock);
681b07bcf34SKevin Tang }
682b07bcf34SKevin Tang
sprd_crtc_enable_vblank(struct drm_crtc * crtc)683b07bcf34SKevin Tang static int sprd_crtc_enable_vblank(struct drm_crtc *crtc)
684b07bcf34SKevin Tang {
685b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(crtc);
686b07bcf34SKevin Tang
687b07bcf34SKevin Tang dpu_reg_set(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
688b07bcf34SKevin Tang
689b07bcf34SKevin Tang return 0;
690b07bcf34SKevin Tang }
691b07bcf34SKevin Tang
sprd_crtc_disable_vblank(struct drm_crtc * crtc)692b07bcf34SKevin Tang static void sprd_crtc_disable_vblank(struct drm_crtc *crtc)
693b07bcf34SKevin Tang {
694b07bcf34SKevin Tang struct sprd_dpu *dpu = to_sprd_crtc(crtc);
695b07bcf34SKevin Tang
696b07bcf34SKevin Tang dpu_reg_clr(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
697b07bcf34SKevin Tang }
698b07bcf34SKevin Tang
699b07bcf34SKevin Tang static const struct drm_crtc_helper_funcs sprd_crtc_helper_funcs = {
700b07bcf34SKevin Tang .mode_set_nofb = sprd_crtc_mode_set_nofb,
701b07bcf34SKevin Tang .atomic_flush = sprd_crtc_atomic_flush,
702b07bcf34SKevin Tang .atomic_enable = sprd_crtc_atomic_enable,
703b07bcf34SKevin Tang .atomic_disable = sprd_crtc_atomic_disable,
704b07bcf34SKevin Tang };
705b07bcf34SKevin Tang
706b07bcf34SKevin Tang static const struct drm_crtc_funcs sprd_crtc_funcs = {
707b07bcf34SKevin Tang .destroy = drm_crtc_cleanup,
708b07bcf34SKevin Tang .set_config = drm_atomic_helper_set_config,
709b07bcf34SKevin Tang .page_flip = drm_atomic_helper_page_flip,
710b07bcf34SKevin Tang .reset = drm_atomic_helper_crtc_reset,
711b07bcf34SKevin Tang .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
712b07bcf34SKevin Tang .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
713b07bcf34SKevin Tang .enable_vblank = sprd_crtc_enable_vblank,
714b07bcf34SKevin Tang .disable_vblank = sprd_crtc_disable_vblank,
715b07bcf34SKevin Tang };
716b07bcf34SKevin Tang
sprd_crtc_init(struct drm_device * drm,struct drm_plane * primary,struct device * dev)717b07bcf34SKevin Tang static struct sprd_dpu *sprd_crtc_init(struct drm_device *drm,
718b07bcf34SKevin Tang struct drm_plane *primary, struct device *dev)
719b07bcf34SKevin Tang {
720b07bcf34SKevin Tang struct device_node *port;
721b07bcf34SKevin Tang struct sprd_dpu *dpu;
722b07bcf34SKevin Tang
723b07bcf34SKevin Tang dpu = drmm_crtc_alloc_with_planes(drm, struct sprd_dpu, base,
724b07bcf34SKevin Tang primary, NULL,
725b07bcf34SKevin Tang &sprd_crtc_funcs, NULL);
726b07bcf34SKevin Tang if (IS_ERR(dpu)) {
727b07bcf34SKevin Tang drm_err(drm, "failed to init crtc\n");
728b07bcf34SKevin Tang return dpu;
729b07bcf34SKevin Tang }
730b07bcf34SKevin Tang drm_crtc_helper_add(&dpu->base, &sprd_crtc_helper_funcs);
731b07bcf34SKevin Tang
732b07bcf34SKevin Tang /*
733b07bcf34SKevin Tang * set crtc port so that drm_of_find_possible_crtcs call works
734b07bcf34SKevin Tang */
735b07bcf34SKevin Tang port = of_graph_get_port_by_id(dev->of_node, 0);
736b07bcf34SKevin Tang if (!port) {
737b07bcf34SKevin Tang drm_err(drm, "failed to found crtc output port for %s\n",
738b07bcf34SKevin Tang dev->of_node->full_name);
739b07bcf34SKevin Tang return ERR_PTR(-EINVAL);
740b07bcf34SKevin Tang }
741b07bcf34SKevin Tang dpu->base.port = port;
742b07bcf34SKevin Tang of_node_put(port);
743b07bcf34SKevin Tang
744b07bcf34SKevin Tang return dpu;
745b07bcf34SKevin Tang }
746b07bcf34SKevin Tang
sprd_dpu_isr(int irq,void * data)747b07bcf34SKevin Tang static irqreturn_t sprd_dpu_isr(int irq, void *data)
748b07bcf34SKevin Tang {
749b07bcf34SKevin Tang struct sprd_dpu *dpu = data;
750b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
751b07bcf34SKevin Tang u32 reg_val, int_mask = 0;
752b07bcf34SKevin Tang
753b07bcf34SKevin Tang reg_val = readl(ctx->base + REG_DPU_INT_STS);
754b07bcf34SKevin Tang
755b07bcf34SKevin Tang /* disable err interrupt */
756b07bcf34SKevin Tang if (reg_val & BIT_DPU_INT_ERR) {
757b07bcf34SKevin Tang int_mask |= BIT_DPU_INT_ERR;
758b07bcf34SKevin Tang drm_warn(dpu->drm, "Warning: dpu underflow!\n");
759b07bcf34SKevin Tang }
760b07bcf34SKevin Tang
761b07bcf34SKevin Tang /* dpu update done isr */
762b07bcf34SKevin Tang if (reg_val & BIT_DPU_INT_UPDATE_DONE) {
763b07bcf34SKevin Tang ctx->evt_update = true;
764b07bcf34SKevin Tang wake_up_interruptible_all(&ctx->wait_queue);
765b07bcf34SKevin Tang }
766b07bcf34SKevin Tang
767b07bcf34SKevin Tang /* dpu stop done isr */
768b07bcf34SKevin Tang if (reg_val & BIT_DPU_INT_DONE) {
769b07bcf34SKevin Tang ctx->evt_stop = true;
770b07bcf34SKevin Tang wake_up_interruptible_all(&ctx->wait_queue);
771b07bcf34SKevin Tang }
772b07bcf34SKevin Tang
773b07bcf34SKevin Tang if (reg_val & BIT_DPU_INT_VSYNC)
774b07bcf34SKevin Tang drm_crtc_handle_vblank(&dpu->base);
775b07bcf34SKevin Tang
776b07bcf34SKevin Tang writel(reg_val, ctx->base + REG_DPU_INT_CLR);
777b07bcf34SKevin Tang dpu_reg_clr(ctx, REG_DPU_INT_EN, int_mask);
778b07bcf34SKevin Tang
779b07bcf34SKevin Tang return IRQ_HANDLED;
780b07bcf34SKevin Tang }
781b07bcf34SKevin Tang
sprd_dpu_context_init(struct sprd_dpu * dpu,struct device * dev)782b07bcf34SKevin Tang static int sprd_dpu_context_init(struct sprd_dpu *dpu,
783b07bcf34SKevin Tang struct device *dev)
784b07bcf34SKevin Tang {
785b07bcf34SKevin Tang struct platform_device *pdev = to_platform_device(dev);
786b07bcf34SKevin Tang struct dpu_context *ctx = &dpu->ctx;
787b07bcf34SKevin Tang struct resource *res;
788b07bcf34SKevin Tang int ret;
789b07bcf34SKevin Tang
790b07bcf34SKevin Tang res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
79173792e6eSKevin Tang if (!res) {
79273792e6eSKevin Tang dev_err(dev, "failed to get I/O resource\n");
79373792e6eSKevin Tang return -EINVAL;
79473792e6eSKevin Tang }
79573792e6eSKevin Tang
796b07bcf34SKevin Tang ctx->base = devm_ioremap(dev, res->start, resource_size(res));
797b07bcf34SKevin Tang if (!ctx->base) {
798b07bcf34SKevin Tang dev_err(dev, "failed to map dpu registers\n");
799b07bcf34SKevin Tang return -EFAULT;
800b07bcf34SKevin Tang }
801b07bcf34SKevin Tang
802b07bcf34SKevin Tang ctx->irq = platform_get_irq(pdev, 0);
8032306f5d0SDeepak R Varma if (ctx->irq < 0)
804b07bcf34SKevin Tang return ctx->irq;
805b07bcf34SKevin Tang
806b07bcf34SKevin Tang /* disable and clear interrupts before register dpu IRQ. */
807b07bcf34SKevin Tang writel(0x00, ctx->base + REG_DPU_INT_EN);
808b07bcf34SKevin Tang writel(0xff, ctx->base + REG_DPU_INT_CLR);
809b07bcf34SKevin Tang
810b07bcf34SKevin Tang ret = devm_request_irq(dev, ctx->irq, sprd_dpu_isr,
811b07bcf34SKevin Tang IRQF_TRIGGER_NONE, "DPU", dpu);
812b07bcf34SKevin Tang if (ret) {
813b07bcf34SKevin Tang dev_err(dev, "failed to register dpu irq handler\n");
814b07bcf34SKevin Tang return ret;
815b07bcf34SKevin Tang }
816b07bcf34SKevin Tang
817b07bcf34SKevin Tang init_waitqueue_head(&ctx->wait_queue);
818b07bcf34SKevin Tang
819b07bcf34SKevin Tang return 0;
820b07bcf34SKevin Tang }
821b07bcf34SKevin Tang
sprd_dpu_bind(struct device * dev,struct device * master,void * data)822b07bcf34SKevin Tang static int sprd_dpu_bind(struct device *dev, struct device *master, void *data)
823b07bcf34SKevin Tang {
824b07bcf34SKevin Tang struct drm_device *drm = data;
825b07bcf34SKevin Tang struct sprd_dpu *dpu;
826b07bcf34SKevin Tang struct sprd_plane *plane;
827b07bcf34SKevin Tang int ret;
828b07bcf34SKevin Tang
829b07bcf34SKevin Tang plane = sprd_planes_init(drm);
830b07bcf34SKevin Tang if (IS_ERR(plane))
831b07bcf34SKevin Tang return PTR_ERR(plane);
832b07bcf34SKevin Tang
833b07bcf34SKevin Tang dpu = sprd_crtc_init(drm, &plane->base, dev);
834b07bcf34SKevin Tang if (IS_ERR(dpu))
835b07bcf34SKevin Tang return PTR_ERR(dpu);
836b07bcf34SKevin Tang
837b07bcf34SKevin Tang dpu->drm = drm;
838b07bcf34SKevin Tang dev_set_drvdata(dev, dpu);
839b07bcf34SKevin Tang
840b07bcf34SKevin Tang ret = sprd_dpu_context_init(dpu, dev);
841b07bcf34SKevin Tang if (ret)
842b07bcf34SKevin Tang return ret;
843b07bcf34SKevin Tang
844b07bcf34SKevin Tang return 0;
845b07bcf34SKevin Tang }
846b07bcf34SKevin Tang
847b07bcf34SKevin Tang static const struct component_ops dpu_component_ops = {
848b07bcf34SKevin Tang .bind = sprd_dpu_bind,
849b07bcf34SKevin Tang };
850b07bcf34SKevin Tang
851b07bcf34SKevin Tang static const struct of_device_id dpu_match_table[] = {
852b07bcf34SKevin Tang { .compatible = "sprd,sharkl3-dpu" },
853b07bcf34SKevin Tang { /* sentinel */ },
854b07bcf34SKevin Tang };
855b07bcf34SKevin Tang MODULE_DEVICE_TABLE(of, dpu_match_table);
856b07bcf34SKevin Tang
sprd_dpu_probe(struct platform_device * pdev)857b07bcf34SKevin Tang static int sprd_dpu_probe(struct platform_device *pdev)
858b07bcf34SKevin Tang {
859b07bcf34SKevin Tang return component_add(&pdev->dev, &dpu_component_ops);
860b07bcf34SKevin Tang }
861b07bcf34SKevin Tang
sprd_dpu_remove(struct platform_device * pdev)862b07bcf34SKevin Tang static int sprd_dpu_remove(struct platform_device *pdev)
863b07bcf34SKevin Tang {
864b07bcf34SKevin Tang component_del(&pdev->dev, &dpu_component_ops);
865b07bcf34SKevin Tang
866b07bcf34SKevin Tang return 0;
867b07bcf34SKevin Tang }
868b07bcf34SKevin Tang
869b07bcf34SKevin Tang struct platform_driver sprd_dpu_driver = {
870b07bcf34SKevin Tang .probe = sprd_dpu_probe,
871b07bcf34SKevin Tang .remove = sprd_dpu_remove,
872b07bcf34SKevin Tang .driver = {
873b07bcf34SKevin Tang .name = "sprd-dpu-drv",
874b07bcf34SKevin Tang .of_match_table = dpu_match_table,
875b07bcf34SKevin Tang },
876b07bcf34SKevin Tang };
877b07bcf34SKevin Tang
878b07bcf34SKevin Tang MODULE_AUTHOR("Leon He <leon.he@unisoc.com>");
879b07bcf34SKevin Tang MODULE_AUTHOR("Kevin Tang <kevin.tang@unisoc.com>");
880b07bcf34SKevin Tang MODULE_DESCRIPTION("Unisoc Display Controller Driver");
881b07bcf34SKevin Tang MODULE_LICENSE("GPL v2");
882