1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_plane.h> 15 #include <drm/drm_print.h> 16 17 #include "rockchip_drm_vop.h" 18 #include "rockchip_vop_reg.h" 19 #include "rockchip_drm_drv.h" 20 21 #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \ 22 { \ 23 .offset = off, \ 24 .mask = _mask, \ 25 .shift = _shift, \ 26 .write_mask = _write_mask, \ 27 .relaxed = _relaxed, \ 28 } 29 30 #define VOP_REG(off, _mask, _shift) \ 31 _VOP_REG(off, _mask, _shift, false, true) 32 33 #define VOP_REG_SYNC(off, _mask, _shift) \ 34 _VOP_REG(off, _mask, _shift, false, false) 35 36 #define VOP_REG_MASK_SYNC(off, _mask, _shift) \ 37 _VOP_REG(off, _mask, _shift, true, false) 38 39 static const uint32_t formats_win_full[] = { 40 DRM_FORMAT_XRGB8888, 41 DRM_FORMAT_ARGB8888, 42 DRM_FORMAT_XBGR8888, 43 DRM_FORMAT_ABGR8888, 44 DRM_FORMAT_RGB888, 45 DRM_FORMAT_BGR888, 46 DRM_FORMAT_RGB565, 47 DRM_FORMAT_BGR565, 48 DRM_FORMAT_NV12, 49 DRM_FORMAT_NV21, 50 DRM_FORMAT_NV16, 51 DRM_FORMAT_NV61, 52 DRM_FORMAT_NV24, 53 DRM_FORMAT_NV42, 54 }; 55 56 static const uint64_t format_modifiers_win_full[] = { 57 DRM_FORMAT_MOD_LINEAR, 58 DRM_FORMAT_MOD_INVALID, 59 }; 60 61 static const uint64_t format_modifiers_win_full_afbc[] = { 62 ROCKCHIP_AFBC_MOD, 63 DRM_FORMAT_MOD_LINEAR, 64 DRM_FORMAT_MOD_INVALID, 65 }; 66 67 static const uint32_t formats_win_lite[] = { 68 DRM_FORMAT_XRGB8888, 69 DRM_FORMAT_ARGB8888, 70 DRM_FORMAT_XBGR8888, 71 DRM_FORMAT_ABGR8888, 72 DRM_FORMAT_RGB888, 73 DRM_FORMAT_BGR888, 74 DRM_FORMAT_RGB565, 75 DRM_FORMAT_BGR565, 76 }; 77 78 static const uint64_t format_modifiers_win_lite[] = { 79 DRM_FORMAT_MOD_LINEAR, 80 DRM_FORMAT_MOD_INVALID, 81 }; 82 83 static const struct vop_scl_regs rk3036_win0_scl = { 84 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 85 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 86 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 87 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 88 }; 89 90 static const struct vop_scl_regs rk3036_win1_scl = { 91 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0), 92 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16), 93 }; 94 95 static const struct vop_win_phy rk3036_win0_data = { 96 .scl = &rk3036_win0_scl, 97 .data_formats = formats_win_full, 98 .nformats = ARRAY_SIZE(formats_win_full), 99 .format_modifiers = format_modifiers_win_full, 100 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 101 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 102 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 103 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 104 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 105 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 106 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 107 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 108 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 109 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 110 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 111 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0), 112 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), 113 }; 114 115 static const struct vop_win_phy rk3036_win1_data = { 116 .scl = &rk3036_win1_scl, 117 .data_formats = formats_win_lite, 118 .nformats = ARRAY_SIZE(formats_win_lite), 119 .format_modifiers = format_modifiers_win_lite, 120 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 121 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 122 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 123 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), 124 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), 125 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), 126 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), 127 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 128 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19), 129 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1), 130 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), 131 }; 132 133 static const struct vop_win_data rk3036_vop_win_data[] = { 134 { .base = 0x00, .phy = &rk3036_win0_data, 135 .type = DRM_PLANE_TYPE_PRIMARY }, 136 { .base = 0x00, .phy = &rk3036_win1_data, 137 .type = DRM_PLANE_TYPE_CURSOR }, 138 }; 139 140 static const int rk3036_vop_intrs[] = { 141 DSP_HOLD_VALID_INTR, 142 FS_INTR, 143 LINE_FLAG_INTR, 144 BUS_ERROR_INTR, 145 }; 146 147 static const struct vop_intr rk3036_intr = { 148 .intrs = rk3036_vop_intrs, 149 .nintrs = ARRAY_SIZE(rk3036_vop_intrs), 150 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 151 .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0), 152 .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4), 153 .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8), 154 }; 155 156 static const struct vop_modeset rk3036_modeset = { 157 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 158 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 159 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 160 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 161 }; 162 163 static const struct vop_output rk3036_output = { 164 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 165 }; 166 167 static const struct vop_common rk3036_common = { 168 .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), 169 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 170 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 171 .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27), 172 .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11), 173 .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10), 174 .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), 175 }; 176 177 static const struct vop_data rk3036_vop = { 178 .intr = &rk3036_intr, 179 .common = &rk3036_common, 180 .modeset = &rk3036_modeset, 181 .output = &rk3036_output, 182 .win = rk3036_vop_win_data, 183 .win_size = ARRAY_SIZE(rk3036_vop_win_data), 184 .max_output = { 1920, 1080 }, 185 }; 186 187 static const struct vop_win_phy rk3126_win1_data = { 188 .data_formats = formats_win_lite, 189 .nformats = ARRAY_SIZE(formats_win_lite), 190 .format_modifiers = format_modifiers_win_lite, 191 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 192 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 193 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 194 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0), 195 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), 196 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), 197 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 198 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19), 199 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1), 200 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), 201 }; 202 203 static const struct vop_win_data rk3126_vop_win_data[] = { 204 { .base = 0x00, .phy = &rk3036_win0_data, 205 .type = DRM_PLANE_TYPE_PRIMARY }, 206 { .base = 0x00, .phy = &rk3126_win1_data, 207 .type = DRM_PLANE_TYPE_CURSOR }, 208 }; 209 210 static const struct vop_data rk3126_vop = { 211 .intr = &rk3036_intr, 212 .common = &rk3036_common, 213 .modeset = &rk3036_modeset, 214 .output = &rk3036_output, 215 .win = rk3126_vop_win_data, 216 .win_size = ARRAY_SIZE(rk3126_vop_win_data), 217 .max_output = { 1920, 1080 }, 218 }; 219 220 static const int px30_vop_intrs[] = { 221 FS_INTR, 222 0, 0, 223 LINE_FLAG_INTR, 224 0, 225 BUS_ERROR_INTR, 226 0, 0, 227 DSP_HOLD_VALID_INTR, 228 }; 229 230 static const struct vop_intr px30_intr = { 231 .intrs = px30_vop_intrs, 232 .nintrs = ARRAY_SIZE(px30_vop_intrs), 233 .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 0), 234 .status = VOP_REG_MASK_SYNC(PX30_INTR_STATUS, 0xffff, 0), 235 .enable = VOP_REG_MASK_SYNC(PX30_INTR_EN, 0xffff, 0), 236 .clear = VOP_REG_MASK_SYNC(PX30_INTR_CLEAR, 0xffff, 0), 237 }; 238 239 static const struct vop_common px30_common = { 240 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), 241 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), 242 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), 243 .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8), 244 .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7), 245 .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6), 246 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), 247 }; 248 249 static const struct vop_modeset px30_modeset = { 250 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 251 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0), 252 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 253 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0), 254 }; 255 256 static const struct vop_output px30_output = { 257 .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1), 258 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2), 259 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), 260 .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25), 261 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26), 262 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), 263 }; 264 265 static const struct vop_scl_regs px30_win_scl = { 266 .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 267 .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 268 .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 269 .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 270 }; 271 272 static const struct vop_win_phy px30_win0_data = { 273 .scl = &px30_win_scl, 274 .data_formats = formats_win_full, 275 .nformats = ARRAY_SIZE(formats_win_full), 276 .format_modifiers = format_modifiers_win_full, 277 .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0), 278 .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1), 279 .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12), 280 .uv_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 15), 281 .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0), 282 .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0), 283 .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0), 284 .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0), 285 .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0), 286 .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0), 287 .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16), 288 .alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2), 289 .alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1), 290 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0), 291 }; 292 293 static const struct vop_win_phy px30_win1_data = { 294 .data_formats = formats_win_lite, 295 .nformats = ARRAY_SIZE(formats_win_lite), 296 .format_modifiers = format_modifiers_win_lite, 297 .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0), 298 .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4), 299 .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12), 300 .uv_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 15), 301 .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0), 302 .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0), 303 .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0), 304 .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0), 305 .alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2), 306 .alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1), 307 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0), 308 }; 309 310 static const struct vop_win_phy px30_win2_data = { 311 .data_formats = formats_win_lite, 312 .nformats = ARRAY_SIZE(formats_win_lite), 313 .format_modifiers = format_modifiers_win_lite, 314 .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4), 315 .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0), 316 .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5), 317 .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20), 318 .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0), 319 .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0), 320 .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0), 321 .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0), 322 .alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2), 323 .alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1), 324 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0), 325 }; 326 327 static const struct vop_win_data px30_vop_big_win_data[] = { 328 { .base = 0x00, .phy = &px30_win0_data, 329 .type = DRM_PLANE_TYPE_PRIMARY }, 330 { .base = 0x00, .phy = &px30_win1_data, 331 .type = DRM_PLANE_TYPE_OVERLAY }, 332 { .base = 0x00, .phy = &px30_win2_data, 333 .type = DRM_PLANE_TYPE_CURSOR }, 334 }; 335 336 static const struct vop_data px30_vop_big = { 337 .version = VOP_VERSION(2, 6), 338 .intr = &px30_intr, 339 .feature = VOP_FEATURE_INTERNAL_RGB, 340 .common = &px30_common, 341 .modeset = &px30_modeset, 342 .output = &px30_output, 343 .win = px30_vop_big_win_data, 344 .win_size = ARRAY_SIZE(px30_vop_big_win_data), 345 .max_output = { 1920, 1080 }, 346 }; 347 348 static const struct vop_win_data px30_vop_lit_win_data[] = { 349 { .base = 0x00, .phy = &px30_win1_data, 350 .type = DRM_PLANE_TYPE_PRIMARY }, 351 }; 352 353 static const struct vop_data px30_vop_lit = { 354 .version = VOP_VERSION(2, 5), 355 .intr = &px30_intr, 356 .feature = VOP_FEATURE_INTERNAL_RGB, 357 .common = &px30_common, 358 .modeset = &px30_modeset, 359 .output = &px30_output, 360 .win = px30_vop_lit_win_data, 361 .win_size = ARRAY_SIZE(px30_vop_lit_win_data), 362 .max_output = { 1920, 1080 }, 363 }; 364 365 static const struct vop_scl_regs rk3066_win_scl = { 366 .scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 367 .scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 368 .scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 369 .scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 370 }; 371 372 static const struct vop_win_phy rk3066_win0_data = { 373 .scl = &rk3066_win_scl, 374 .data_formats = formats_win_full, 375 .nformats = ARRAY_SIZE(formats_win_full), 376 .format_modifiers = format_modifiers_win_full, 377 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0), 378 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 4), 379 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 19), 380 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 22), 381 .act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0), 382 .dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0), 383 .dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0), 384 .yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0), 385 .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0), 386 .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0), 387 .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16), 388 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21), 389 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0), 390 }; 391 392 static const struct vop_win_phy rk3066_win1_data = { 393 .data_formats = formats_win_full, 394 .nformats = ARRAY_SIZE(formats_win_full), 395 .format_modifiers = format_modifiers_win_full, 396 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1), 397 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 7), 398 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 23), 399 .uv_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 26), 400 .act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0), 401 .dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0), 402 .dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0), 403 .yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0), 404 .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0), 405 .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0), 406 .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16), 407 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22), 408 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1), 409 }; 410 411 static const struct vop_win_phy rk3066_win2_data = { 412 .data_formats = formats_win_lite, 413 .nformats = ARRAY_SIZE(formats_win_lite), 414 .format_modifiers = format_modifiers_win_lite, 415 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2), 416 .format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 10), 417 .rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 27), 418 .dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0), 419 .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0), 420 .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0), 421 .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0), 422 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23), 423 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2), 424 }; 425 426 static const struct vop_modeset rk3066_modeset = { 427 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 428 .hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0), 429 .vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 430 .vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0), 431 }; 432 433 static const struct vop_output rk3066_output = { 434 .pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4), 435 }; 436 437 static const struct vop_common rk3066_common = { 438 .dma_stop = VOP_REG(RK3066_SYS_CTRL0, 0x1, 0), 439 .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1), 440 .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0), 441 .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0), 442 .dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11), 443 .dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10), 444 .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24), 445 .dither_up = VOP_REG(RK3066_DSP_CTRL0, 0x1, 9), 446 .dsp_lut_en = VOP_REG(RK3066_SYS_CTRL1, 0x1, 31), 447 .data_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 25), 448 }; 449 450 static const struct vop_win_data rk3066_vop_win_data[] = { 451 { .base = 0x00, .phy = &rk3066_win0_data, 452 .type = DRM_PLANE_TYPE_PRIMARY }, 453 { .base = 0x00, .phy = &rk3066_win1_data, 454 .type = DRM_PLANE_TYPE_OVERLAY }, 455 { .base = 0x00, .phy = &rk3066_win2_data, 456 .type = DRM_PLANE_TYPE_CURSOR }, 457 }; 458 459 static const int rk3066_vop_intrs[] = { 460 /* 461 * hs_start interrupt fires at frame-start, so serves 462 * the same purpose as dsp_hold in the driver. 463 */ 464 DSP_HOLD_VALID_INTR, 465 FS_INTR, 466 LINE_FLAG_INTR, 467 BUS_ERROR_INTR, 468 }; 469 470 static const struct vop_intr rk3066_intr = { 471 .intrs = rk3066_vop_intrs, 472 .nintrs = ARRAY_SIZE(rk3066_vop_intrs), 473 .line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12), 474 .status = VOP_REG(RK3066_INT_STATUS, 0xf, 0), 475 .enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4), 476 .clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8), 477 }; 478 479 static const struct vop_data rk3066_vop = { 480 .version = VOP_VERSION(2, 1), 481 .intr = &rk3066_intr, 482 .common = &rk3066_common, 483 .modeset = &rk3066_modeset, 484 .output = &rk3066_output, 485 .win = rk3066_vop_win_data, 486 .win_size = ARRAY_SIZE(rk3066_vop_win_data), 487 .max_output = { 1920, 1080 }, 488 }; 489 490 static const struct vop_scl_regs rk3188_win_scl = { 491 .scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 492 .scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 493 .scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 494 .scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 495 }; 496 497 static const struct vop_win_phy rk3188_win0_data = { 498 .scl = &rk3188_win_scl, 499 .data_formats = formats_win_full, 500 .nformats = ARRAY_SIZE(formats_win_full), 501 .format_modifiers = format_modifiers_win_full, 502 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0), 503 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3), 504 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15), 505 .uv_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 18), 506 .act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0), 507 .dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0), 508 .dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0), 509 .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0), 510 .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0), 511 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0), 512 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 18), 513 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0), 514 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29), 515 }; 516 517 static const struct vop_win_phy rk3188_win1_data = { 518 .data_formats = formats_win_lite, 519 .nformats = ARRAY_SIZE(formats_win_lite), 520 .format_modifiers = format_modifiers_win_lite, 521 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1), 522 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6), 523 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19), 524 /* no act_info on window1 */ 525 .dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0), 526 .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0), 527 .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0), 528 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16), 529 .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 19), 530 .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 1), 531 .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29), 532 }; 533 534 static const struct vop_modeset rk3188_modeset = { 535 .htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 536 .hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0), 537 .vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 538 .vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0), 539 }; 540 541 static const struct vop_output rk3188_output = { 542 .pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4), 543 }; 544 545 static const struct vop_common rk3188_common = { 546 .gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31), 547 .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30), 548 .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0), 549 .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0), 550 .dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27), 551 .dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11), 552 .dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10), 553 .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 24), 554 .dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9), 555 .dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28), 556 .data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25), 557 }; 558 559 static const struct vop_win_data rk3188_vop_win_data[] = { 560 { .base = 0x00, .phy = &rk3188_win0_data, 561 .type = DRM_PLANE_TYPE_PRIMARY }, 562 { .base = 0x00, .phy = &rk3188_win1_data, 563 .type = DRM_PLANE_TYPE_CURSOR }, 564 }; 565 566 static const int rk3188_vop_intrs[] = { 567 /* 568 * hs_start interrupt fires at frame-start, so serves 569 * the same purpose as dsp_hold in the driver. 570 */ 571 DSP_HOLD_VALID_INTR, 572 FS_INTR, 573 LINE_FLAG_INTR, 574 BUS_ERROR_INTR, 575 }; 576 577 static const struct vop_intr rk3188_vop_intr = { 578 .intrs = rk3188_vop_intrs, 579 .nintrs = ARRAY_SIZE(rk3188_vop_intrs), 580 .line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12), 581 .status = VOP_REG(RK3188_INT_STATUS, 0xf, 0), 582 .enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4), 583 .clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8), 584 }; 585 586 static const struct vop_data rk3188_vop = { 587 .intr = &rk3188_vop_intr, 588 .common = &rk3188_common, 589 .modeset = &rk3188_modeset, 590 .output = &rk3188_output, 591 .win = rk3188_vop_win_data, 592 .win_size = ARRAY_SIZE(rk3188_vop_win_data), 593 .feature = VOP_FEATURE_INTERNAL_RGB, 594 .max_output = { 2048, 1536 }, 595 }; 596 597 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 598 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 599 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 600 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 601 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 602 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 603 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 604 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 605 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 606 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 607 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 608 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 609 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 610 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 611 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 612 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 613 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 614 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 615 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 616 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 617 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 618 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 619 }; 620 621 static const struct vop_scl_regs rk3288_win_full_scl = { 622 .ext = &rk3288_win_full_scl_ext, 623 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 624 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 625 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 626 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 627 }; 628 629 static const struct vop_win_phy rk3288_win01_data = { 630 .scl = &rk3288_win_full_scl, 631 .data_formats = formats_win_full, 632 .nformats = ARRAY_SIZE(formats_win_full), 633 .format_modifiers = format_modifiers_win_full, 634 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 635 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 636 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 637 .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), 638 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 639 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 640 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 641 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 642 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 643 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 644 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 645 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 646 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0), 647 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0), 648 }; 649 650 static const struct vop_win_phy rk3288_win23_data = { 651 .data_formats = formats_win_lite, 652 .nformats = ARRAY_SIZE(formats_win_lite), 653 .format_modifiers = format_modifiers_win_lite, 654 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4), 655 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 656 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1), 657 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12), 658 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0), 659 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0), 660 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0), 661 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0), 662 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 663 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0), 664 }; 665 666 static const struct vop_modeset rk3288_modeset = { 667 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 668 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 669 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 670 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 671 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 672 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 673 }; 674 675 static const struct vop_output rk3288_output = { 676 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), 677 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 678 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 679 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 680 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 681 }; 682 683 static const struct vop_common rk3288_common = { 684 .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), 685 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 686 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), 687 .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4), 688 .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3), 689 .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2), 690 .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1), 691 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 692 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 693 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), 694 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 695 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 696 .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), 697 }; 698 699 /* 700 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 701 * special support to get alpha blending working. For now, just use overlay 702 * window 3 for the drm cursor. 703 * 704 */ 705 static const struct vop_win_data rk3288_vop_win_data[] = { 706 { .base = 0x00, .phy = &rk3288_win01_data, 707 .type = DRM_PLANE_TYPE_PRIMARY }, 708 { .base = 0x40, .phy = &rk3288_win01_data, 709 .type = DRM_PLANE_TYPE_OVERLAY }, 710 { .base = 0x00, .phy = &rk3288_win23_data, 711 .type = DRM_PLANE_TYPE_OVERLAY }, 712 { .base = 0x50, .phy = &rk3288_win23_data, 713 .type = DRM_PLANE_TYPE_CURSOR }, 714 }; 715 716 static const int rk3288_vop_intrs[] = { 717 DSP_HOLD_VALID_INTR, 718 FS_INTR, 719 LINE_FLAG_INTR, 720 BUS_ERROR_INTR, 721 }; 722 723 static const struct vop_intr rk3288_vop_intr = { 724 .intrs = rk3288_vop_intrs, 725 .nintrs = ARRAY_SIZE(rk3288_vop_intrs), 726 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 727 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0), 728 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4), 729 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), 730 }; 731 732 static const struct vop_data rk3288_vop = { 733 .version = VOP_VERSION(3, 1), 734 .feature = VOP_FEATURE_OUTPUT_RGB10, 735 .intr = &rk3288_vop_intr, 736 .common = &rk3288_common, 737 .modeset = &rk3288_modeset, 738 .output = &rk3288_output, 739 .win = rk3288_vop_win_data, 740 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 741 .lut_size = 1024, 742 /* 743 * This is the maximum resolution for the VOPB, the VOPL can only do 744 * 2560x1600, but we can't distinguish them as they have the same 745 * compatible. 746 */ 747 .max_output = { 3840, 2160 }, 748 }; 749 750 static const int rk3368_vop_intrs[] = { 751 FS_INTR, 752 0, 0, 753 LINE_FLAG_INTR, 754 0, 755 BUS_ERROR_INTR, 756 0, 0, 0, 0, 0, 0, 0, 757 DSP_HOLD_VALID_INTR, 758 }; 759 760 static const struct vop_intr rk3368_vop_intr = { 761 .intrs = rk3368_vop_intrs, 762 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 763 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 764 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 765 .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0), 766 .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0), 767 .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0), 768 }; 769 770 static const struct vop_win_phy rk3368_win01_data = { 771 .scl = &rk3288_win_full_scl, 772 .data_formats = formats_win_full, 773 .nformats = ARRAY_SIZE(formats_win_full), 774 .format_modifiers = format_modifiers_win_full, 775 .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), 776 .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), 777 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), 778 .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15), 779 .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), 780 .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), 781 .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0), 782 .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0), 783 .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0), 784 .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0), 785 .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0), 786 .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0), 787 .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16), 788 .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 789 .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0), 790 .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0), 791 }; 792 793 static const struct vop_win_phy rk3368_win23_data = { 794 .data_formats = formats_win_lite, 795 .nformats = ARRAY_SIZE(formats_win_lite), 796 .format_modifiers = format_modifiers_win_lite, 797 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0), 798 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 799 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 800 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 801 .y_mir_en = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15), 802 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 803 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 804 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 805 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 806 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 807 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0), 808 }; 809 810 static const struct vop_win_data rk3368_vop_win_data[] = { 811 { .base = 0x00, .phy = &rk3368_win01_data, 812 .type = DRM_PLANE_TYPE_PRIMARY }, 813 { .base = 0x40, .phy = &rk3368_win01_data, 814 .type = DRM_PLANE_TYPE_OVERLAY }, 815 { .base = 0x00, .phy = &rk3368_win23_data, 816 .type = DRM_PLANE_TYPE_OVERLAY }, 817 { .base = 0x50, .phy = &rk3368_win23_data, 818 .type = DRM_PLANE_TYPE_CURSOR }, 819 }; 820 821 static const struct vop_output rk3368_output = { 822 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19), 823 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23), 824 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27), 825 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31), 826 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16), 827 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20), 828 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24), 829 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28), 830 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 831 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 832 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 833 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 834 }; 835 836 static const struct vop_misc rk3368_misc = { 837 .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11), 838 }; 839 840 static const struct vop_data rk3368_vop = { 841 .version = VOP_VERSION(3, 2), 842 .intr = &rk3368_vop_intr, 843 .common = &rk3288_common, 844 .modeset = &rk3288_modeset, 845 .output = &rk3368_output, 846 .misc = &rk3368_misc, 847 .win = rk3368_vop_win_data, 848 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 849 .max_output = { 4096, 2160 }, 850 }; 851 852 static const struct vop_intr rk3366_vop_intr = { 853 .intrs = rk3368_vop_intrs, 854 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 855 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 856 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 857 .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0), 858 .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0), 859 .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0), 860 }; 861 862 static const struct vop_data rk3366_vop = { 863 .version = VOP_VERSION(3, 4), 864 .intr = &rk3366_vop_intr, 865 .common = &rk3288_common, 866 .modeset = &rk3288_modeset, 867 .output = &rk3368_output, 868 .misc = &rk3368_misc, 869 .win = rk3368_vop_win_data, 870 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 871 .max_output = { 4096, 2160 }, 872 }; 873 874 static const struct vop_output rk3399_output = { 875 .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19), 876 .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19), 877 .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23), 878 .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27), 879 .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31), 880 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16), 881 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16), 882 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20), 883 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24), 884 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28), 885 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 886 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 887 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 888 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 889 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 890 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 891 }; 892 893 static const struct vop_common rk3399_common = { 894 .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), 895 .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), 896 .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20), 897 .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4), 898 .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3), 899 .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2), 900 .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1), 901 .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), 902 .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0), 903 .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7), 904 .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1), 905 .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), 906 .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), 907 .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), 908 .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), 909 }; 910 911 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { 912 .y2r_coefficients = { 913 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), 914 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 16), 915 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 0), 916 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 16), 917 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 0), 918 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 16), 919 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 0), 920 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 16), 921 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 16, 0xffff, 0), 922 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 20, 0xffffffff, 0), 923 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 24, 0xffffffff, 0), 924 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 28, 0xffffffff, 0), 925 }, 926 }; 927 928 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win23_data = { }; 929 930 static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { 931 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, 932 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1) }, 933 { .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data, 934 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9) }, 935 { .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data }, 936 { .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data }, 937 938 }; 939 940 static const struct vop_win_phy rk3399_win01_data = { 941 .scl = &rk3288_win_full_scl, 942 .data_formats = formats_win_full, 943 .nformats = ARRAY_SIZE(formats_win_full), 944 .format_modifiers = format_modifiers_win_full_afbc, 945 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 946 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 947 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 948 .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), 949 .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21), 950 .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22), 951 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 952 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 953 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 954 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 955 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 956 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 957 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 958 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 959 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0), 960 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0), 961 }; 962 963 /* 964 * rk3399 vop big windows register layout is same as rk3288, but we 965 * have a separate rk3399 win data array here so that we can advertise 966 * AFBC on the primary plane. 967 */ 968 static const struct vop_win_data rk3399_vop_win_data[] = { 969 { .base = 0x00, .phy = &rk3399_win01_data, 970 .type = DRM_PLANE_TYPE_PRIMARY }, 971 { .base = 0x40, .phy = &rk3368_win01_data, 972 .type = DRM_PLANE_TYPE_OVERLAY }, 973 { .base = 0x00, .phy = &rk3368_win23_data, 974 .type = DRM_PLANE_TYPE_OVERLAY }, 975 { .base = 0x50, .phy = &rk3368_win23_data, 976 .type = DRM_PLANE_TYPE_CURSOR }, 977 }; 978 979 static const struct vop_afbc rk3399_vop_afbc = { 980 .rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3), 981 .enable = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0), 982 .win_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1), 983 .format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16), 984 .hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21), 985 .hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0), 986 .pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0), 987 }; 988 989 static const struct vop_data rk3399_vop_big = { 990 .version = VOP_VERSION(3, 5), 991 .feature = VOP_FEATURE_OUTPUT_RGB10, 992 .intr = &rk3366_vop_intr, 993 .common = &rk3399_common, 994 .modeset = &rk3288_modeset, 995 .output = &rk3399_output, 996 .afbc = &rk3399_vop_afbc, 997 .misc = &rk3368_misc, 998 .win = rk3399_vop_win_data, 999 .win_size = ARRAY_SIZE(rk3399_vop_win_data), 1000 .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, 1001 .lut_size = 1024, 1002 .max_output = { 4096, 2160 }, 1003 }; 1004 1005 static const struct vop_win_data rk3399_vop_lit_win_data[] = { 1006 { .base = 0x00, .phy = &rk3368_win01_data, 1007 .type = DRM_PLANE_TYPE_PRIMARY }, 1008 { .base = 0x00, .phy = &rk3368_win23_data, 1009 .type = DRM_PLANE_TYPE_CURSOR}, 1010 }; 1011 1012 static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { 1013 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, 1014 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1)}, 1015 { .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data }, 1016 }; 1017 1018 static const struct vop_data rk3399_vop_lit = { 1019 .version = VOP_VERSION(3, 6), 1020 .intr = &rk3366_vop_intr, 1021 .common = &rk3399_common, 1022 .modeset = &rk3288_modeset, 1023 .output = &rk3399_output, 1024 .misc = &rk3368_misc, 1025 .win = rk3399_vop_lit_win_data, 1026 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), 1027 .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, 1028 .lut_size = 256, 1029 .max_output = { 2560, 1600 }, 1030 }; 1031 1032 static const struct vop_win_data rk3228_vop_win_data[] = { 1033 { .base = 0x00, .phy = &rk3288_win01_data, 1034 .type = DRM_PLANE_TYPE_PRIMARY }, 1035 { .base = 0x40, .phy = &rk3288_win01_data, 1036 .type = DRM_PLANE_TYPE_CURSOR }, 1037 }; 1038 1039 static const struct vop_data rk3228_vop = { 1040 .version = VOP_VERSION(3, 7), 1041 .feature = VOP_FEATURE_OUTPUT_RGB10, 1042 .intr = &rk3366_vop_intr, 1043 .common = &rk3288_common, 1044 .modeset = &rk3288_modeset, 1045 .output = &rk3399_output, 1046 .misc = &rk3368_misc, 1047 .win = rk3228_vop_win_data, 1048 .win_size = ARRAY_SIZE(rk3228_vop_win_data), 1049 .max_output = { 4096, 2160 }, 1050 }; 1051 1052 static const struct vop_modeset rk3328_modeset = { 1053 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 1054 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 1055 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 1056 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 1057 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 1058 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 1059 }; 1060 1061 static const struct vop_output rk3328_output = { 1062 .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19), 1063 .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23), 1064 .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27), 1065 .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31), 1066 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 1067 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 1068 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 1069 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 1070 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16), 1071 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20), 1072 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24), 1073 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28), 1074 }; 1075 1076 static const struct vop_misc rk3328_misc = { 1077 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 1078 }; 1079 1080 static const struct vop_common rk3328_common = { 1081 .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22), 1082 .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4), 1083 .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3), 1084 .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2), 1085 .pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1), 1086 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 1087 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 1088 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 1089 .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), 1090 }; 1091 1092 static const struct vop_intr rk3328_vop_intr = { 1093 .intrs = rk3368_vop_intrs, 1094 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 1095 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 1096 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 1097 .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0), 1098 .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0), 1099 .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), 1100 }; 1101 1102 static const struct vop_win_data rk3328_vop_win_data[] = { 1103 { .base = 0xd0, .phy = &rk3368_win01_data, 1104 .type = DRM_PLANE_TYPE_PRIMARY }, 1105 { .base = 0x1d0, .phy = &rk3368_win01_data, 1106 .type = DRM_PLANE_TYPE_OVERLAY }, 1107 { .base = 0x2d0, .phy = &rk3368_win01_data, 1108 .type = DRM_PLANE_TYPE_CURSOR }, 1109 }; 1110 1111 static const struct vop_data rk3328_vop = { 1112 .version = VOP_VERSION(3, 8), 1113 .feature = VOP_FEATURE_OUTPUT_RGB10, 1114 .intr = &rk3328_vop_intr, 1115 .common = &rk3328_common, 1116 .modeset = &rk3328_modeset, 1117 .output = &rk3328_output, 1118 .misc = &rk3328_misc, 1119 .win = rk3328_vop_win_data, 1120 .win_size = ARRAY_SIZE(rk3328_vop_win_data), 1121 .max_output = { 4096, 2160 }, 1122 }; 1123 1124 static const struct of_device_id vop_driver_dt_match[] = { 1125 { .compatible = "rockchip,rk3036-vop", 1126 .data = &rk3036_vop }, 1127 { .compatible = "rockchip,rk3126-vop", 1128 .data = &rk3126_vop }, 1129 { .compatible = "rockchip,px30-vop-big", 1130 .data = &px30_vop_big }, 1131 { .compatible = "rockchip,px30-vop-lit", 1132 .data = &px30_vop_lit }, 1133 { .compatible = "rockchip,rk3066-vop", 1134 .data = &rk3066_vop }, 1135 { .compatible = "rockchip,rk3188-vop", 1136 .data = &rk3188_vop }, 1137 { .compatible = "rockchip,rk3288-vop", 1138 .data = &rk3288_vop }, 1139 { .compatible = "rockchip,rk3368-vop", 1140 .data = &rk3368_vop }, 1141 { .compatible = "rockchip,rk3366-vop", 1142 .data = &rk3366_vop }, 1143 { .compatible = "rockchip,rk3399-vop-big", 1144 .data = &rk3399_vop_big }, 1145 { .compatible = "rockchip,rk3399-vop-lit", 1146 .data = &rk3399_vop_lit }, 1147 { .compatible = "rockchip,rk3228-vop", 1148 .data = &rk3228_vop }, 1149 { .compatible = "rockchip,rk3328-vop", 1150 .data = &rk3328_vop }, 1151 {}, 1152 }; 1153 MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 1154 1155 static int vop_probe(struct platform_device *pdev) 1156 { 1157 struct device *dev = &pdev->dev; 1158 1159 if (!dev->of_node) { 1160 DRM_DEV_ERROR(dev, "can't find vop devices\n"); 1161 return -ENODEV; 1162 } 1163 1164 return component_add(dev, &vop_component_ops); 1165 } 1166 1167 static void vop_remove(struct platform_device *pdev) 1168 { 1169 component_del(&pdev->dev, &vop_component_ops); 1170 } 1171 1172 struct platform_driver vop_platform_driver = { 1173 .probe = vop_probe, 1174 .remove_new = vop_remove, 1175 .driver = { 1176 .name = "rockchip-vop", 1177 .of_match_table = vop_driver_dt_match, 1178 }, 1179 }; 1180