1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drmP.h> 16 17 #include <linux/kernel.h> 18 #include <linux/component.h> 19 20 #include "rockchip_drm_vop.h" 21 #include "rockchip_vop_reg.h" 22 23 #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \ 24 { \ 25 .offset = off, \ 26 .mask = _mask, \ 27 .shift = _shift, \ 28 .write_mask = _write_mask, \ 29 .relaxed = _relaxed, \ 30 } 31 32 #define VOP_REG(off, _mask, _shift) \ 33 _VOP_REG(off, _mask, _shift, false, true) 34 35 #define VOP_REG_SYNC(off, _mask, _shift) \ 36 _VOP_REG(off, _mask, _shift, false, false) 37 38 #define VOP_REG_MASK_SYNC(off, _mask, _shift) \ 39 _VOP_REG(off, _mask, _shift, true, false) 40 41 static const uint32_t formats_win_full[] = { 42 DRM_FORMAT_XRGB8888, 43 DRM_FORMAT_ARGB8888, 44 DRM_FORMAT_XBGR8888, 45 DRM_FORMAT_ABGR8888, 46 DRM_FORMAT_RGB888, 47 DRM_FORMAT_BGR888, 48 DRM_FORMAT_RGB565, 49 DRM_FORMAT_BGR565, 50 DRM_FORMAT_NV12, 51 DRM_FORMAT_NV16, 52 DRM_FORMAT_NV24, 53 }; 54 55 static const uint32_t formats_win_lite[] = { 56 DRM_FORMAT_XRGB8888, 57 DRM_FORMAT_ARGB8888, 58 DRM_FORMAT_XBGR8888, 59 DRM_FORMAT_ABGR8888, 60 DRM_FORMAT_RGB888, 61 DRM_FORMAT_BGR888, 62 DRM_FORMAT_RGB565, 63 DRM_FORMAT_BGR565, 64 }; 65 66 static const struct vop_scl_regs rk3036_win_scl = { 67 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 68 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 69 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 70 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 71 }; 72 73 static const struct vop_win_phy rk3036_win0_data = { 74 .scl = &rk3036_win_scl, 75 .data_formats = formats_win_full, 76 .nformats = ARRAY_SIZE(formats_win_full), 77 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 78 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 79 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 80 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 81 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 82 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 83 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 84 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 85 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 86 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 87 }; 88 89 static const struct vop_win_phy rk3036_win1_data = { 90 .data_formats = formats_win_lite, 91 .nformats = ARRAY_SIZE(formats_win_lite), 92 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 93 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 94 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 95 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), 96 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), 97 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), 98 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), 99 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 100 }; 101 102 static const struct vop_win_data rk3036_vop_win_data[] = { 103 { .base = 0x00, .phy = &rk3036_win0_data, 104 .type = DRM_PLANE_TYPE_PRIMARY }, 105 { .base = 0x00, .phy = &rk3036_win1_data, 106 .type = DRM_PLANE_TYPE_CURSOR }, 107 }; 108 109 static const int rk3036_vop_intrs[] = { 110 DSP_HOLD_VALID_INTR, 111 FS_INTR, 112 LINE_FLAG_INTR, 113 BUS_ERROR_INTR, 114 }; 115 116 static const struct vop_intr rk3036_intr = { 117 .intrs = rk3036_vop_intrs, 118 .nintrs = ARRAY_SIZE(rk3036_vop_intrs), 119 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 120 .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0), 121 .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4), 122 .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8), 123 }; 124 125 static const struct vop_modeset rk3036_modeset = { 126 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 127 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 128 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 129 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 130 }; 131 132 static const struct vop_output rk3036_output = { 133 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 134 }; 135 136 static const struct vop_common rk3036_common = { 137 .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), 138 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 139 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 140 .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), 141 }; 142 143 static const struct vop_data rk3036_vop = { 144 .intr = &rk3036_intr, 145 .common = &rk3036_common, 146 .modeset = &rk3036_modeset, 147 .output = &rk3036_output, 148 .win = rk3036_vop_win_data, 149 .win_size = ARRAY_SIZE(rk3036_vop_win_data), 150 }; 151 152 static const struct vop_win_phy rk3126_win1_data = { 153 .data_formats = formats_win_lite, 154 .nformats = ARRAY_SIZE(formats_win_lite), 155 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 156 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 157 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 158 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0), 159 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), 160 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), 161 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 162 }; 163 164 static const struct vop_win_data rk3126_vop_win_data[] = { 165 { .base = 0x00, .phy = &rk3036_win0_data, 166 .type = DRM_PLANE_TYPE_PRIMARY }, 167 { .base = 0x00, .phy = &rk3126_win1_data, 168 .type = DRM_PLANE_TYPE_CURSOR }, 169 }; 170 171 static const struct vop_data rk3126_vop = { 172 .intr = &rk3036_intr, 173 .common = &rk3036_common, 174 .modeset = &rk3036_modeset, 175 .output = &rk3036_output, 176 .win = rk3126_vop_win_data, 177 .win_size = ARRAY_SIZE(rk3126_vop_win_data), 178 }; 179 180 static const int px30_vop_intrs[] = { 181 FS_INTR, 182 0, 0, 183 LINE_FLAG_INTR, 184 0, 185 BUS_ERROR_INTR, 186 0, 0, 187 DSP_HOLD_VALID_INTR, 188 }; 189 190 static const struct vop_intr px30_intr = { 191 .intrs = px30_vop_intrs, 192 .nintrs = ARRAY_SIZE(px30_vop_intrs), 193 .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 12), 194 .status = VOP_REG_SYNC(PX30_INTR_STATUS, 0xf, 0), 195 .enable = VOP_REG_SYNC(PX30_INTR_EN, 0xf, 4), 196 .clear = VOP_REG_SYNC(PX30_INTR_CLEAR, 0xf, 8), 197 }; 198 199 static const struct vop_common px30_common = { 200 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), 201 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), 202 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), 203 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), 204 }; 205 206 static const struct vop_modeset px30_modeset = { 207 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 208 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0), 209 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 210 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0), 211 }; 212 213 static const struct vop_output px30_output = { 214 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 1), 215 .hdmi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 9), 216 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 25), 217 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), 218 .hdmi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 8), 219 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), 220 }; 221 222 static const struct vop_scl_regs px30_win_scl = { 223 .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 224 .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 225 .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 226 .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 227 }; 228 229 static const struct vop_win_phy px30_win0_data = { 230 .scl = &px30_win_scl, 231 .data_formats = formats_win_full, 232 .nformats = ARRAY_SIZE(formats_win_full), 233 .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0), 234 .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1), 235 .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12), 236 .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0), 237 .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0), 238 .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0), 239 .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0), 240 .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0), 241 .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0), 242 .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16), 243 }; 244 245 static const struct vop_win_phy px30_win1_data = { 246 .data_formats = formats_win_lite, 247 .nformats = ARRAY_SIZE(formats_win_lite), 248 .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0), 249 .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4), 250 .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12), 251 .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0), 252 .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0), 253 .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0), 254 .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0), 255 }; 256 257 static const struct vop_win_phy px30_win2_data = { 258 .data_formats = formats_win_lite, 259 .nformats = ARRAY_SIZE(formats_win_lite), 260 .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0), 261 .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4), 262 .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5), 263 .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20), 264 .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0), 265 .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0), 266 .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0), 267 .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0), 268 }; 269 270 static const struct vop_win_data px30_vop_big_win_data[] = { 271 { .base = 0x00, .phy = &px30_win0_data, 272 .type = DRM_PLANE_TYPE_PRIMARY }, 273 { .base = 0x00, .phy = &px30_win1_data, 274 .type = DRM_PLANE_TYPE_OVERLAY }, 275 { .base = 0x00, .phy = &px30_win2_data, 276 .type = DRM_PLANE_TYPE_CURSOR }, 277 }; 278 279 static const struct vop_data px30_vop_big = { 280 .intr = &px30_intr, 281 .common = &px30_common, 282 .modeset = &px30_modeset, 283 .output = &px30_output, 284 .win = px30_vop_big_win_data, 285 .win_size = ARRAY_SIZE(px30_vop_big_win_data), 286 }; 287 288 static const struct vop_win_data px30_vop_lit_win_data[] = { 289 { .base = 0x00, .phy = &px30_win1_data, 290 .type = DRM_PLANE_TYPE_PRIMARY }, 291 }; 292 293 static const struct vop_data px30_vop_lit = { 294 .intr = &px30_intr, 295 .common = &px30_common, 296 .modeset = &px30_modeset, 297 .output = &px30_output, 298 .win = px30_vop_lit_win_data, 299 .win_size = ARRAY_SIZE(px30_vop_lit_win_data), 300 }; 301 302 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 303 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 304 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 305 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 306 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 307 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 308 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 309 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 310 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 311 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 312 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 313 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 314 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 315 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 316 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 317 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 318 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 319 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 320 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 321 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 322 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 323 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 324 }; 325 326 static const struct vop_scl_regs rk3288_win_full_scl = { 327 .ext = &rk3288_win_full_scl_ext, 328 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 329 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 330 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 331 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 332 }; 333 334 static const struct vop_win_phy rk3288_win01_data = { 335 .scl = &rk3288_win_full_scl, 336 .data_formats = formats_win_full, 337 .nformats = ARRAY_SIZE(formats_win_full), 338 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 339 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 340 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 341 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 342 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 343 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 344 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 345 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 346 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 347 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 348 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 349 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0), 350 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0), 351 }; 352 353 static const struct vop_win_phy rk3288_win23_data = { 354 .data_formats = formats_win_lite, 355 .nformats = ARRAY_SIZE(formats_win_lite), 356 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4), 357 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 358 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1), 359 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12), 360 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0), 361 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0), 362 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0), 363 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0), 364 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 365 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0), 366 }; 367 368 static const struct vop_modeset rk3288_modeset = { 369 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 370 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 371 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 372 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 373 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 374 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 375 }; 376 377 static const struct vop_output rk3288_output = { 378 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), 379 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 380 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 381 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 382 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 383 }; 384 385 static const struct vop_common rk3288_common = { 386 .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), 387 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 388 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), 389 .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1), 390 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 391 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 392 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), 393 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 394 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 395 .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), 396 }; 397 398 /* 399 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 400 * special support to get alpha blending working. For now, just use overlay 401 * window 3 for the drm cursor. 402 * 403 */ 404 static const struct vop_win_data rk3288_vop_win_data[] = { 405 { .base = 0x00, .phy = &rk3288_win01_data, 406 .type = DRM_PLANE_TYPE_PRIMARY }, 407 { .base = 0x40, .phy = &rk3288_win01_data, 408 .type = DRM_PLANE_TYPE_OVERLAY }, 409 { .base = 0x00, .phy = &rk3288_win23_data, 410 .type = DRM_PLANE_TYPE_OVERLAY }, 411 { .base = 0x50, .phy = &rk3288_win23_data, 412 .type = DRM_PLANE_TYPE_CURSOR }, 413 }; 414 415 static const int rk3288_vop_intrs[] = { 416 DSP_HOLD_VALID_INTR, 417 FS_INTR, 418 LINE_FLAG_INTR, 419 BUS_ERROR_INTR, 420 }; 421 422 static const struct vop_intr rk3288_vop_intr = { 423 .intrs = rk3288_vop_intrs, 424 .nintrs = ARRAY_SIZE(rk3288_vop_intrs), 425 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 426 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0), 427 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4), 428 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), 429 }; 430 431 static const struct vop_data rk3288_vop = { 432 .version = VOP_VERSION(3, 1), 433 .feature = VOP_FEATURE_OUTPUT_RGB10, 434 .intr = &rk3288_vop_intr, 435 .common = &rk3288_common, 436 .modeset = &rk3288_modeset, 437 .output = &rk3288_output, 438 .win = rk3288_vop_win_data, 439 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 440 }; 441 442 static const int rk3368_vop_intrs[] = { 443 FS_INTR, 444 0, 0, 445 LINE_FLAG_INTR, 446 0, 447 BUS_ERROR_INTR, 448 0, 0, 0, 0, 0, 0, 0, 449 DSP_HOLD_VALID_INTR, 450 }; 451 452 static const struct vop_intr rk3368_vop_intr = { 453 .intrs = rk3368_vop_intrs, 454 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 455 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 456 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 457 .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0), 458 .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0), 459 .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0), 460 }; 461 462 static const struct vop_win_phy rk3368_win23_data = { 463 .data_formats = formats_win_lite, 464 .nformats = ARRAY_SIZE(formats_win_lite), 465 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0), 466 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 467 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 468 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 469 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 470 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 471 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 472 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 473 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 474 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0), 475 }; 476 477 static const struct vop_win_data rk3368_vop_win_data[] = { 478 { .base = 0x00, .phy = &rk3288_win01_data, 479 .type = DRM_PLANE_TYPE_PRIMARY }, 480 { .base = 0x40, .phy = &rk3288_win01_data, 481 .type = DRM_PLANE_TYPE_OVERLAY }, 482 { .base = 0x00, .phy = &rk3368_win23_data, 483 .type = DRM_PLANE_TYPE_OVERLAY }, 484 { .base = 0x50, .phy = &rk3368_win23_data, 485 .type = DRM_PLANE_TYPE_CURSOR }, 486 }; 487 488 static const struct vop_output rk3368_output = { 489 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 490 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 491 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 492 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 493 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 494 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 495 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 496 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 497 }; 498 499 static const struct vop_misc rk3368_misc = { 500 .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11), 501 }; 502 503 static const struct vop_data rk3368_vop = { 504 .version = VOP_VERSION(3, 2), 505 .intr = &rk3368_vop_intr, 506 .common = &rk3288_common, 507 .modeset = &rk3288_modeset, 508 .output = &rk3368_output, 509 .misc = &rk3368_misc, 510 .win = rk3368_vop_win_data, 511 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 512 }; 513 514 static const struct vop_intr rk3366_vop_intr = { 515 .intrs = rk3368_vop_intrs, 516 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 517 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 518 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 519 .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0), 520 .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0), 521 .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0), 522 }; 523 524 static const struct vop_data rk3366_vop = { 525 .version = VOP_VERSION(3, 4), 526 .intr = &rk3366_vop_intr, 527 .common = &rk3288_common, 528 .modeset = &rk3288_modeset, 529 .output = &rk3368_output, 530 .misc = &rk3368_misc, 531 .win = rk3368_vop_win_data, 532 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 533 }; 534 535 static const struct vop_output rk3399_output = { 536 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), 537 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 538 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 539 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 540 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 541 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 542 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 543 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 544 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 545 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 546 }; 547 548 static const struct vop_data rk3399_vop_big = { 549 .version = VOP_VERSION(3, 5), 550 .feature = VOP_FEATURE_OUTPUT_RGB10, 551 .intr = &rk3366_vop_intr, 552 .common = &rk3288_common, 553 .modeset = &rk3288_modeset, 554 .output = &rk3399_output, 555 .misc = &rk3368_misc, 556 .win = rk3368_vop_win_data, 557 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 558 }; 559 560 static const struct vop_win_data rk3399_vop_lit_win_data[] = { 561 { .base = 0x00, .phy = &rk3288_win01_data, 562 .type = DRM_PLANE_TYPE_PRIMARY }, 563 { .base = 0x00, .phy = &rk3368_win23_data, 564 .type = DRM_PLANE_TYPE_CURSOR}, 565 }; 566 567 static const struct vop_data rk3399_vop_lit = { 568 .version = VOP_VERSION(3, 6), 569 .intr = &rk3366_vop_intr, 570 .common = &rk3288_common, 571 .modeset = &rk3288_modeset, 572 .output = &rk3399_output, 573 .misc = &rk3368_misc, 574 .win = rk3399_vop_lit_win_data, 575 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), 576 }; 577 578 static const struct vop_win_data rk3228_vop_win_data[] = { 579 { .base = 0x00, .phy = &rk3288_win01_data, 580 .type = DRM_PLANE_TYPE_PRIMARY }, 581 { .base = 0x40, .phy = &rk3288_win01_data, 582 .type = DRM_PLANE_TYPE_CURSOR }, 583 }; 584 585 static const struct vop_data rk3228_vop = { 586 .version = VOP_VERSION(3, 7), 587 .feature = VOP_FEATURE_OUTPUT_RGB10, 588 .intr = &rk3366_vop_intr, 589 .common = &rk3288_common, 590 .modeset = &rk3288_modeset, 591 .output = &rk3399_output, 592 .misc = &rk3368_misc, 593 .win = rk3228_vop_win_data, 594 .win_size = ARRAY_SIZE(rk3228_vop_win_data), 595 }; 596 597 static const struct vop_modeset rk3328_modeset = { 598 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 599 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 600 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 601 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 602 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 603 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 604 }; 605 606 static const struct vop_output rk3328_output = { 607 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 608 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 609 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 610 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 611 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 612 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 613 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 614 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 615 }; 616 617 static const struct vop_misc rk3328_misc = { 618 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 619 }; 620 621 static const struct vop_common rk3328_common = { 622 .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22), 623 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 624 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 625 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 626 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 627 .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), 628 }; 629 630 static const struct vop_intr rk3328_vop_intr = { 631 .intrs = rk3368_vop_intrs, 632 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 633 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 634 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 635 .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0), 636 .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0), 637 .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), 638 }; 639 640 static const struct vop_win_data rk3328_vop_win_data[] = { 641 { .base = 0xd0, .phy = &rk3288_win01_data, 642 .type = DRM_PLANE_TYPE_PRIMARY }, 643 { .base = 0x1d0, .phy = &rk3288_win01_data, 644 .type = DRM_PLANE_TYPE_OVERLAY }, 645 { .base = 0x2d0, .phy = &rk3288_win01_data, 646 .type = DRM_PLANE_TYPE_CURSOR }, 647 }; 648 649 static const struct vop_data rk3328_vop = { 650 .version = VOP_VERSION(3, 8), 651 .feature = VOP_FEATURE_OUTPUT_RGB10, 652 .intr = &rk3328_vop_intr, 653 .common = &rk3328_common, 654 .modeset = &rk3328_modeset, 655 .output = &rk3328_output, 656 .misc = &rk3328_misc, 657 .win = rk3328_vop_win_data, 658 .win_size = ARRAY_SIZE(rk3328_vop_win_data), 659 }; 660 661 static const struct of_device_id vop_driver_dt_match[] = { 662 { .compatible = "rockchip,rk3036-vop", 663 .data = &rk3036_vop }, 664 { .compatible = "rockchip,rk3126-vop", 665 .data = &rk3126_vop }, 666 { .compatible = "rockchip,px30-vop-big", 667 .data = &px30_vop_big }, 668 { .compatible = "rockchip,px30-vop-lit", 669 .data = &px30_vop_lit }, 670 { .compatible = "rockchip,rk3288-vop", 671 .data = &rk3288_vop }, 672 { .compatible = "rockchip,rk3368-vop", 673 .data = &rk3368_vop }, 674 { .compatible = "rockchip,rk3366-vop", 675 .data = &rk3366_vop }, 676 { .compatible = "rockchip,rk3399-vop-big", 677 .data = &rk3399_vop_big }, 678 { .compatible = "rockchip,rk3399-vop-lit", 679 .data = &rk3399_vop_lit }, 680 { .compatible = "rockchip,rk3228-vop", 681 .data = &rk3228_vop }, 682 { .compatible = "rockchip,rk3328-vop", 683 .data = &rk3328_vop }, 684 {}, 685 }; 686 MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 687 688 static int vop_probe(struct platform_device *pdev) 689 { 690 struct device *dev = &pdev->dev; 691 692 if (!dev->of_node) { 693 DRM_DEV_ERROR(dev, "can't find vop devices\n"); 694 return -ENODEV; 695 } 696 697 return component_add(dev, &vop_component_ops); 698 } 699 700 static int vop_remove(struct platform_device *pdev) 701 { 702 component_del(&pdev->dev, &vop_component_ops); 703 704 return 0; 705 } 706 707 struct platform_driver vop_platform_driver = { 708 .probe = vop_probe, 709 .remove = vop_remove, 710 .driver = { 711 .name = "rockchip-vop", 712 .of_match_table = of_match_ptr(vop_driver_dt_match), 713 }, 714 }; 715