1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drmP.h> 16 17 #include <linux/kernel.h> 18 #include <linux/component.h> 19 20 #include "rockchip_drm_vop.h" 21 #include "rockchip_vop_reg.h" 22 23 #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \ 24 { \ 25 .offset = off, \ 26 .mask = _mask, \ 27 .shift = _shift, \ 28 .write_mask = _write_mask, \ 29 .relaxed = _relaxed, \ 30 } 31 32 #define VOP_REG(off, _mask, _shift) \ 33 _VOP_REG(off, _mask, _shift, false, true) 34 35 #define VOP_REG_SYNC(off, _mask, _shift) \ 36 _VOP_REG(off, _mask, _shift, false, false) 37 38 #define VOP_REG_MASK_SYNC(off, _mask, _shift) \ 39 _VOP_REG(off, _mask, _shift, true, false) 40 41 static const uint32_t formats_win_full[] = { 42 DRM_FORMAT_XRGB8888, 43 DRM_FORMAT_ARGB8888, 44 DRM_FORMAT_XBGR8888, 45 DRM_FORMAT_ABGR8888, 46 DRM_FORMAT_RGB888, 47 DRM_FORMAT_BGR888, 48 DRM_FORMAT_RGB565, 49 DRM_FORMAT_BGR565, 50 DRM_FORMAT_NV12, 51 DRM_FORMAT_NV16, 52 DRM_FORMAT_NV24, 53 }; 54 55 static const uint32_t formats_win_lite[] = { 56 DRM_FORMAT_XRGB8888, 57 DRM_FORMAT_ARGB8888, 58 DRM_FORMAT_XBGR8888, 59 DRM_FORMAT_ABGR8888, 60 DRM_FORMAT_RGB888, 61 DRM_FORMAT_BGR888, 62 DRM_FORMAT_RGB565, 63 DRM_FORMAT_BGR565, 64 }; 65 66 static const struct vop_scl_regs rk3036_win_scl = { 67 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 68 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 69 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 70 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 71 }; 72 73 static const struct vop_win_phy rk3036_win0_data = { 74 .scl = &rk3036_win_scl, 75 .data_formats = formats_win_full, 76 .nformats = ARRAY_SIZE(formats_win_full), 77 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 78 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 79 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 80 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 81 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 82 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 83 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 84 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 85 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 86 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 87 }; 88 89 static const struct vop_win_phy rk3036_win1_data = { 90 .data_formats = formats_win_lite, 91 .nformats = ARRAY_SIZE(formats_win_lite), 92 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 93 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 94 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 95 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), 96 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), 97 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), 98 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), 99 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 100 }; 101 102 static const struct vop_win_data rk3036_vop_win_data[] = { 103 { .base = 0x00, .phy = &rk3036_win0_data, 104 .type = DRM_PLANE_TYPE_PRIMARY }, 105 { .base = 0x00, .phy = &rk3036_win1_data, 106 .type = DRM_PLANE_TYPE_CURSOR }, 107 }; 108 109 static const int rk3036_vop_intrs[] = { 110 DSP_HOLD_VALID_INTR, 111 FS_INTR, 112 LINE_FLAG_INTR, 113 BUS_ERROR_INTR, 114 }; 115 116 static const struct vop_intr rk3036_intr = { 117 .intrs = rk3036_vop_intrs, 118 .nintrs = ARRAY_SIZE(rk3036_vop_intrs), 119 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 120 .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0), 121 .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4), 122 .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8), 123 }; 124 125 static const struct vop_modeset rk3036_modeset = { 126 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 127 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 128 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 129 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 130 }; 131 132 static const struct vop_output rk3036_output = { 133 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 134 }; 135 136 static const struct vop_common rk3036_common = { 137 .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), 138 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 139 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 140 .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27), 141 .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11), 142 .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10), 143 .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), 144 }; 145 146 static const struct vop_data rk3036_vop = { 147 .intr = &rk3036_intr, 148 .common = &rk3036_common, 149 .modeset = &rk3036_modeset, 150 .output = &rk3036_output, 151 .win = rk3036_vop_win_data, 152 .win_size = ARRAY_SIZE(rk3036_vop_win_data), 153 }; 154 155 static const struct vop_win_phy rk3126_win1_data = { 156 .data_formats = formats_win_lite, 157 .nformats = ARRAY_SIZE(formats_win_lite), 158 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 159 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 160 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 161 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0), 162 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), 163 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), 164 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 165 }; 166 167 static const struct vop_win_data rk3126_vop_win_data[] = { 168 { .base = 0x00, .phy = &rk3036_win0_data, 169 .type = DRM_PLANE_TYPE_PRIMARY }, 170 { .base = 0x00, .phy = &rk3126_win1_data, 171 .type = DRM_PLANE_TYPE_CURSOR }, 172 }; 173 174 static const struct vop_data rk3126_vop = { 175 .intr = &rk3036_intr, 176 .common = &rk3036_common, 177 .modeset = &rk3036_modeset, 178 .output = &rk3036_output, 179 .win = rk3126_vop_win_data, 180 .win_size = ARRAY_SIZE(rk3126_vop_win_data), 181 }; 182 183 static const int px30_vop_intrs[] = { 184 FS_INTR, 185 0, 0, 186 LINE_FLAG_INTR, 187 0, 188 BUS_ERROR_INTR, 189 0, 0, 190 DSP_HOLD_VALID_INTR, 191 }; 192 193 static const struct vop_intr px30_intr = { 194 .intrs = px30_vop_intrs, 195 .nintrs = ARRAY_SIZE(px30_vop_intrs), 196 .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 0), 197 .status = VOP_REG_MASK_SYNC(PX30_INTR_STATUS, 0xffff, 0), 198 .enable = VOP_REG_MASK_SYNC(PX30_INTR_EN, 0xffff, 0), 199 .clear = VOP_REG_MASK_SYNC(PX30_INTR_CLEAR, 0xffff, 0), 200 }; 201 202 static const struct vop_common px30_common = { 203 .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), 204 .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), 205 .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), 206 .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8), 207 .dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7), 208 .dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6), 209 .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), 210 }; 211 212 static const struct vop_modeset px30_modeset = { 213 .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 214 .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0), 215 .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 216 .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0), 217 }; 218 219 static const struct vop_output px30_output = { 220 .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 1), 221 .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 25), 222 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), 223 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), 224 }; 225 226 static const struct vop_scl_regs px30_win_scl = { 227 .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 228 .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 229 .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 230 .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 231 }; 232 233 static const struct vop_win_phy px30_win0_data = { 234 .scl = &px30_win_scl, 235 .data_formats = formats_win_full, 236 .nformats = ARRAY_SIZE(formats_win_full), 237 .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0), 238 .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1), 239 .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12), 240 .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0), 241 .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0), 242 .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0), 243 .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0), 244 .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0), 245 .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0), 246 .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16), 247 }; 248 249 static const struct vop_win_phy px30_win1_data = { 250 .data_formats = formats_win_lite, 251 .nformats = ARRAY_SIZE(formats_win_lite), 252 .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0), 253 .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4), 254 .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12), 255 .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0), 256 .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0), 257 .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0), 258 .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0), 259 }; 260 261 static const struct vop_win_phy px30_win2_data = { 262 .data_formats = formats_win_lite, 263 .nformats = ARRAY_SIZE(formats_win_lite), 264 .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4), 265 .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0), 266 .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5), 267 .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20), 268 .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0), 269 .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0), 270 .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0), 271 .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0), 272 }; 273 274 static const struct vop_win_data px30_vop_big_win_data[] = { 275 { .base = 0x00, .phy = &px30_win0_data, 276 .type = DRM_PLANE_TYPE_PRIMARY }, 277 { .base = 0x00, .phy = &px30_win1_data, 278 .type = DRM_PLANE_TYPE_OVERLAY }, 279 { .base = 0x00, .phy = &px30_win2_data, 280 .type = DRM_PLANE_TYPE_CURSOR }, 281 }; 282 283 static const struct vop_data px30_vop_big = { 284 .intr = &px30_intr, 285 .feature = VOP_FEATURE_INTERNAL_RGB, 286 .common = &px30_common, 287 .modeset = &px30_modeset, 288 .output = &px30_output, 289 .win = px30_vop_big_win_data, 290 .win_size = ARRAY_SIZE(px30_vop_big_win_data), 291 }; 292 293 static const struct vop_win_data px30_vop_lit_win_data[] = { 294 { .base = 0x00, .phy = &px30_win1_data, 295 .type = DRM_PLANE_TYPE_PRIMARY }, 296 }; 297 298 static const struct vop_data px30_vop_lit = { 299 .intr = &px30_intr, 300 .feature = VOP_FEATURE_INTERNAL_RGB, 301 .common = &px30_common, 302 .modeset = &px30_modeset, 303 .output = &px30_output, 304 .win = px30_vop_lit_win_data, 305 .win_size = ARRAY_SIZE(px30_vop_lit_win_data), 306 }; 307 308 static const struct vop_scl_regs rk3066_win_scl = { 309 .scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 310 .scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 311 .scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 312 .scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 313 }; 314 315 static const struct vop_win_phy rk3066_win0_data = { 316 .scl = &rk3066_win_scl, 317 .data_formats = formats_win_full, 318 .nformats = ARRAY_SIZE(formats_win_full), 319 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0), 320 .format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 4), 321 .rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 19), 322 .act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0), 323 .dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0), 324 .dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0), 325 .yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0), 326 .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0), 327 .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0), 328 .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16), 329 }; 330 331 static const struct vop_win_phy rk3066_win1_data = { 332 .scl = &rk3066_win_scl, 333 .data_formats = formats_win_full, 334 .nformats = ARRAY_SIZE(formats_win_full), 335 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1), 336 .format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 7), 337 .rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 23), 338 .act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0), 339 .dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0), 340 .dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0), 341 .yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0), 342 .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0), 343 .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0), 344 .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16), 345 }; 346 347 static const struct vop_win_phy rk3066_win2_data = { 348 .data_formats = formats_win_lite, 349 .nformats = ARRAY_SIZE(formats_win_lite), 350 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2), 351 .format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 10), 352 .rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 27), 353 .dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0), 354 .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0), 355 .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0), 356 .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0), 357 }; 358 359 static const struct vop_modeset rk3066_modeset = { 360 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 361 .hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0), 362 .vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 363 .vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0), 364 }; 365 366 static const struct vop_output rk3066_output = { 367 .pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4), 368 }; 369 370 static const struct vop_common rk3066_common = { 371 .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1), 372 .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0), 373 .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0), 374 .dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11), 375 .dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10), 376 .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24), 377 }; 378 379 static const struct vop_win_data rk3066_vop_win_data[] = { 380 { .base = 0x00, .phy = &rk3066_win0_data, 381 .type = DRM_PLANE_TYPE_PRIMARY }, 382 { .base = 0x00, .phy = &rk3066_win1_data, 383 .type = DRM_PLANE_TYPE_OVERLAY }, 384 { .base = 0x00, .phy = &rk3066_win2_data, 385 .type = DRM_PLANE_TYPE_CURSOR }, 386 }; 387 388 static const int rk3066_vop_intrs[] = { 389 /* 390 * hs_start interrupt fires at frame-start, so serves 391 * the same purpose as dsp_hold in the driver. 392 */ 393 DSP_HOLD_VALID_INTR, 394 FS_INTR, 395 LINE_FLAG_INTR, 396 BUS_ERROR_INTR, 397 }; 398 399 static const struct vop_intr rk3066_intr = { 400 .intrs = rk3066_vop_intrs, 401 .nintrs = ARRAY_SIZE(rk3066_vop_intrs), 402 .line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12), 403 .status = VOP_REG(RK3066_INT_STATUS, 0xf, 0), 404 .enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4), 405 .clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8), 406 }; 407 408 static const struct vop_data rk3066_vop = { 409 .version = VOP_VERSION(2, 1), 410 .intr = &rk3066_intr, 411 .common = &rk3066_common, 412 .modeset = &rk3066_modeset, 413 .output = &rk3066_output, 414 .win = rk3066_vop_win_data, 415 .win_size = ARRAY_SIZE(rk3066_vop_win_data), 416 }; 417 418 static const struct vop_scl_regs rk3188_win_scl = { 419 .scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 420 .scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 421 .scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 422 .scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 423 }; 424 425 static const struct vop_win_phy rk3188_win0_data = { 426 .scl = &rk3188_win_scl, 427 .data_formats = formats_win_full, 428 .nformats = ARRAY_SIZE(formats_win_full), 429 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0), 430 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3), 431 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15), 432 .act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0), 433 .dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0), 434 .dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0), 435 .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0), 436 .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0), 437 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0), 438 }; 439 440 static const struct vop_win_phy rk3188_win1_data = { 441 .data_formats = formats_win_lite, 442 .nformats = ARRAY_SIZE(formats_win_lite), 443 .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1), 444 .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6), 445 .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19), 446 /* no act_info on window1 */ 447 .dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0), 448 .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0), 449 .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0), 450 .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16), 451 }; 452 453 static const struct vop_modeset rk3188_modeset = { 454 .htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 455 .hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0), 456 .vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 457 .vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0), 458 }; 459 460 static const struct vop_output rk3188_output = { 461 .pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4), 462 }; 463 464 static const struct vop_common rk3188_common = { 465 .gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31), 466 .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30), 467 .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0), 468 .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0), 469 .dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27), 470 .dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11), 471 .dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10), 472 .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x3, 24), 473 }; 474 475 static const struct vop_win_data rk3188_vop_win_data[] = { 476 { .base = 0x00, .phy = &rk3188_win0_data, 477 .type = DRM_PLANE_TYPE_PRIMARY }, 478 { .base = 0x00, .phy = &rk3188_win1_data, 479 .type = DRM_PLANE_TYPE_CURSOR }, 480 }; 481 482 static const int rk3188_vop_intrs[] = { 483 /* 484 * hs_start interrupt fires at frame-start, so serves 485 * the same purpose as dsp_hold in the driver. 486 */ 487 DSP_HOLD_VALID_INTR, 488 FS_INTR, 489 LINE_FLAG_INTR, 490 BUS_ERROR_INTR, 491 }; 492 493 static const struct vop_intr rk3188_vop_intr = { 494 .intrs = rk3188_vop_intrs, 495 .nintrs = ARRAY_SIZE(rk3188_vop_intrs), 496 .line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12), 497 .status = VOP_REG(RK3188_INT_STATUS, 0xf, 0), 498 .enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4), 499 .clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8), 500 }; 501 502 static const struct vop_data rk3188_vop = { 503 .intr = &rk3188_vop_intr, 504 .common = &rk3188_common, 505 .modeset = &rk3188_modeset, 506 .output = &rk3188_output, 507 .win = rk3188_vop_win_data, 508 .win_size = ARRAY_SIZE(rk3188_vop_win_data), 509 .feature = VOP_FEATURE_INTERNAL_RGB, 510 }; 511 512 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 513 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 514 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 515 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 516 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 517 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 518 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 519 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 520 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 521 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 522 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 523 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 524 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 525 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 526 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 527 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 528 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 529 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 530 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 531 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 532 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 533 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 534 }; 535 536 static const struct vop_scl_regs rk3288_win_full_scl = { 537 .ext = &rk3288_win_full_scl_ext, 538 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 539 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 540 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 541 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 542 }; 543 544 static const struct vop_win_phy rk3288_win01_data = { 545 .scl = &rk3288_win_full_scl, 546 .data_formats = formats_win_full, 547 .nformats = ARRAY_SIZE(formats_win_full), 548 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 549 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 550 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 551 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 552 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 553 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 554 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 555 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 556 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 557 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 558 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 559 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0), 560 .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0), 561 }; 562 563 static const struct vop_win_phy rk3288_win23_data = { 564 .data_formats = formats_win_lite, 565 .nformats = ARRAY_SIZE(formats_win_lite), 566 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4), 567 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 568 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1), 569 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12), 570 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0), 571 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0), 572 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0), 573 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0), 574 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 575 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0), 576 }; 577 578 static const struct vop_modeset rk3288_modeset = { 579 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 580 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 581 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 582 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 583 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 584 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 585 }; 586 587 static const struct vop_output rk3288_output = { 588 .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), 589 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 590 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 591 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 592 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 593 }; 594 595 static const struct vop_common rk3288_common = { 596 .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), 597 .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 598 .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), 599 .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4), 600 .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3), 601 .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2), 602 .pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1), 603 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 604 .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), 605 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 606 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 607 .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), 608 }; 609 610 /* 611 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 612 * special support to get alpha blending working. For now, just use overlay 613 * window 3 for the drm cursor. 614 * 615 */ 616 static const struct vop_win_data rk3288_vop_win_data[] = { 617 { .base = 0x00, .phy = &rk3288_win01_data, 618 .type = DRM_PLANE_TYPE_PRIMARY }, 619 { .base = 0x40, .phy = &rk3288_win01_data, 620 .type = DRM_PLANE_TYPE_OVERLAY }, 621 { .base = 0x00, .phy = &rk3288_win23_data, 622 .type = DRM_PLANE_TYPE_OVERLAY }, 623 { .base = 0x50, .phy = &rk3288_win23_data, 624 .type = DRM_PLANE_TYPE_CURSOR }, 625 }; 626 627 static const int rk3288_vop_intrs[] = { 628 DSP_HOLD_VALID_INTR, 629 FS_INTR, 630 LINE_FLAG_INTR, 631 BUS_ERROR_INTR, 632 }; 633 634 static const struct vop_intr rk3288_vop_intr = { 635 .intrs = rk3288_vop_intrs, 636 .nintrs = ARRAY_SIZE(rk3288_vop_intrs), 637 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 638 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0), 639 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4), 640 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), 641 }; 642 643 static const struct vop_data rk3288_vop = { 644 .version = VOP_VERSION(3, 1), 645 .feature = VOP_FEATURE_OUTPUT_RGB10, 646 .intr = &rk3288_vop_intr, 647 .common = &rk3288_common, 648 .modeset = &rk3288_modeset, 649 .output = &rk3288_output, 650 .win = rk3288_vop_win_data, 651 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 652 }; 653 654 static const int rk3368_vop_intrs[] = { 655 FS_INTR, 656 0, 0, 657 LINE_FLAG_INTR, 658 0, 659 BUS_ERROR_INTR, 660 0, 0, 0, 0, 0, 0, 0, 661 DSP_HOLD_VALID_INTR, 662 }; 663 664 static const struct vop_intr rk3368_vop_intr = { 665 .intrs = rk3368_vop_intrs, 666 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 667 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 668 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 669 .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0), 670 .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0), 671 .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0), 672 }; 673 674 static const struct vop_win_phy rk3368_win01_data = { 675 .scl = &rk3288_win_full_scl, 676 .data_formats = formats_win_full, 677 .nformats = ARRAY_SIZE(formats_win_full), 678 .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), 679 .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), 680 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), 681 .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), 682 .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), 683 .act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0), 684 .dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0), 685 .dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0), 686 .yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0), 687 .uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0), 688 .yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0), 689 .uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16), 690 .src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0), 691 .dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0), 692 .channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0), 693 }; 694 695 static const struct vop_win_phy rk3368_win23_data = { 696 .data_formats = formats_win_lite, 697 .nformats = ARRAY_SIZE(formats_win_lite), 698 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0), 699 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 700 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 701 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 702 .y_mir_en = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15), 703 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 704 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 705 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 706 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 707 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 708 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0), 709 }; 710 711 static const struct vop_win_data rk3368_vop_win_data[] = { 712 { .base = 0x00, .phy = &rk3368_win01_data, 713 .type = DRM_PLANE_TYPE_PRIMARY }, 714 { .base = 0x40, .phy = &rk3368_win01_data, 715 .type = DRM_PLANE_TYPE_OVERLAY }, 716 { .base = 0x00, .phy = &rk3368_win23_data, 717 .type = DRM_PLANE_TYPE_OVERLAY }, 718 { .base = 0x50, .phy = &rk3368_win23_data, 719 .type = DRM_PLANE_TYPE_CURSOR }, 720 }; 721 722 static const struct vop_output rk3368_output = { 723 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 724 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 725 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 726 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 727 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 728 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 729 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 730 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 731 }; 732 733 static const struct vop_misc rk3368_misc = { 734 .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11), 735 }; 736 737 static const struct vop_data rk3368_vop = { 738 .version = VOP_VERSION(3, 2), 739 .intr = &rk3368_vop_intr, 740 .common = &rk3288_common, 741 .modeset = &rk3288_modeset, 742 .output = &rk3368_output, 743 .misc = &rk3368_misc, 744 .win = rk3368_vop_win_data, 745 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 746 }; 747 748 static const struct vop_intr rk3366_vop_intr = { 749 .intrs = rk3368_vop_intrs, 750 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 751 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 752 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 753 .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0), 754 .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0), 755 .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0), 756 }; 757 758 static const struct vop_data rk3366_vop = { 759 .version = VOP_VERSION(3, 4), 760 .intr = &rk3366_vop_intr, 761 .common = &rk3288_common, 762 .modeset = &rk3288_modeset, 763 .output = &rk3368_output, 764 .misc = &rk3368_misc, 765 .win = rk3368_vop_win_data, 766 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 767 }; 768 769 static const struct vop_output rk3399_output = { 770 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), 771 .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 772 .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 773 .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 774 .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 775 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 776 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 777 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 778 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 779 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 780 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 781 }; 782 783 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { 784 .y2r_coefficients = { 785 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), 786 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 16), 787 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 0), 788 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 16), 789 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 0), 790 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 16), 791 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 0), 792 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 16), 793 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 16, 0xffff, 0), 794 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 20, 0xffffffff, 0), 795 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 24, 0xffffffff, 0), 796 VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 28, 0xffffffff, 0), 797 }, 798 }; 799 800 static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win23_data = { }; 801 802 static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { 803 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, 804 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1) }, 805 { .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data, 806 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9) }, 807 { .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data }, 808 { .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data }, 809 }; 810 811 static const struct vop_data rk3399_vop_big = { 812 .version = VOP_VERSION(3, 5), 813 .feature = VOP_FEATURE_OUTPUT_RGB10, 814 .intr = &rk3366_vop_intr, 815 .common = &rk3288_common, 816 .modeset = &rk3288_modeset, 817 .output = &rk3399_output, 818 .misc = &rk3368_misc, 819 .win = rk3368_vop_win_data, 820 .win_size = ARRAY_SIZE(rk3368_vop_win_data), 821 .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, 822 }; 823 824 static const struct vop_win_data rk3399_vop_lit_win_data[] = { 825 { .base = 0x00, .phy = &rk3368_win01_data, 826 .type = DRM_PLANE_TYPE_PRIMARY }, 827 { .base = 0x00, .phy = &rk3368_win23_data, 828 .type = DRM_PLANE_TYPE_CURSOR}, 829 }; 830 831 static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { 832 { .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data, 833 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1)}, 834 { .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data }, 835 }; 836 837 static const struct vop_data rk3399_vop_lit = { 838 .version = VOP_VERSION(3, 6), 839 .intr = &rk3366_vop_intr, 840 .common = &rk3288_common, 841 .modeset = &rk3288_modeset, 842 .output = &rk3399_output, 843 .misc = &rk3368_misc, 844 .win = rk3399_vop_lit_win_data, 845 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), 846 .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, 847 }; 848 849 static const struct vop_win_data rk3228_vop_win_data[] = { 850 { .base = 0x00, .phy = &rk3288_win01_data, 851 .type = DRM_PLANE_TYPE_PRIMARY }, 852 { .base = 0x40, .phy = &rk3288_win01_data, 853 .type = DRM_PLANE_TYPE_CURSOR }, 854 }; 855 856 static const struct vop_data rk3228_vop = { 857 .version = VOP_VERSION(3, 7), 858 .feature = VOP_FEATURE_OUTPUT_RGB10, 859 .intr = &rk3366_vop_intr, 860 .common = &rk3288_common, 861 .modeset = &rk3288_modeset, 862 .output = &rk3399_output, 863 .misc = &rk3368_misc, 864 .win = rk3228_vop_win_data, 865 .win_size = ARRAY_SIZE(rk3228_vop_win_data), 866 }; 867 868 static const struct vop_modeset rk3328_modeset = { 869 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 870 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 871 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 872 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 873 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 874 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 875 }; 876 877 static const struct vop_output rk3328_output = { 878 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 879 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 880 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 881 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 882 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 883 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 884 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 885 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 886 }; 887 888 static const struct vop_misc rk3328_misc = { 889 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 890 }; 891 892 static const struct vop_common rk3328_common = { 893 .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22), 894 .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4), 895 .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3), 896 .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2), 897 .pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1), 898 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 899 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 900 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 901 .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), 902 }; 903 904 static const struct vop_intr rk3328_vop_intr = { 905 .intrs = rk3368_vop_intrs, 906 .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 907 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 908 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 909 .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0), 910 .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0), 911 .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), 912 }; 913 914 static const struct vop_win_data rk3328_vop_win_data[] = { 915 { .base = 0xd0, .phy = &rk3368_win01_data, 916 .type = DRM_PLANE_TYPE_PRIMARY }, 917 { .base = 0x1d0, .phy = &rk3368_win01_data, 918 .type = DRM_PLANE_TYPE_OVERLAY }, 919 { .base = 0x2d0, .phy = &rk3368_win01_data, 920 .type = DRM_PLANE_TYPE_CURSOR }, 921 }; 922 923 static const struct vop_data rk3328_vop = { 924 .version = VOP_VERSION(3, 8), 925 .feature = VOP_FEATURE_OUTPUT_RGB10, 926 .intr = &rk3328_vop_intr, 927 .common = &rk3328_common, 928 .modeset = &rk3328_modeset, 929 .output = &rk3328_output, 930 .misc = &rk3328_misc, 931 .win = rk3328_vop_win_data, 932 .win_size = ARRAY_SIZE(rk3328_vop_win_data), 933 }; 934 935 static const struct of_device_id vop_driver_dt_match[] = { 936 { .compatible = "rockchip,rk3036-vop", 937 .data = &rk3036_vop }, 938 { .compatible = "rockchip,rk3126-vop", 939 .data = &rk3126_vop }, 940 { .compatible = "rockchip,px30-vop-big", 941 .data = &px30_vop_big }, 942 { .compatible = "rockchip,px30-vop-lit", 943 .data = &px30_vop_lit }, 944 { .compatible = "rockchip,rk3066-vop", 945 .data = &rk3066_vop }, 946 { .compatible = "rockchip,rk3188-vop", 947 .data = &rk3188_vop }, 948 { .compatible = "rockchip,rk3288-vop", 949 .data = &rk3288_vop }, 950 { .compatible = "rockchip,rk3368-vop", 951 .data = &rk3368_vop }, 952 { .compatible = "rockchip,rk3366-vop", 953 .data = &rk3366_vop }, 954 { .compatible = "rockchip,rk3399-vop-big", 955 .data = &rk3399_vop_big }, 956 { .compatible = "rockchip,rk3399-vop-lit", 957 .data = &rk3399_vop_lit }, 958 { .compatible = "rockchip,rk3228-vop", 959 .data = &rk3228_vop }, 960 { .compatible = "rockchip,rk3328-vop", 961 .data = &rk3328_vop }, 962 {}, 963 }; 964 MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 965 966 static int vop_probe(struct platform_device *pdev) 967 { 968 struct device *dev = &pdev->dev; 969 970 if (!dev->of_node) { 971 DRM_DEV_ERROR(dev, "can't find vop devices\n"); 972 return -ENODEV; 973 } 974 975 return component_add(dev, &vop_component_ops); 976 } 977 978 static int vop_remove(struct platform_device *pdev) 979 { 980 component_del(&pdev->dev, &vop_component_ops); 981 982 return 0; 983 } 984 985 struct platform_driver vop_platform_driver = { 986 .probe = vop_probe, 987 .remove = vop_remove, 988 .driver = { 989 .name = "rockchip-vop", 990 .of_match_table = of_match_ptr(vop_driver_dt_match), 991 }, 992 }; 993