1 /*
2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3  * Author:
4  *      Sandy Huang <hjc@rock-chips.com>
5  *      Mark Yao <mark.yao@rock-chips.com>
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #ifndef _ROCKCHIP_LVDS_
18 #define _ROCKCHIP_LVDS_
19 
20 #define RK3288_LVDS_CH0_REG0			0x00
21 #define RK3288_LVDS_CH0_REG0_LVDS_EN		BIT(7)
22 #define RK3288_LVDS_CH0_REG0_TTL_EN		BIT(6)
23 #define RK3288_LVDS_CH0_REG0_LANECK_EN		BIT(5)
24 #define RK3288_LVDS_CH0_REG0_LANE4_EN		BIT(4)
25 #define RK3288_LVDS_CH0_REG0_LANE3_EN		BIT(3)
26 #define RK3288_LVDS_CH0_REG0_LANE2_EN		BIT(2)
27 #define RK3288_LVDS_CH0_REG0_LANE1_EN		BIT(1)
28 #define RK3288_LVDS_CH0_REG0_LANE0_EN		BIT(0)
29 
30 #define RK3288_LVDS_CH0_REG1			0x04
31 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS	BIT(5)
32 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS		BIT(4)
33 #define RK3288_LVDS_CH0_REG1_LANE3_BIAS		BIT(3)
34 #define RK3288_LVDS_CH0_REG1_LANE2_BIAS		BIT(2)
35 #define RK3288_LVDS_CH0_REG1_LANE1_BIAS		BIT(1)
36 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS		BIT(0)
37 
38 #define RK3288_LVDS_CH0_REG2			0x08
39 #define RK3288_LVDS_CH0_REG2_RESERVE_ON		BIT(7)
40 #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE	BIT(6)
41 #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE	BIT(5)
42 #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE	BIT(4)
43 #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE	BIT(3)
44 #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE	BIT(2)
45 #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE	BIT(1)
46 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8		BIT(0)
47 
48 #define RK3288_LVDS_CH0_REG3			0x0c
49 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK	0xff
50 
51 #define RK3288_LVDS_CH0_REG4			0x10
52 #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE	BIT(5)
53 #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE	BIT(4)
54 #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE	BIT(3)
55 #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE	BIT(2)
56 #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE	BIT(1)
57 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE	BIT(0)
58 
59 #define RK3288_LVDS_CH0_REG5			0x14
60 #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA	BIT(5)
61 #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA	BIT(4)
62 #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA	BIT(3)
63 #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA	BIT(2)
64 #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA	BIT(1)
65 #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA	BIT(0)
66 
67 #define RK3288_LVDS_CFG_REGC			0x30
68 #define RK3288_LVDS_CFG_REGC_PLL_ENABLE		0x00
69 #define RK3288_LVDS_CFG_REGC_PLL_DISABLE	0xff
70 
71 #define RK3288_LVDS_CH0_REGD			0x34
72 #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK	0x1f
73 
74 #define RK3288_LVDS_CH0_REG20			0x80
75 #define RK3288_LVDS_CH0_REG20_MSB		0x45
76 #define RK3288_LVDS_CH0_REG20_LSB		0x44
77 
78 #define RK3288_LVDS_CFG_REG21			0x84
79 #define RK3288_LVDS_CFG_REG21_TX_ENABLE		0x92
80 #define RK3288_LVDS_CFG_REG21_TX_DISABLE	0x00
81 #define RK3288_LVDS_CH1_OFFSET                 0x100
82 
83 /* fbdiv value is split over 2 registers, with bit8 in reg2 */
84 #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
85 		(_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
86 #define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
87 		(_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
88 #define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
89 		(_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
90 
91 #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT	BIT(3)
92 
93 #define LVDS_FMT_MASK				(0x07 << 16)
94 #define LVDS_MSB				BIT(3)
95 #define LVDS_DUAL				BIT(4)
96 #define LVDS_FMT_1				BIT(5)
97 #define LVDS_TTL_EN				BIT(6)
98 #define LVDS_START_PHASE_RST_1			BIT(7)
99 #define LVDS_DCLK_INV				BIT(8)
100 #define LVDS_CH0_EN				BIT(11)
101 #define LVDS_CH1_EN				BIT(12)
102 #define LVDS_PWRDN				BIT(15)
103 
104 #define LVDS_24BIT				(0 << 1)
105 #define LVDS_18BIT				(1 << 1)
106 #define LVDS_FORMAT_VESA			(0 << 0)
107 #define LVDS_FORMAT_JEIDA			(1 << 0)
108 
109 #define LVDS_VESA_24				0
110 #define LVDS_JEIDA_24				1
111 #define LVDS_VESA_18				2
112 #define LVDS_JEIDA_18				3
113 
114 #endif /* _ROCKCHIP_LVDS_ */
115