1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #ifndef _ROCKCHIP_DRM_VOP_H 8 #define _ROCKCHIP_DRM_VOP_H 9 10 /* 11 * major: IP major version, used for IP structure 12 * minor: big feature change under same structure 13 */ 14 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 15 #define VOP_MAJOR(version) ((version) >> 8) 16 #define VOP_MINOR(version) ((version) & 0xff) 17 18 #define NUM_YUV2YUV_COEFFICIENTS 12 19 20 #define ROCKCHIP_AFBC_MOD \ 21 DRM_FORMAT_MOD_ARM_AFBC( \ 22 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \ 23 ) 24 25 enum vop_data_format { 26 VOP_FMT_ARGB8888 = 0, 27 VOP_FMT_RGB888, 28 VOP_FMT_RGB565, 29 VOP_FMT_YUV420SP = 4, 30 VOP_FMT_YUV422SP, 31 VOP_FMT_YUV444SP, 32 }; 33 34 struct vop_reg { 35 uint32_t mask; 36 uint16_t offset; 37 uint8_t shift; 38 bool write_mask; 39 bool relaxed; 40 }; 41 42 struct vop_afbc { 43 struct vop_reg enable; 44 struct vop_reg win_sel; 45 struct vop_reg format; 46 struct vop_reg hreg_block_split; 47 struct vop_reg pic_size; 48 struct vop_reg hdr_ptr; 49 struct vop_reg rstn; 50 }; 51 52 struct vop_modeset { 53 struct vop_reg htotal_pw; 54 struct vop_reg hact_st_end; 55 struct vop_reg hpost_st_end; 56 struct vop_reg vtotal_pw; 57 struct vop_reg vact_st_end; 58 struct vop_reg vpost_st_end; 59 }; 60 61 struct vop_output { 62 struct vop_reg pin_pol; 63 struct vop_reg dp_pin_pol; 64 struct vop_reg dp_dclk_pol; 65 struct vop_reg edp_pin_pol; 66 struct vop_reg edp_dclk_pol; 67 struct vop_reg hdmi_pin_pol; 68 struct vop_reg hdmi_dclk_pol; 69 struct vop_reg mipi_pin_pol; 70 struct vop_reg mipi_dclk_pol; 71 struct vop_reg rgb_pin_pol; 72 struct vop_reg rgb_dclk_pol; 73 struct vop_reg dp_en; 74 struct vop_reg edp_en; 75 struct vop_reg hdmi_en; 76 struct vop_reg mipi_en; 77 struct vop_reg mipi_dual_channel_en; 78 struct vop_reg rgb_en; 79 }; 80 81 struct vop_common { 82 struct vop_reg cfg_done; 83 struct vop_reg dsp_blank; 84 struct vop_reg data_blank; 85 struct vop_reg pre_dither_down; 86 struct vop_reg dither_down_sel; 87 struct vop_reg dither_down_mode; 88 struct vop_reg dither_down_en; 89 struct vop_reg dither_up; 90 struct vop_reg dsp_lut_en; 91 struct vop_reg gate_en; 92 struct vop_reg mmu_en; 93 struct vop_reg out_mode; 94 struct vop_reg standby; 95 }; 96 97 struct vop_misc { 98 struct vop_reg global_regdone_en; 99 }; 100 101 struct vop_intr { 102 const int *intrs; 103 uint32_t nintrs; 104 105 struct vop_reg line_flag_num[2]; 106 struct vop_reg enable; 107 struct vop_reg clear; 108 struct vop_reg status; 109 }; 110 111 struct vop_scl_extension { 112 struct vop_reg cbcr_vsd_mode; 113 struct vop_reg cbcr_vsu_mode; 114 struct vop_reg cbcr_hsd_mode; 115 struct vop_reg cbcr_ver_scl_mode; 116 struct vop_reg cbcr_hor_scl_mode; 117 struct vop_reg yrgb_vsd_mode; 118 struct vop_reg yrgb_vsu_mode; 119 struct vop_reg yrgb_hsd_mode; 120 struct vop_reg yrgb_ver_scl_mode; 121 struct vop_reg yrgb_hor_scl_mode; 122 struct vop_reg line_load_mode; 123 struct vop_reg cbcr_axi_gather_num; 124 struct vop_reg yrgb_axi_gather_num; 125 struct vop_reg vsd_cbcr_gt2; 126 struct vop_reg vsd_cbcr_gt4; 127 struct vop_reg vsd_yrgb_gt2; 128 struct vop_reg vsd_yrgb_gt4; 129 struct vop_reg bic_coe_sel; 130 struct vop_reg cbcr_axi_gather_en; 131 struct vop_reg yrgb_axi_gather_en; 132 struct vop_reg lb_mode; 133 }; 134 135 struct vop_scl_regs { 136 const struct vop_scl_extension *ext; 137 138 struct vop_reg scale_yrgb_x; 139 struct vop_reg scale_yrgb_y; 140 struct vop_reg scale_cbcr_x; 141 struct vop_reg scale_cbcr_y; 142 }; 143 144 struct vop_yuv2yuv_phy { 145 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS]; 146 }; 147 148 struct vop_win_phy { 149 const struct vop_scl_regs *scl; 150 const uint32_t *data_formats; 151 uint32_t nformats; 152 const uint64_t *format_modifiers; 153 154 struct vop_reg enable; 155 struct vop_reg gate; 156 struct vop_reg format; 157 struct vop_reg rb_swap; 158 struct vop_reg act_info; 159 struct vop_reg dsp_info; 160 struct vop_reg dsp_st; 161 struct vop_reg yrgb_mst; 162 struct vop_reg uv_mst; 163 struct vop_reg yrgb_vir; 164 struct vop_reg uv_vir; 165 struct vop_reg y_mir_en; 166 struct vop_reg x_mir_en; 167 168 struct vop_reg dst_alpha_ctl; 169 struct vop_reg src_alpha_ctl; 170 struct vop_reg alpha_pre_mul; 171 struct vop_reg alpha_mode; 172 struct vop_reg alpha_en; 173 struct vop_reg channel; 174 }; 175 176 struct vop_win_yuv2yuv_data { 177 uint32_t base; 178 const struct vop_yuv2yuv_phy *phy; 179 struct vop_reg y2r_en; 180 }; 181 182 struct vop_win_data { 183 uint32_t base; 184 const struct vop_win_phy *phy; 185 enum drm_plane_type type; 186 }; 187 188 struct vop_data { 189 uint32_t version; 190 const struct vop_intr *intr; 191 const struct vop_common *common; 192 const struct vop_misc *misc; 193 const struct vop_modeset *modeset; 194 const struct vop_output *output; 195 const struct vop_afbc *afbc; 196 const struct vop_win_yuv2yuv_data *win_yuv2yuv; 197 const struct vop_win_data *win; 198 unsigned int win_size; 199 unsigned int lut_size; 200 201 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) 202 #define VOP_FEATURE_INTERNAL_RGB BIT(1) 203 u64 feature; 204 }; 205 206 /* interrupt define */ 207 #define DSP_HOLD_VALID_INTR (1 << 0) 208 #define FS_INTR (1 << 1) 209 #define LINE_FLAG_INTR (1 << 2) 210 #define BUS_ERROR_INTR (1 << 3) 211 212 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \ 213 LINE_FLAG_INTR | BUS_ERROR_INTR) 214 215 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4) 216 #define FS_INTR_EN(x) ((x) << 5) 217 #define LINE_FLAG_INTR_EN(x) ((x) << 6) 218 #define BUS_ERROR_INTR_EN(x) ((x) << 7) 219 #define DSP_HOLD_VALID_INTR_MASK (1 << 4) 220 #define FS_INTR_MASK (1 << 5) 221 #define LINE_FLAG_INTR_MASK (1 << 6) 222 #define BUS_ERROR_INTR_MASK (1 << 7) 223 224 #define INTR_CLR_SHIFT 8 225 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0)) 226 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1)) 227 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2)) 228 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3)) 229 230 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12) 231 #define DSP_LINE_NUM_MASK (0x1fff << 12) 232 233 /* src alpha ctrl define */ 234 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24) 235 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16) 236 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6) 237 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5) 238 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3) 239 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2) 240 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1) 241 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0) 242 /* dst alpha ctrl define */ 243 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6) 244 245 /* 246 * display output interface supported by rockchip lcdc 247 */ 248 #define ROCKCHIP_OUT_MODE_P888 0 249 #define ROCKCHIP_OUT_MODE_P666 1 250 #define ROCKCHIP_OUT_MODE_P565 2 251 /* for use special outface */ 252 #define ROCKCHIP_OUT_MODE_AAAA 15 253 254 /* output flags */ 255 #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) 256 257 enum alpha_mode { 258 ALPHA_STRAIGHT, 259 ALPHA_INVERSE, 260 }; 261 262 enum global_blend_mode { 263 ALPHA_GLOBAL, 264 ALPHA_PER_PIX, 265 ALPHA_PER_PIX_GLOBAL, 266 }; 267 268 enum alpha_cal_mode { 269 ALPHA_SATURATION, 270 ALPHA_NO_SATURATION, 271 }; 272 273 enum color_mode { 274 ALPHA_SRC_PRE_MUL, 275 ALPHA_SRC_NO_PRE_MUL, 276 }; 277 278 enum factor_mode { 279 ALPHA_ZERO, 280 ALPHA_ONE, 281 ALPHA_SRC, 282 ALPHA_SRC_INVERSE, 283 ALPHA_SRC_GLOBAL, 284 }; 285 286 enum scale_mode { 287 SCALE_NONE = 0x0, 288 SCALE_UP = 0x1, 289 SCALE_DOWN = 0x2 290 }; 291 292 enum lb_mode { 293 LB_YUV_3840X5 = 0x0, 294 LB_YUV_2560X8 = 0x1, 295 LB_RGB_3840X2 = 0x2, 296 LB_RGB_2560X4 = 0x3, 297 LB_RGB_1920X5 = 0x4, 298 LB_RGB_1280X8 = 0x5 299 }; 300 301 enum sacle_up_mode { 302 SCALE_UP_BIL = 0x0, 303 SCALE_UP_BIC = 0x1 304 }; 305 306 enum scale_down_mode { 307 SCALE_DOWN_BIL = 0x0, 308 SCALE_DOWN_AVG = 0x1 309 }; 310 311 enum dither_down_mode { 312 RGB888_TO_RGB565 = 0x0, 313 RGB888_TO_RGB666 = 0x1 314 }; 315 316 enum dither_down_mode_sel { 317 DITHER_DOWN_ALLEGRO = 0x0, 318 DITHER_DOWN_FRC = 0x1 319 }; 320 321 enum vop_pol { 322 HSYNC_POSITIVE = 0, 323 VSYNC_POSITIVE = 1, 324 DEN_NEGATIVE = 2 325 }; 326 327 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 328 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 329 #define SCL_MAX_VSKIPLINES 4 330 #define MIN_SCL_FT_AFTER_VSKIP 1 331 332 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 333 { 334 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 335 } 336 337 static inline uint16_t scl_cal_scale2(int src, int dst) 338 { 339 return ((src - 1) << 12) / (dst - 1); 340 } 341 342 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 343 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 344 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 345 346 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 347 int vskiplines) 348 { 349 int act_height; 350 351 act_height = DIV_ROUND_UP(src_h, vskiplines); 352 353 if (act_height == dst_h) 354 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines; 355 356 return GET_SCL_FT_BILI_DN(act_height, dst_h); 357 } 358 359 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 360 { 361 if (src < dst) 362 return SCALE_UP; 363 else if (src > dst) 364 return SCALE_DOWN; 365 366 return SCALE_NONE; 367 } 368 369 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 370 { 371 uint32_t vskiplines; 372 373 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 374 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 375 break; 376 377 return vskiplines; 378 } 379 380 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 381 { 382 int lb_mode; 383 384 if (is_yuv) { 385 if (width > 1280) 386 lb_mode = LB_YUV_3840X5; 387 else 388 lb_mode = LB_YUV_2560X8; 389 } else { 390 if (width > 2560) 391 lb_mode = LB_RGB_3840X2; 392 else if (width > 1920) 393 lb_mode = LB_RGB_2560X4; 394 else 395 lb_mode = LB_RGB_1920X5; 396 } 397 398 return lb_mode; 399 } 400 401 extern const struct component_ops vop_component_ops; 402 #endif /* _ROCKCHIP_DRM_VOP_H */ 403