1 /*
2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3  * Author:Mark Yao <mark.yao@rock-chips.com>
4  *
5  * This software is licensed under the terms of the GNU General Public
6  * License version 2, as published by the Free Software Foundation, and
7  * may be copied, distributed, and modified under those terms.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #ifndef _ROCKCHIP_DRM_VOP_H
16 #define _ROCKCHIP_DRM_VOP_H
17 
18 enum vop_data_format {
19 	VOP_FMT_ARGB8888 = 0,
20 	VOP_FMT_RGB888,
21 	VOP_FMT_RGB565,
22 	VOP_FMT_YUV420SP = 4,
23 	VOP_FMT_YUV422SP,
24 	VOP_FMT_YUV444SP,
25 };
26 
27 struct vop_reg_data {
28 	uint32_t offset;
29 	uint32_t value;
30 };
31 
32 struct vop_reg {
33 	uint32_t offset;
34 	uint32_t shift;
35 	uint32_t mask;
36 	bool write_mask;
37 };
38 
39 struct vop_ctrl {
40 	struct vop_reg standby;
41 	struct vop_reg data_blank;
42 	struct vop_reg gate_en;
43 	struct vop_reg mmu_en;
44 	struct vop_reg rgb_en;
45 	struct vop_reg edp_en;
46 	struct vop_reg hdmi_en;
47 	struct vop_reg mipi_en;
48 	struct vop_reg dp_en;
49 	struct vop_reg out_mode;
50 	struct vop_reg dither_down;
51 	struct vop_reg dither_up;
52 	struct vop_reg pin_pol;
53 	struct vop_reg rgb_pin_pol;
54 	struct vop_reg hdmi_pin_pol;
55 	struct vop_reg edp_pin_pol;
56 	struct vop_reg mipi_pin_pol;
57 	struct vop_reg dp_pin_pol;
58 
59 	struct vop_reg htotal_pw;
60 	struct vop_reg hact_st_end;
61 	struct vop_reg vtotal_pw;
62 	struct vop_reg vact_st_end;
63 	struct vop_reg hpost_st_end;
64 	struct vop_reg vpost_st_end;
65 
66 	struct vop_reg line_flag_num[2];
67 
68 	struct vop_reg cfg_done;
69 };
70 
71 struct vop_intr {
72 	const int *intrs;
73 	uint32_t nintrs;
74 	struct vop_reg enable;
75 	struct vop_reg clear;
76 	struct vop_reg status;
77 };
78 
79 struct vop_scl_extension {
80 	struct vop_reg cbcr_vsd_mode;
81 	struct vop_reg cbcr_vsu_mode;
82 	struct vop_reg cbcr_hsd_mode;
83 	struct vop_reg cbcr_ver_scl_mode;
84 	struct vop_reg cbcr_hor_scl_mode;
85 	struct vop_reg yrgb_vsd_mode;
86 	struct vop_reg yrgb_vsu_mode;
87 	struct vop_reg yrgb_hsd_mode;
88 	struct vop_reg yrgb_ver_scl_mode;
89 	struct vop_reg yrgb_hor_scl_mode;
90 	struct vop_reg line_load_mode;
91 	struct vop_reg cbcr_axi_gather_num;
92 	struct vop_reg yrgb_axi_gather_num;
93 	struct vop_reg vsd_cbcr_gt2;
94 	struct vop_reg vsd_cbcr_gt4;
95 	struct vop_reg vsd_yrgb_gt2;
96 	struct vop_reg vsd_yrgb_gt4;
97 	struct vop_reg bic_coe_sel;
98 	struct vop_reg cbcr_axi_gather_en;
99 	struct vop_reg yrgb_axi_gather_en;
100 	struct vop_reg lb_mode;
101 };
102 
103 struct vop_scl_regs {
104 	const struct vop_scl_extension *ext;
105 
106 	struct vop_reg scale_yrgb_x;
107 	struct vop_reg scale_yrgb_y;
108 	struct vop_reg scale_cbcr_x;
109 	struct vop_reg scale_cbcr_y;
110 };
111 
112 struct vop_win_phy {
113 	const struct vop_scl_regs *scl;
114 	const uint32_t *data_formats;
115 	uint32_t nformats;
116 
117 	struct vop_reg enable;
118 	struct vop_reg format;
119 	struct vop_reg rb_swap;
120 	struct vop_reg act_info;
121 	struct vop_reg dsp_info;
122 	struct vop_reg dsp_st;
123 	struct vop_reg yrgb_mst;
124 	struct vop_reg uv_mst;
125 	struct vop_reg yrgb_vir;
126 	struct vop_reg uv_vir;
127 
128 	struct vop_reg dst_alpha_ctl;
129 	struct vop_reg src_alpha_ctl;
130 };
131 
132 struct vop_win_data {
133 	uint32_t base;
134 	const struct vop_win_phy *phy;
135 	enum drm_plane_type type;
136 };
137 
138 struct vop_data {
139 	const struct vop_reg_data *init_table;
140 	unsigned int table_size;
141 	const struct vop_ctrl *ctrl;
142 	const struct vop_intr *intr;
143 	const struct vop_win_data *win;
144 	unsigned int win_size;
145 
146 #define VOP_FEATURE_OUTPUT_RGB10	BIT(0)
147 	u64 feature;
148 };
149 
150 /* interrupt define */
151 #define DSP_HOLD_VALID_INTR		(1 << 0)
152 #define FS_INTR				(1 << 1)
153 #define LINE_FLAG_INTR			(1 << 2)
154 #define BUS_ERROR_INTR			(1 << 3)
155 
156 #define INTR_MASK			(DSP_HOLD_VALID_INTR | FS_INTR | \
157 					 LINE_FLAG_INTR | BUS_ERROR_INTR)
158 
159 #define DSP_HOLD_VALID_INTR_EN(x)	((x) << 4)
160 #define FS_INTR_EN(x)			((x) << 5)
161 #define LINE_FLAG_INTR_EN(x)		((x) << 6)
162 #define BUS_ERROR_INTR_EN(x)		((x) << 7)
163 #define DSP_HOLD_VALID_INTR_MASK	(1 << 4)
164 #define FS_INTR_MASK			(1 << 5)
165 #define LINE_FLAG_INTR_MASK		(1 << 6)
166 #define BUS_ERROR_INTR_MASK		(1 << 7)
167 
168 #define INTR_CLR_SHIFT			8
169 #define DSP_HOLD_VALID_INTR_CLR		(1 << (INTR_CLR_SHIFT + 0))
170 #define FS_INTR_CLR			(1 << (INTR_CLR_SHIFT + 1))
171 #define LINE_FLAG_INTR_CLR		(1 << (INTR_CLR_SHIFT + 2))
172 #define BUS_ERROR_INTR_CLR		(1 << (INTR_CLR_SHIFT + 3))
173 
174 #define DSP_LINE_NUM(x)			(((x) & 0x1fff) << 12)
175 #define DSP_LINE_NUM_MASK		(0x1fff << 12)
176 
177 /* src alpha ctrl define */
178 #define SRC_FADING_VALUE(x)		(((x) & 0xff) << 24)
179 #define SRC_GLOBAL_ALPHA(x)		(((x) & 0xff) << 16)
180 #define SRC_FACTOR_M0(x)		(((x) & 0x7) << 6)
181 #define SRC_ALPHA_CAL_M0(x)		(((x) & 0x1) << 5)
182 #define SRC_BLEND_M0(x)			(((x) & 0x3) << 3)
183 #define SRC_ALPHA_M0(x)			(((x) & 0x1) << 2)
184 #define SRC_COLOR_M0(x)			(((x) & 0x1) << 1)
185 #define SRC_ALPHA_EN(x)			(((x) & 0x1) << 0)
186 /* dst alpha ctrl define */
187 #define DST_FACTOR_M0(x)		(((x) & 0x7) << 6)
188 
189 /*
190  * display output interface supported by rockchip lcdc
191  */
192 #define ROCKCHIP_OUT_MODE_P888	0
193 #define ROCKCHIP_OUT_MODE_P666	1
194 #define ROCKCHIP_OUT_MODE_P565	2
195 /* for use special outface */
196 #define ROCKCHIP_OUT_MODE_AAAA	15
197 
198 enum alpha_mode {
199 	ALPHA_STRAIGHT,
200 	ALPHA_INVERSE,
201 };
202 
203 enum global_blend_mode {
204 	ALPHA_GLOBAL,
205 	ALPHA_PER_PIX,
206 	ALPHA_PER_PIX_GLOBAL,
207 };
208 
209 enum alpha_cal_mode {
210 	ALPHA_SATURATION,
211 	ALPHA_NO_SATURATION,
212 };
213 
214 enum color_mode {
215 	ALPHA_SRC_PRE_MUL,
216 	ALPHA_SRC_NO_PRE_MUL,
217 };
218 
219 enum factor_mode {
220 	ALPHA_ZERO,
221 	ALPHA_ONE,
222 	ALPHA_SRC,
223 	ALPHA_SRC_INVERSE,
224 	ALPHA_SRC_GLOBAL,
225 };
226 
227 enum scale_mode {
228 	SCALE_NONE = 0x0,
229 	SCALE_UP   = 0x1,
230 	SCALE_DOWN = 0x2
231 };
232 
233 enum lb_mode {
234 	LB_YUV_3840X5 = 0x0,
235 	LB_YUV_2560X8 = 0x1,
236 	LB_RGB_3840X2 = 0x2,
237 	LB_RGB_2560X4 = 0x3,
238 	LB_RGB_1920X5 = 0x4,
239 	LB_RGB_1280X8 = 0x5
240 };
241 
242 enum sacle_up_mode {
243 	SCALE_UP_BIL = 0x0,
244 	SCALE_UP_BIC = 0x1
245 };
246 
247 enum scale_down_mode {
248 	SCALE_DOWN_BIL = 0x0,
249 	SCALE_DOWN_AVG = 0x1
250 };
251 
252 enum vop_pol {
253 	HSYNC_POSITIVE = 0,
254 	VSYNC_POSITIVE = 1,
255 	DEN_NEGATIVE   = 2,
256 	DCLK_INVERT    = 3
257 };
258 
259 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
260 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT	12
261 #define SCL_MAX_VSKIPLINES		4
262 #define MIN_SCL_FT_AFTER_VSKIP		1
263 
264 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
265 {
266 	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
267 }
268 
269 static inline uint16_t scl_cal_scale2(int src, int dst)
270 {
271 	return ((src - 1) << 12) / (dst - 1);
272 }
273 
274 #define GET_SCL_FT_BILI_DN(src, dst)	scl_cal_scale(src, dst, 12)
275 #define GET_SCL_FT_BILI_UP(src, dst)	scl_cal_scale(src, dst, 16)
276 #define GET_SCL_FT_BIC(src, dst)	scl_cal_scale(src, dst, 16)
277 
278 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
279 					     int vskiplines)
280 {
281 	int act_height;
282 
283 	act_height = (src_h + vskiplines - 1) / vskiplines;
284 
285 	return GET_SCL_FT_BILI_DN(act_height, dst_h);
286 }
287 
288 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
289 {
290 	if (src < dst)
291 		return SCALE_UP;
292 	else if (src > dst)
293 		return SCALE_DOWN;
294 
295 	return SCALE_NONE;
296 }
297 
298 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
299 {
300 	uint32_t vskiplines;
301 
302 	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
303 		if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
304 			break;
305 
306 	return vskiplines;
307 }
308 
309 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
310 {
311 	int lb_mode;
312 
313 	if (width > 2560)
314 		lb_mode = LB_RGB_3840X2;
315 	else if (width > 1920)
316 		lb_mode = LB_RGB_2560X4;
317 	else if (!is_yuv)
318 		lb_mode = LB_RGB_1920X5;
319 	else if (width > 1280)
320 		lb_mode = LB_YUV_3840X5;
321 	else
322 		lb_mode = LB_YUV_2560X8;
323 
324 	return lb_mode;
325 }
326 
327 extern const struct component_ops vop_component_ops;
328 #endif /* _ROCKCHIP_DRM_VOP_H */
329