1 /*
2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3  * Author:Mark Yao <mark.yao@rock-chips.com>
4  *
5  * This software is licensed under the terms of the GNU General Public
6  * License version 2, as published by the Free Software Foundation, and
7  * may be copied, distributed, and modified under those terms.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #ifndef _ROCKCHIP_DRM_VOP_H
16 #define _ROCKCHIP_DRM_VOP_H
17 
18 /*
19  * major: IP major version, used for IP structure
20  * minor: big feature change under same structure
21  */
22 #define VOP_VERSION(major, minor)	((major) << 8 | (minor))
23 #define VOP_MAJOR(version)		((version) >> 8)
24 #define VOP_MINOR(version)		((version) & 0xff)
25 
26 #define NUM_YUV2YUV_COEFFICIENTS 12
27 
28 enum vop_data_format {
29 	VOP_FMT_ARGB8888 = 0,
30 	VOP_FMT_RGB888,
31 	VOP_FMT_RGB565,
32 	VOP_FMT_YUV420SP = 4,
33 	VOP_FMT_YUV422SP,
34 	VOP_FMT_YUV444SP,
35 };
36 
37 struct vop_reg {
38 	uint32_t mask;
39 	uint16_t offset;
40 	uint8_t shift;
41 	bool write_mask;
42 	bool relaxed;
43 };
44 
45 struct vop_modeset {
46 	struct vop_reg htotal_pw;
47 	struct vop_reg hact_st_end;
48 	struct vop_reg hpost_st_end;
49 	struct vop_reg vtotal_pw;
50 	struct vop_reg vact_st_end;
51 	struct vop_reg vpost_st_end;
52 };
53 
54 struct vop_output {
55 	struct vop_reg pin_pol;
56 	struct vop_reg dp_pin_pol;
57 	struct vop_reg edp_pin_pol;
58 	struct vop_reg hdmi_pin_pol;
59 	struct vop_reg mipi_pin_pol;
60 	struct vop_reg rgb_pin_pol;
61 	struct vop_reg dp_en;
62 	struct vop_reg edp_en;
63 	struct vop_reg hdmi_en;
64 	struct vop_reg mipi_en;
65 	struct vop_reg mipi_dual_channel_en;
66 	struct vop_reg rgb_en;
67 };
68 
69 struct vop_common {
70 	struct vop_reg cfg_done;
71 	struct vop_reg dsp_blank;
72 	struct vop_reg data_blank;
73 	struct vop_reg pre_dither_down;
74 	struct vop_reg dither_down_sel;
75 	struct vop_reg dither_down_mode;
76 	struct vop_reg dither_down_en;
77 	struct vop_reg dither_up;
78 	struct vop_reg gate_en;
79 	struct vop_reg mmu_en;
80 	struct vop_reg out_mode;
81 	struct vop_reg standby;
82 };
83 
84 struct vop_misc {
85 	struct vop_reg global_regdone_en;
86 };
87 
88 struct vop_intr {
89 	const int *intrs;
90 	uint32_t nintrs;
91 
92 	struct vop_reg line_flag_num[2];
93 	struct vop_reg enable;
94 	struct vop_reg clear;
95 	struct vop_reg status;
96 };
97 
98 struct vop_scl_extension {
99 	struct vop_reg cbcr_vsd_mode;
100 	struct vop_reg cbcr_vsu_mode;
101 	struct vop_reg cbcr_hsd_mode;
102 	struct vop_reg cbcr_ver_scl_mode;
103 	struct vop_reg cbcr_hor_scl_mode;
104 	struct vop_reg yrgb_vsd_mode;
105 	struct vop_reg yrgb_vsu_mode;
106 	struct vop_reg yrgb_hsd_mode;
107 	struct vop_reg yrgb_ver_scl_mode;
108 	struct vop_reg yrgb_hor_scl_mode;
109 	struct vop_reg line_load_mode;
110 	struct vop_reg cbcr_axi_gather_num;
111 	struct vop_reg yrgb_axi_gather_num;
112 	struct vop_reg vsd_cbcr_gt2;
113 	struct vop_reg vsd_cbcr_gt4;
114 	struct vop_reg vsd_yrgb_gt2;
115 	struct vop_reg vsd_yrgb_gt4;
116 	struct vop_reg bic_coe_sel;
117 	struct vop_reg cbcr_axi_gather_en;
118 	struct vop_reg yrgb_axi_gather_en;
119 	struct vop_reg lb_mode;
120 };
121 
122 struct vop_scl_regs {
123 	const struct vop_scl_extension *ext;
124 
125 	struct vop_reg scale_yrgb_x;
126 	struct vop_reg scale_yrgb_y;
127 	struct vop_reg scale_cbcr_x;
128 	struct vop_reg scale_cbcr_y;
129 };
130 
131 struct vop_yuv2yuv_phy {
132 	struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
133 };
134 
135 struct vop_win_phy {
136 	const struct vop_scl_regs *scl;
137 	const uint32_t *data_formats;
138 	uint32_t nformats;
139 
140 	struct vop_reg enable;
141 	struct vop_reg gate;
142 	struct vop_reg format;
143 	struct vop_reg rb_swap;
144 	struct vop_reg act_info;
145 	struct vop_reg dsp_info;
146 	struct vop_reg dsp_st;
147 	struct vop_reg yrgb_mst;
148 	struct vop_reg uv_mst;
149 	struct vop_reg yrgb_vir;
150 	struct vop_reg uv_vir;
151 	struct vop_reg y_mir_en;
152 	struct vop_reg x_mir_en;
153 
154 	struct vop_reg dst_alpha_ctl;
155 	struct vop_reg src_alpha_ctl;
156 	struct vop_reg channel;
157 };
158 
159 struct vop_win_yuv2yuv_data {
160 	uint32_t base;
161 	const struct vop_yuv2yuv_phy *phy;
162 	struct vop_reg y2r_en;
163 };
164 
165 struct vop_win_data {
166 	uint32_t base;
167 	const struct vop_win_phy *phy;
168 	enum drm_plane_type type;
169 };
170 
171 struct vop_data {
172 	uint32_t version;
173 	const struct vop_intr *intr;
174 	const struct vop_common *common;
175 	const struct vop_misc *misc;
176 	const struct vop_modeset *modeset;
177 	const struct vop_output *output;
178 	const struct vop_win_yuv2yuv_data *win_yuv2yuv;
179 	const struct vop_win_data *win;
180 	unsigned int win_size;
181 
182 #define VOP_FEATURE_OUTPUT_RGB10	BIT(0)
183 #define VOP_FEATURE_INTERNAL_RGB	BIT(1)
184 	u64 feature;
185 };
186 
187 /* interrupt define */
188 #define DSP_HOLD_VALID_INTR		(1 << 0)
189 #define FS_INTR				(1 << 1)
190 #define LINE_FLAG_INTR			(1 << 2)
191 #define BUS_ERROR_INTR			(1 << 3)
192 
193 #define INTR_MASK			(DSP_HOLD_VALID_INTR | FS_INTR | \
194 					 LINE_FLAG_INTR | BUS_ERROR_INTR)
195 
196 #define DSP_HOLD_VALID_INTR_EN(x)	((x) << 4)
197 #define FS_INTR_EN(x)			((x) << 5)
198 #define LINE_FLAG_INTR_EN(x)		((x) << 6)
199 #define BUS_ERROR_INTR_EN(x)		((x) << 7)
200 #define DSP_HOLD_VALID_INTR_MASK	(1 << 4)
201 #define FS_INTR_MASK			(1 << 5)
202 #define LINE_FLAG_INTR_MASK		(1 << 6)
203 #define BUS_ERROR_INTR_MASK		(1 << 7)
204 
205 #define INTR_CLR_SHIFT			8
206 #define DSP_HOLD_VALID_INTR_CLR		(1 << (INTR_CLR_SHIFT + 0))
207 #define FS_INTR_CLR			(1 << (INTR_CLR_SHIFT + 1))
208 #define LINE_FLAG_INTR_CLR		(1 << (INTR_CLR_SHIFT + 2))
209 #define BUS_ERROR_INTR_CLR		(1 << (INTR_CLR_SHIFT + 3))
210 
211 #define DSP_LINE_NUM(x)			(((x) & 0x1fff) << 12)
212 #define DSP_LINE_NUM_MASK		(0x1fff << 12)
213 
214 /* src alpha ctrl define */
215 #define SRC_FADING_VALUE(x)		(((x) & 0xff) << 24)
216 #define SRC_GLOBAL_ALPHA(x)		(((x) & 0xff) << 16)
217 #define SRC_FACTOR_M0(x)		(((x) & 0x7) << 6)
218 #define SRC_ALPHA_CAL_M0(x)		(((x) & 0x1) << 5)
219 #define SRC_BLEND_M0(x)			(((x) & 0x3) << 3)
220 #define SRC_ALPHA_M0(x)			(((x) & 0x1) << 2)
221 #define SRC_COLOR_M0(x)			(((x) & 0x1) << 1)
222 #define SRC_ALPHA_EN(x)			(((x) & 0x1) << 0)
223 /* dst alpha ctrl define */
224 #define DST_FACTOR_M0(x)		(((x) & 0x7) << 6)
225 
226 /*
227  * display output interface supported by rockchip lcdc
228  */
229 #define ROCKCHIP_OUT_MODE_P888	0
230 #define ROCKCHIP_OUT_MODE_P666	1
231 #define ROCKCHIP_OUT_MODE_P565	2
232 /* for use special outface */
233 #define ROCKCHIP_OUT_MODE_AAAA	15
234 
235 /* output flags */
236 #define ROCKCHIP_OUTPUT_DSI_DUAL	BIT(0)
237 
238 enum alpha_mode {
239 	ALPHA_STRAIGHT,
240 	ALPHA_INVERSE,
241 };
242 
243 enum global_blend_mode {
244 	ALPHA_GLOBAL,
245 	ALPHA_PER_PIX,
246 	ALPHA_PER_PIX_GLOBAL,
247 };
248 
249 enum alpha_cal_mode {
250 	ALPHA_SATURATION,
251 	ALPHA_NO_SATURATION,
252 };
253 
254 enum color_mode {
255 	ALPHA_SRC_PRE_MUL,
256 	ALPHA_SRC_NO_PRE_MUL,
257 };
258 
259 enum factor_mode {
260 	ALPHA_ZERO,
261 	ALPHA_ONE,
262 	ALPHA_SRC,
263 	ALPHA_SRC_INVERSE,
264 	ALPHA_SRC_GLOBAL,
265 };
266 
267 enum scale_mode {
268 	SCALE_NONE = 0x0,
269 	SCALE_UP   = 0x1,
270 	SCALE_DOWN = 0x2
271 };
272 
273 enum lb_mode {
274 	LB_YUV_3840X5 = 0x0,
275 	LB_YUV_2560X8 = 0x1,
276 	LB_RGB_3840X2 = 0x2,
277 	LB_RGB_2560X4 = 0x3,
278 	LB_RGB_1920X5 = 0x4,
279 	LB_RGB_1280X8 = 0x5
280 };
281 
282 enum sacle_up_mode {
283 	SCALE_UP_BIL = 0x0,
284 	SCALE_UP_BIC = 0x1
285 };
286 
287 enum scale_down_mode {
288 	SCALE_DOWN_BIL = 0x0,
289 	SCALE_DOWN_AVG = 0x1
290 };
291 
292 enum dither_down_mode {
293 	RGB888_TO_RGB565 = 0x0,
294 	RGB888_TO_RGB666 = 0x1
295 };
296 
297 enum dither_down_mode_sel {
298 	DITHER_DOWN_ALLEGRO = 0x0,
299 	DITHER_DOWN_FRC = 0x1
300 };
301 
302 enum vop_pol {
303 	HSYNC_POSITIVE = 0,
304 	VSYNC_POSITIVE = 1,
305 	DEN_NEGATIVE   = 2,
306 	DCLK_INVERT    = 3
307 };
308 
309 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
310 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT	12
311 #define SCL_MAX_VSKIPLINES		4
312 #define MIN_SCL_FT_AFTER_VSKIP		1
313 
314 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
315 {
316 	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
317 }
318 
319 static inline uint16_t scl_cal_scale2(int src, int dst)
320 {
321 	return ((src - 1) << 12) / (dst - 1);
322 }
323 
324 #define GET_SCL_FT_BILI_DN(src, dst)	scl_cal_scale(src, dst, 12)
325 #define GET_SCL_FT_BILI_UP(src, dst)	scl_cal_scale(src, dst, 16)
326 #define GET_SCL_FT_BIC(src, dst)	scl_cal_scale(src, dst, 16)
327 
328 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
329 					     int vskiplines)
330 {
331 	int act_height;
332 
333 	act_height = (src_h + vskiplines - 1) / vskiplines;
334 
335 	if (act_height == dst_h)
336 		return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
337 
338 	return GET_SCL_FT_BILI_DN(act_height, dst_h);
339 }
340 
341 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
342 {
343 	if (src < dst)
344 		return SCALE_UP;
345 	else if (src > dst)
346 		return SCALE_DOWN;
347 
348 	return SCALE_NONE;
349 }
350 
351 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
352 {
353 	uint32_t vskiplines;
354 
355 	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
356 		if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
357 			break;
358 
359 	return vskiplines;
360 }
361 
362 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
363 {
364 	int lb_mode;
365 
366 	if (is_yuv) {
367 		if (width > 1280)
368 			lb_mode = LB_YUV_3840X5;
369 		else
370 			lb_mode = LB_YUV_2560X8;
371 	} else {
372 		if (width > 2560)
373 			lb_mode = LB_RGB_3840X2;
374 		else if (width > 1920)
375 			lb_mode = LB_RGB_2560X4;
376 		else
377 			lb_mode = LB_RGB_1920X5;
378 	}
379 
380 	return lb_mode;
381 }
382 
383 extern const struct component_ops vop_component_ops;
384 #endif /* _ROCKCHIP_DRM_VOP_H */
385