1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_plane_helper.h> 22 #ifdef CONFIG_DRM_ANALOGIX_DP 23 #include <drm/bridge/analogix_dp.h> 24 #endif 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/iopoll.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/component.h> 35 36 #include <linux/reset.h> 37 #include <linux/delay.h> 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_psr.h" 43 #include "rockchip_drm_vop.h" 44 45 #define VOP_WIN_SET(x, win, name, v) \ 46 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET(x, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 49 #define VOP_SCL_SET_EXT(x, win, name, v) \ 50 vop_reg_set(vop, &win->phy->scl->ext->name, \ 51 win->base, ~0, v, #name) 52 53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 54 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 55 56 #define VOP_REG_SET(vop, group, name, v) \ 57 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58 59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60 do { \ 61 int i, reg = 0, mask = 0; \ 62 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63 if (vop->data->intr->intrs[i] & type) { \ 64 reg |= (v) << i; \ 65 mask |= 1 << i; \ 66 } \ 67 } \ 68 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69 } while (0) 70 #define VOP_INTR_GET_TYPE(vop, name, type) \ 71 vop_get_intr_type(vop, &vop->data->intr->name, type) 72 73 #define VOP_WIN_GET(x, win, name) \ 74 vop_read_reg(x, win->offset, win->phy->name) 75 76 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 77 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 78 79 #define to_vop(x) container_of(x, struct vop, crtc) 80 #define to_vop_win(x) container_of(x, struct vop_win, base) 81 82 enum vop_pending { 83 VOP_PENDING_FB_UNREF, 84 }; 85 86 struct vop_win { 87 struct drm_plane base; 88 const struct vop_win_data *data; 89 struct vop *vop; 90 }; 91 92 struct vop { 93 struct drm_crtc crtc; 94 struct device *dev; 95 struct drm_device *drm_dev; 96 bool is_enabled; 97 98 /* mutex vsync_ work */ 99 struct mutex vsync_mutex; 100 bool vsync_work_pending; 101 struct completion dsp_hold_completion; 102 103 /* protected by dev->event_lock */ 104 struct drm_pending_vblank_event *event; 105 106 struct drm_flip_work fb_unref_work; 107 unsigned long pending; 108 109 struct completion line_flag_completion; 110 111 const struct vop_data *data; 112 113 uint32_t *regsbak; 114 void __iomem *regs; 115 116 /* physical map length of vop register */ 117 uint32_t len; 118 119 /* one time only one process allowed to config the register */ 120 spinlock_t reg_lock; 121 /* lock vop irq reg */ 122 spinlock_t irq_lock; 123 124 unsigned int irq; 125 126 /* vop AHP clk */ 127 struct clk *hclk; 128 /* vop dclk */ 129 struct clk *dclk; 130 /* vop share memory frequency */ 131 struct clk *aclk; 132 133 /* vop dclk reset */ 134 struct reset_control *dclk_rst; 135 136 struct vop_win win[]; 137 }; 138 139 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 140 { 141 writel(v, vop->regs + offset); 142 vop->regsbak[offset >> 2] = v; 143 } 144 145 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 146 { 147 return readl(vop->regs + offset); 148 } 149 150 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 151 const struct vop_reg *reg) 152 { 153 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 154 } 155 156 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 157 uint32_t _offset, uint32_t _mask, uint32_t v, 158 const char *reg_name) 159 { 160 int offset, mask, shift; 161 162 if (!reg || !reg->mask) { 163 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 164 return; 165 } 166 167 offset = reg->offset + _offset; 168 mask = reg->mask & _mask; 169 shift = reg->shift; 170 171 if (reg->write_mask) { 172 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 173 } else { 174 uint32_t cached_val = vop->regsbak[offset >> 2]; 175 176 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 177 vop->regsbak[offset >> 2] = v; 178 } 179 180 if (reg->relaxed) 181 writel_relaxed(v, vop->regs + offset); 182 else 183 writel(v, vop->regs + offset); 184 } 185 186 static inline uint32_t vop_get_intr_type(struct vop *vop, 187 const struct vop_reg *reg, int type) 188 { 189 uint32_t i, ret = 0; 190 uint32_t regs = vop_read_reg(vop, 0, reg); 191 192 for (i = 0; i < vop->data->intr->nintrs; i++) { 193 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 194 ret |= vop->data->intr->intrs[i]; 195 } 196 197 return ret; 198 } 199 200 static inline void vop_cfg_done(struct vop *vop) 201 { 202 VOP_REG_SET(vop, common, cfg_done, 1); 203 } 204 205 static bool has_rb_swapped(uint32_t format) 206 { 207 switch (format) { 208 case DRM_FORMAT_XBGR8888: 209 case DRM_FORMAT_ABGR8888: 210 case DRM_FORMAT_BGR888: 211 case DRM_FORMAT_BGR565: 212 return true; 213 default: 214 return false; 215 } 216 } 217 218 static enum vop_data_format vop_convert_format(uint32_t format) 219 { 220 switch (format) { 221 case DRM_FORMAT_XRGB8888: 222 case DRM_FORMAT_ARGB8888: 223 case DRM_FORMAT_XBGR8888: 224 case DRM_FORMAT_ABGR8888: 225 return VOP_FMT_ARGB8888; 226 case DRM_FORMAT_RGB888: 227 case DRM_FORMAT_BGR888: 228 return VOP_FMT_RGB888; 229 case DRM_FORMAT_RGB565: 230 case DRM_FORMAT_BGR565: 231 return VOP_FMT_RGB565; 232 case DRM_FORMAT_NV12: 233 return VOP_FMT_YUV420SP; 234 case DRM_FORMAT_NV16: 235 return VOP_FMT_YUV422SP; 236 case DRM_FORMAT_NV24: 237 return VOP_FMT_YUV444SP; 238 default: 239 DRM_ERROR("unsupported format[%08x]\n", format); 240 return -EINVAL; 241 } 242 } 243 244 static bool is_yuv_support(uint32_t format) 245 { 246 switch (format) { 247 case DRM_FORMAT_NV12: 248 case DRM_FORMAT_NV16: 249 case DRM_FORMAT_NV24: 250 return true; 251 default: 252 return false; 253 } 254 } 255 256 static bool is_alpha_support(uint32_t format) 257 { 258 switch (format) { 259 case DRM_FORMAT_ARGB8888: 260 case DRM_FORMAT_ABGR8888: 261 return true; 262 default: 263 return false; 264 } 265 } 266 267 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 268 uint32_t dst, bool is_horizontal, 269 int vsu_mode, int *vskiplines) 270 { 271 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 272 273 if (is_horizontal) { 274 if (mode == SCALE_UP) 275 val = GET_SCL_FT_BIC(src, dst); 276 else if (mode == SCALE_DOWN) 277 val = GET_SCL_FT_BILI_DN(src, dst); 278 } else { 279 if (mode == SCALE_UP) { 280 if (vsu_mode == SCALE_UP_BIL) 281 val = GET_SCL_FT_BILI_UP(src, dst); 282 else 283 val = GET_SCL_FT_BIC(src, dst); 284 } else if (mode == SCALE_DOWN) { 285 if (vskiplines) { 286 *vskiplines = scl_get_vskiplines(src, dst); 287 val = scl_get_bili_dn_vskip(src, dst, 288 *vskiplines); 289 } else { 290 val = GET_SCL_FT_BILI_DN(src, dst); 291 } 292 } 293 } 294 295 return val; 296 } 297 298 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 299 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 300 uint32_t dst_h, uint32_t pixel_format) 301 { 302 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 303 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 304 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 305 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 306 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 307 bool is_yuv = is_yuv_support(pixel_format); 308 uint16_t cbcr_src_w = src_w / hsub; 309 uint16_t cbcr_src_h = src_h / vsub; 310 uint16_t vsu_mode; 311 uint16_t lb_mode; 312 uint32_t val; 313 int vskiplines = 0; 314 315 if (dst_w > 3840) { 316 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 317 return; 318 } 319 320 if (!win->phy->scl->ext) { 321 VOP_SCL_SET(vop, win, scale_yrgb_x, 322 scl_cal_scale2(src_w, dst_w)); 323 VOP_SCL_SET(vop, win, scale_yrgb_y, 324 scl_cal_scale2(src_h, dst_h)); 325 if (is_yuv) { 326 VOP_SCL_SET(vop, win, scale_cbcr_x, 327 scl_cal_scale2(cbcr_src_w, dst_w)); 328 VOP_SCL_SET(vop, win, scale_cbcr_y, 329 scl_cal_scale2(cbcr_src_h, dst_h)); 330 } 331 return; 332 } 333 334 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 335 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 336 337 if (is_yuv) { 338 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 339 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 340 if (cbcr_hor_scl_mode == SCALE_DOWN) 341 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 342 else 343 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 344 } else { 345 if (yrgb_hor_scl_mode == SCALE_DOWN) 346 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 347 else 348 lb_mode = scl_vop_cal_lb_mode(src_w, false); 349 } 350 351 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 352 if (lb_mode == LB_RGB_3840X2) { 353 if (yrgb_ver_scl_mode != SCALE_NONE) { 354 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 355 return; 356 } 357 if (cbcr_ver_scl_mode != SCALE_NONE) { 358 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 359 return; 360 } 361 vsu_mode = SCALE_UP_BIL; 362 } else if (lb_mode == LB_RGB_2560X4) { 363 vsu_mode = SCALE_UP_BIL; 364 } else { 365 vsu_mode = SCALE_UP_BIC; 366 } 367 368 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 369 true, 0, NULL); 370 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 371 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 372 false, vsu_mode, &vskiplines); 373 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 374 375 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 376 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 377 378 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 379 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 380 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 381 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 382 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 383 if (is_yuv) { 384 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 385 dst_w, true, 0, NULL); 386 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 387 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 388 dst_h, false, vsu_mode, &vskiplines); 389 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 390 391 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 392 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 393 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 394 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 395 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 396 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 397 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 398 } 399 } 400 401 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 402 { 403 unsigned long flags; 404 405 if (WARN_ON(!vop->is_enabled)) 406 return; 407 408 spin_lock_irqsave(&vop->irq_lock, flags); 409 410 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 411 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 412 413 spin_unlock_irqrestore(&vop->irq_lock, flags); 414 } 415 416 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 417 { 418 unsigned long flags; 419 420 if (WARN_ON(!vop->is_enabled)) 421 return; 422 423 spin_lock_irqsave(&vop->irq_lock, flags); 424 425 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 426 427 spin_unlock_irqrestore(&vop->irq_lock, flags); 428 } 429 430 /* 431 * (1) each frame starts at the start of the Vsync pulse which is signaled by 432 * the "FRAME_SYNC" interrupt. 433 * (2) the active data region of each frame ends at dsp_vact_end 434 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 435 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 436 * 437 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 438 * Interrupts 439 * LINE_FLAG -------------------------------+ 440 * FRAME_SYNC ----+ | 441 * | | 442 * v v 443 * | Vsync | Vbp | Vactive | Vfp | 444 * ^ ^ ^ ^ 445 * | | | | 446 * | | | | 447 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 448 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 449 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 450 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 451 */ 452 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 453 { 454 uint32_t line_flag_irq; 455 unsigned long flags; 456 457 spin_lock_irqsave(&vop->irq_lock, flags); 458 459 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 460 461 spin_unlock_irqrestore(&vop->irq_lock, flags); 462 463 return !!line_flag_irq; 464 } 465 466 static void vop_line_flag_irq_enable(struct vop *vop) 467 { 468 unsigned long flags; 469 470 if (WARN_ON(!vop->is_enabled)) 471 return; 472 473 spin_lock_irqsave(&vop->irq_lock, flags); 474 475 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 476 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 477 478 spin_unlock_irqrestore(&vop->irq_lock, flags); 479 } 480 481 static void vop_line_flag_irq_disable(struct vop *vop) 482 { 483 unsigned long flags; 484 485 if (WARN_ON(!vop->is_enabled)) 486 return; 487 488 spin_lock_irqsave(&vop->irq_lock, flags); 489 490 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 491 492 spin_unlock_irqrestore(&vop->irq_lock, flags); 493 } 494 495 static int vop_enable(struct drm_crtc *crtc) 496 { 497 struct vop *vop = to_vop(crtc); 498 int ret, i; 499 500 ret = pm_runtime_get_sync(vop->dev); 501 if (ret < 0) { 502 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 503 return ret; 504 } 505 506 ret = clk_enable(vop->hclk); 507 if (WARN_ON(ret < 0)) 508 goto err_put_pm_runtime; 509 510 ret = clk_enable(vop->dclk); 511 if (WARN_ON(ret < 0)) 512 goto err_disable_hclk; 513 514 ret = clk_enable(vop->aclk); 515 if (WARN_ON(ret < 0)) 516 goto err_disable_dclk; 517 518 /* 519 * Slave iommu shares power, irq and clock with vop. It was associated 520 * automatically with this master device via common driver code. 521 * Now that we have enabled the clock we attach it to the shared drm 522 * mapping. 523 */ 524 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 525 if (ret) { 526 DRM_DEV_ERROR(vop->dev, 527 "failed to attach dma mapping, %d\n", ret); 528 goto err_disable_aclk; 529 } 530 531 memcpy(vop->regs, vop->regsbak, vop->len); 532 /* 533 * We need to make sure that all windows are disabled before we 534 * enable the crtc. Otherwise we might try to scan from a destroyed 535 * buffer later. 536 */ 537 for (i = 0; i < vop->data->win_size; i++) { 538 struct vop_win *vop_win = &vop->win[i]; 539 const struct vop_win_data *win = vop_win->data; 540 541 spin_lock(&vop->reg_lock); 542 VOP_WIN_SET(vop, win, enable, 0); 543 spin_unlock(&vop->reg_lock); 544 } 545 546 vop_cfg_done(vop); 547 548 /* 549 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 550 */ 551 vop->is_enabled = true; 552 553 spin_lock(&vop->reg_lock); 554 555 VOP_REG_SET(vop, common, standby, 1); 556 557 spin_unlock(&vop->reg_lock); 558 559 enable_irq(vop->irq); 560 561 drm_crtc_vblank_on(crtc); 562 563 return 0; 564 565 err_disable_aclk: 566 clk_disable(vop->aclk); 567 err_disable_dclk: 568 clk_disable(vop->dclk); 569 err_disable_hclk: 570 clk_disable(vop->hclk); 571 err_put_pm_runtime: 572 pm_runtime_put_sync(vop->dev); 573 return ret; 574 } 575 576 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 577 struct drm_crtc_state *old_state) 578 { 579 struct vop *vop = to_vop(crtc); 580 581 WARN_ON(vop->event); 582 583 rockchip_drm_psr_deactivate(&vop->crtc); 584 585 drm_crtc_vblank_off(crtc); 586 587 /* 588 * Vop standby will take effect at end of current frame, 589 * if dsp hold valid irq happen, it means standby complete. 590 * 591 * we must wait standby complete when we want to disable aclk, 592 * if not, memory bus maybe dead. 593 */ 594 reinit_completion(&vop->dsp_hold_completion); 595 vop_dsp_hold_valid_irq_enable(vop); 596 597 spin_lock(&vop->reg_lock); 598 599 VOP_REG_SET(vop, common, standby, 1); 600 601 spin_unlock(&vop->reg_lock); 602 603 wait_for_completion(&vop->dsp_hold_completion); 604 605 vop_dsp_hold_valid_irq_disable(vop); 606 607 disable_irq(vop->irq); 608 609 vop->is_enabled = false; 610 611 /* 612 * vop standby complete, so iommu detach is safe. 613 */ 614 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 615 616 clk_disable(vop->dclk); 617 clk_disable(vop->aclk); 618 clk_disable(vop->hclk); 619 pm_runtime_put(vop->dev); 620 621 if (crtc->state->event && !crtc->state->active) { 622 spin_lock_irq(&crtc->dev->event_lock); 623 drm_crtc_send_vblank_event(crtc, crtc->state->event); 624 spin_unlock_irq(&crtc->dev->event_lock); 625 626 crtc->state->event = NULL; 627 } 628 } 629 630 static void vop_plane_destroy(struct drm_plane *plane) 631 { 632 drm_plane_cleanup(plane); 633 } 634 635 static int vop_plane_atomic_check(struct drm_plane *plane, 636 struct drm_plane_state *state) 637 { 638 struct drm_crtc *crtc = state->crtc; 639 struct drm_crtc_state *crtc_state; 640 struct drm_framebuffer *fb = state->fb; 641 struct vop_win *vop_win = to_vop_win(plane); 642 const struct vop_win_data *win = vop_win->data; 643 int ret; 644 struct drm_rect clip; 645 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 646 DRM_PLANE_HELPER_NO_SCALING; 647 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 648 DRM_PLANE_HELPER_NO_SCALING; 649 650 if (!crtc || !fb) 651 return 0; 652 653 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 654 if (WARN_ON(!crtc_state)) 655 return -EINVAL; 656 657 clip.x1 = 0; 658 clip.y1 = 0; 659 clip.x2 = crtc_state->adjusted_mode.hdisplay; 660 clip.y2 = crtc_state->adjusted_mode.vdisplay; 661 662 ret = drm_plane_helper_check_state(state, &clip, 663 min_scale, max_scale, 664 true, true); 665 if (ret) 666 return ret; 667 668 if (!state->visible) 669 return 0; 670 671 ret = vop_convert_format(fb->format->format); 672 if (ret < 0) 673 return ret; 674 675 /* 676 * Src.x1 can be odd when do clip, but yuv plane start point 677 * need align with 2 pixel. 678 */ 679 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) { 680 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 681 return -EINVAL; 682 } 683 684 return 0; 685 } 686 687 static void vop_plane_atomic_disable(struct drm_plane *plane, 688 struct drm_plane_state *old_state) 689 { 690 struct vop_win *vop_win = to_vop_win(plane); 691 const struct vop_win_data *win = vop_win->data; 692 struct vop *vop = to_vop(old_state->crtc); 693 694 if (!old_state->crtc) 695 return; 696 697 spin_lock(&vop->reg_lock); 698 699 VOP_WIN_SET(vop, win, enable, 0); 700 701 spin_unlock(&vop->reg_lock); 702 } 703 704 static void vop_plane_atomic_update(struct drm_plane *plane, 705 struct drm_plane_state *old_state) 706 { 707 struct drm_plane_state *state = plane->state; 708 struct drm_crtc *crtc = state->crtc; 709 struct vop_win *vop_win = to_vop_win(plane); 710 const struct vop_win_data *win = vop_win->data; 711 struct vop *vop = to_vop(state->crtc); 712 struct drm_framebuffer *fb = state->fb; 713 unsigned int actual_w, actual_h; 714 unsigned int dsp_stx, dsp_sty; 715 uint32_t act_info, dsp_info, dsp_st; 716 struct drm_rect *src = &state->src; 717 struct drm_rect *dest = &state->dst; 718 struct drm_gem_object *obj, *uv_obj; 719 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 720 unsigned long offset; 721 dma_addr_t dma_addr; 722 uint32_t val; 723 bool rb_swap; 724 int format; 725 726 /* 727 * can't update plane when vop is disabled. 728 */ 729 if (WARN_ON(!crtc)) 730 return; 731 732 if (WARN_ON(!vop->is_enabled)) 733 return; 734 735 if (!state->visible) { 736 vop_plane_atomic_disable(plane, old_state); 737 return; 738 } 739 740 obj = rockchip_fb_get_gem_obj(fb, 0); 741 rk_obj = to_rockchip_obj(obj); 742 743 actual_w = drm_rect_width(src) >> 16; 744 actual_h = drm_rect_height(src) >> 16; 745 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 746 747 dsp_info = (drm_rect_height(dest) - 1) << 16; 748 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 749 750 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 751 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 752 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 753 754 offset = (src->x1 >> 16) * fb->format->cpp[0]; 755 offset += (src->y1 >> 16) * fb->pitches[0]; 756 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 757 758 format = vop_convert_format(fb->format->format); 759 760 spin_lock(&vop->reg_lock); 761 762 VOP_WIN_SET(vop, win, format, format); 763 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 764 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 765 if (is_yuv_support(fb->format->format)) { 766 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 767 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 768 int bpp = fb->format->cpp[1]; 769 770 uv_obj = rockchip_fb_get_gem_obj(fb, 1); 771 rk_uv_obj = to_rockchip_obj(uv_obj); 772 773 offset = (src->x1 >> 16) * bpp / hsub; 774 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 775 776 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 777 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 778 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 779 } 780 781 if (win->phy->scl) 782 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 783 drm_rect_width(dest), drm_rect_height(dest), 784 fb->format->format); 785 786 VOP_WIN_SET(vop, win, act_info, act_info); 787 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 788 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 789 790 rb_swap = has_rb_swapped(fb->format->format); 791 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 792 793 if (is_alpha_support(fb->format->format)) { 794 VOP_WIN_SET(vop, win, dst_alpha_ctl, 795 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 796 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 797 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 798 SRC_BLEND_M0(ALPHA_PER_PIX) | 799 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 800 SRC_FACTOR_M0(ALPHA_ONE); 801 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 802 } else { 803 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 804 } 805 806 VOP_WIN_SET(vop, win, enable, 1); 807 spin_unlock(&vop->reg_lock); 808 } 809 810 static const struct drm_plane_helper_funcs plane_helper_funcs = { 811 .atomic_check = vop_plane_atomic_check, 812 .atomic_update = vop_plane_atomic_update, 813 .atomic_disable = vop_plane_atomic_disable, 814 }; 815 816 static const struct drm_plane_funcs vop_plane_funcs = { 817 .update_plane = drm_atomic_helper_update_plane, 818 .disable_plane = drm_atomic_helper_disable_plane, 819 .destroy = vop_plane_destroy, 820 .reset = drm_atomic_helper_plane_reset, 821 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 822 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 823 }; 824 825 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 826 { 827 struct vop *vop = to_vop(crtc); 828 unsigned long flags; 829 830 if (WARN_ON(!vop->is_enabled)) 831 return -EPERM; 832 833 spin_lock_irqsave(&vop->irq_lock, flags); 834 835 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 836 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 837 838 spin_unlock_irqrestore(&vop->irq_lock, flags); 839 840 return 0; 841 } 842 843 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 844 { 845 struct vop *vop = to_vop(crtc); 846 unsigned long flags; 847 848 if (WARN_ON(!vop->is_enabled)) 849 return; 850 851 spin_lock_irqsave(&vop->irq_lock, flags); 852 853 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 854 855 spin_unlock_irqrestore(&vop->irq_lock, flags); 856 } 857 858 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 859 const struct drm_display_mode *mode, 860 struct drm_display_mode *adjusted_mode) 861 { 862 struct vop *vop = to_vop(crtc); 863 864 adjusted_mode->clock = 865 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 866 867 return true; 868 } 869 870 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 871 struct drm_crtc_state *old_state) 872 { 873 struct vop *vop = to_vop(crtc); 874 const struct vop_data *vop_data = vop->data; 875 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 876 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 877 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 878 u16 hdisplay = adjusted_mode->hdisplay; 879 u16 htotal = adjusted_mode->htotal; 880 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 881 u16 hact_end = hact_st + hdisplay; 882 u16 vdisplay = adjusted_mode->vdisplay; 883 u16 vtotal = adjusted_mode->vtotal; 884 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 885 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 886 u16 vact_end = vact_st + vdisplay; 887 uint32_t pin_pol, val; 888 int ret; 889 890 WARN_ON(vop->event); 891 892 ret = vop_enable(crtc); 893 if (ret) { 894 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 895 return; 896 } 897 898 pin_pol = BIT(DCLK_INVERT); 899 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 900 BIT(HSYNC_POSITIVE) : 0; 901 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 902 BIT(VSYNC_POSITIVE) : 0; 903 VOP_REG_SET(vop, output, pin_pol, pin_pol); 904 905 switch (s->output_type) { 906 case DRM_MODE_CONNECTOR_LVDS: 907 VOP_REG_SET(vop, output, rgb_en, 1); 908 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 909 break; 910 case DRM_MODE_CONNECTOR_eDP: 911 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 912 VOP_REG_SET(vop, output, edp_en, 1); 913 break; 914 case DRM_MODE_CONNECTOR_HDMIA: 915 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 916 VOP_REG_SET(vop, output, hdmi_en, 1); 917 break; 918 case DRM_MODE_CONNECTOR_DSI: 919 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 920 VOP_REG_SET(vop, output, mipi_en, 1); 921 break; 922 case DRM_MODE_CONNECTOR_DisplayPort: 923 pin_pol &= ~BIT(DCLK_INVERT); 924 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 925 VOP_REG_SET(vop, output, dp_en, 1); 926 break; 927 default: 928 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 929 s->output_type); 930 } 931 932 /* 933 * if vop is not support RGB10 output, need force RGB10 to RGB888. 934 */ 935 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 936 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 937 s->output_mode = ROCKCHIP_OUT_MODE_P888; 938 VOP_REG_SET(vop, common, out_mode, s->output_mode); 939 940 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 941 val = hact_st << 16; 942 val |= hact_end; 943 VOP_REG_SET(vop, modeset, hact_st_end, val); 944 VOP_REG_SET(vop, modeset, hpost_st_end, val); 945 946 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 947 val = vact_st << 16; 948 val |= vact_end; 949 VOP_REG_SET(vop, modeset, vact_st_end, val); 950 VOP_REG_SET(vop, modeset, vpost_st_end, val); 951 952 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 953 954 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 955 956 VOP_REG_SET(vop, common, standby, 0); 957 958 rockchip_drm_psr_activate(&vop->crtc); 959 } 960 961 static bool vop_fs_irq_is_pending(struct vop *vop) 962 { 963 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 964 } 965 966 static void vop_wait_for_irq_handler(struct vop *vop) 967 { 968 bool pending; 969 int ret; 970 971 /* 972 * Spin until frame start interrupt status bit goes low, which means 973 * that interrupt handler was invoked and cleared it. The timeout of 974 * 10 msecs is really too long, but it is just a safety measure if 975 * something goes really wrong. The wait will only happen in the very 976 * unlikely case of a vblank happening exactly at the same time and 977 * shouldn't exceed microseconds range. 978 */ 979 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 980 !pending, 0, 10 * 1000); 981 if (ret) 982 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 983 984 synchronize_irq(vop->irq); 985 } 986 987 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 988 struct drm_crtc_state *old_crtc_state) 989 { 990 struct drm_atomic_state *old_state = old_crtc_state->state; 991 struct drm_plane_state *old_plane_state, *new_plane_state; 992 struct vop *vop = to_vop(crtc); 993 struct drm_plane *plane; 994 int i; 995 996 if (WARN_ON(!vop->is_enabled)) 997 return; 998 999 spin_lock(&vop->reg_lock); 1000 1001 vop_cfg_done(vop); 1002 1003 spin_unlock(&vop->reg_lock); 1004 1005 /* 1006 * There is a (rather unlikely) possiblity that a vblank interrupt 1007 * fired before we set the cfg_done bit. To avoid spuriously 1008 * signalling flip completion we need to wait for it to finish. 1009 */ 1010 vop_wait_for_irq_handler(vop); 1011 1012 spin_lock_irq(&crtc->dev->event_lock); 1013 if (crtc->state->event) { 1014 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1015 WARN_ON(vop->event); 1016 1017 vop->event = crtc->state->event; 1018 crtc->state->event = NULL; 1019 } 1020 spin_unlock_irq(&crtc->dev->event_lock); 1021 1022 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1023 new_plane_state, i) { 1024 if (!old_plane_state->fb) 1025 continue; 1026 1027 if (old_plane_state->fb == new_plane_state->fb) 1028 continue; 1029 1030 drm_framebuffer_get(old_plane_state->fb); 1031 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1032 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1033 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1034 } 1035 } 1036 1037 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1038 struct drm_crtc_state *old_crtc_state) 1039 { 1040 rockchip_drm_psr_flush(crtc); 1041 } 1042 1043 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1044 .mode_fixup = vop_crtc_mode_fixup, 1045 .atomic_flush = vop_crtc_atomic_flush, 1046 .atomic_begin = vop_crtc_atomic_begin, 1047 .atomic_enable = vop_crtc_atomic_enable, 1048 .atomic_disable = vop_crtc_atomic_disable, 1049 }; 1050 1051 static void vop_crtc_destroy(struct drm_crtc *crtc) 1052 { 1053 drm_crtc_cleanup(crtc); 1054 } 1055 1056 static void vop_crtc_reset(struct drm_crtc *crtc) 1057 { 1058 if (crtc->state) 1059 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1060 kfree(crtc->state); 1061 1062 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1063 if (crtc->state) 1064 crtc->state->crtc = crtc; 1065 } 1066 1067 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1068 { 1069 struct rockchip_crtc_state *rockchip_state; 1070 1071 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1072 if (!rockchip_state) 1073 return NULL; 1074 1075 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1076 return &rockchip_state->base; 1077 } 1078 1079 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1080 struct drm_crtc_state *state) 1081 { 1082 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1083 1084 __drm_atomic_helper_crtc_destroy_state(&s->base); 1085 kfree(s); 1086 } 1087 1088 #ifdef CONFIG_DRM_ANALOGIX_DP 1089 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1090 { 1091 struct drm_connector *connector; 1092 struct drm_connector_list_iter conn_iter; 1093 1094 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1095 drm_for_each_connector_iter(connector, &conn_iter) { 1096 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1097 drm_connector_list_iter_end(&conn_iter); 1098 return connector; 1099 } 1100 } 1101 drm_connector_list_iter_end(&conn_iter); 1102 1103 return NULL; 1104 } 1105 1106 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1107 const char *source_name, size_t *values_cnt) 1108 { 1109 struct vop *vop = to_vop(crtc); 1110 struct drm_connector *connector; 1111 int ret; 1112 1113 connector = vop_get_edp_connector(vop); 1114 if (!connector) 1115 return -EINVAL; 1116 1117 *values_cnt = 3; 1118 1119 if (source_name && strcmp(source_name, "auto") == 0) 1120 ret = analogix_dp_start_crc(connector); 1121 else if (!source_name) 1122 ret = analogix_dp_stop_crc(connector); 1123 else 1124 ret = -EINVAL; 1125 1126 return ret; 1127 } 1128 #else 1129 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1130 const char *source_name, size_t *values_cnt) 1131 { 1132 return -ENODEV; 1133 } 1134 #endif 1135 1136 static const struct drm_crtc_funcs vop_crtc_funcs = { 1137 .set_config = drm_atomic_helper_set_config, 1138 .page_flip = drm_atomic_helper_page_flip, 1139 .destroy = vop_crtc_destroy, 1140 .reset = vop_crtc_reset, 1141 .atomic_duplicate_state = vop_crtc_duplicate_state, 1142 .atomic_destroy_state = vop_crtc_destroy_state, 1143 .enable_vblank = vop_crtc_enable_vblank, 1144 .disable_vblank = vop_crtc_disable_vblank, 1145 .set_crc_source = vop_crtc_set_crc_source, 1146 }; 1147 1148 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1149 { 1150 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1151 struct drm_framebuffer *fb = val; 1152 1153 drm_crtc_vblank_put(&vop->crtc); 1154 drm_framebuffer_put(fb); 1155 } 1156 1157 static void vop_handle_vblank(struct vop *vop) 1158 { 1159 struct drm_device *drm = vop->drm_dev; 1160 struct drm_crtc *crtc = &vop->crtc; 1161 unsigned long flags; 1162 1163 spin_lock_irqsave(&drm->event_lock, flags); 1164 if (vop->event) { 1165 drm_crtc_send_vblank_event(crtc, vop->event); 1166 drm_crtc_vblank_put(crtc); 1167 vop->event = NULL; 1168 } 1169 spin_unlock_irqrestore(&drm->event_lock, flags); 1170 1171 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1172 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1173 } 1174 1175 static irqreturn_t vop_isr(int irq, void *data) 1176 { 1177 struct vop *vop = data; 1178 struct drm_crtc *crtc = &vop->crtc; 1179 uint32_t active_irqs; 1180 unsigned long flags; 1181 int ret = IRQ_NONE; 1182 1183 /* 1184 * interrupt register has interrupt status, enable and clear bits, we 1185 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1186 */ 1187 spin_lock_irqsave(&vop->irq_lock, flags); 1188 1189 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1190 /* Clear all active interrupt sources */ 1191 if (active_irqs) 1192 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1193 1194 spin_unlock_irqrestore(&vop->irq_lock, flags); 1195 1196 /* This is expected for vop iommu irqs, since the irq is shared */ 1197 if (!active_irqs) 1198 return IRQ_NONE; 1199 1200 if (active_irqs & DSP_HOLD_VALID_INTR) { 1201 complete(&vop->dsp_hold_completion); 1202 active_irqs &= ~DSP_HOLD_VALID_INTR; 1203 ret = IRQ_HANDLED; 1204 } 1205 1206 if (active_irqs & LINE_FLAG_INTR) { 1207 complete(&vop->line_flag_completion); 1208 active_irqs &= ~LINE_FLAG_INTR; 1209 ret = IRQ_HANDLED; 1210 } 1211 1212 if (active_irqs & FS_INTR) { 1213 drm_crtc_handle_vblank(crtc); 1214 vop_handle_vblank(vop); 1215 active_irqs &= ~FS_INTR; 1216 ret = IRQ_HANDLED; 1217 } 1218 1219 /* Unhandled irqs are spurious. */ 1220 if (active_irqs) 1221 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1222 active_irqs); 1223 1224 return ret; 1225 } 1226 1227 static int vop_create_crtc(struct vop *vop) 1228 { 1229 const struct vop_data *vop_data = vop->data; 1230 struct device *dev = vop->dev; 1231 struct drm_device *drm_dev = vop->drm_dev; 1232 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1233 struct drm_crtc *crtc = &vop->crtc; 1234 struct device_node *port; 1235 int ret; 1236 int i; 1237 1238 /* 1239 * Create drm_plane for primary and cursor planes first, since we need 1240 * to pass them to drm_crtc_init_with_planes, which sets the 1241 * "possible_crtcs" to the newly initialized crtc. 1242 */ 1243 for (i = 0; i < vop_data->win_size; i++) { 1244 struct vop_win *vop_win = &vop->win[i]; 1245 const struct vop_win_data *win_data = vop_win->data; 1246 1247 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1248 win_data->type != DRM_PLANE_TYPE_CURSOR) 1249 continue; 1250 1251 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1252 0, &vop_plane_funcs, 1253 win_data->phy->data_formats, 1254 win_data->phy->nformats, 1255 NULL, win_data->type, NULL); 1256 if (ret) { 1257 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1258 ret); 1259 goto err_cleanup_planes; 1260 } 1261 1262 plane = &vop_win->base; 1263 drm_plane_helper_add(plane, &plane_helper_funcs); 1264 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1265 primary = plane; 1266 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1267 cursor = plane; 1268 } 1269 1270 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1271 &vop_crtc_funcs, NULL); 1272 if (ret) 1273 goto err_cleanup_planes; 1274 1275 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1276 1277 /* 1278 * Create drm_planes for overlay windows with possible_crtcs restricted 1279 * to the newly created crtc. 1280 */ 1281 for (i = 0; i < vop_data->win_size; i++) { 1282 struct vop_win *vop_win = &vop->win[i]; 1283 const struct vop_win_data *win_data = vop_win->data; 1284 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1285 1286 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1287 continue; 1288 1289 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1290 possible_crtcs, 1291 &vop_plane_funcs, 1292 win_data->phy->data_formats, 1293 win_data->phy->nformats, 1294 NULL, win_data->type, NULL); 1295 if (ret) { 1296 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1297 ret); 1298 goto err_cleanup_crtc; 1299 } 1300 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1301 } 1302 1303 port = of_get_child_by_name(dev->of_node, "port"); 1304 if (!port) { 1305 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1306 dev->of_node); 1307 ret = -ENOENT; 1308 goto err_cleanup_crtc; 1309 } 1310 1311 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1312 vop_fb_unref_worker); 1313 1314 init_completion(&vop->dsp_hold_completion); 1315 init_completion(&vop->line_flag_completion); 1316 crtc->port = port; 1317 1318 return 0; 1319 1320 err_cleanup_crtc: 1321 drm_crtc_cleanup(crtc); 1322 err_cleanup_planes: 1323 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1324 head) 1325 drm_plane_cleanup(plane); 1326 return ret; 1327 } 1328 1329 static void vop_destroy_crtc(struct vop *vop) 1330 { 1331 struct drm_crtc *crtc = &vop->crtc; 1332 struct drm_device *drm_dev = vop->drm_dev; 1333 struct drm_plane *plane, *tmp; 1334 1335 of_node_put(crtc->port); 1336 1337 /* 1338 * We need to cleanup the planes now. Why? 1339 * 1340 * The planes are "&vop->win[i].base". That means the memory is 1341 * all part of the big "struct vop" chunk of memory. That memory 1342 * was devm allocated and associated with this component. We need to 1343 * free it ourselves before vop_unbind() finishes. 1344 */ 1345 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1346 head) 1347 vop_plane_destroy(plane); 1348 1349 /* 1350 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1351 * references the CRTC. 1352 */ 1353 drm_crtc_cleanup(crtc); 1354 drm_flip_work_cleanup(&vop->fb_unref_work); 1355 } 1356 1357 static int vop_initial(struct vop *vop) 1358 { 1359 const struct vop_data *vop_data = vop->data; 1360 struct reset_control *ahb_rst; 1361 int i, ret; 1362 1363 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1364 if (IS_ERR(vop->hclk)) { 1365 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1366 return PTR_ERR(vop->hclk); 1367 } 1368 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1369 if (IS_ERR(vop->aclk)) { 1370 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1371 return PTR_ERR(vop->aclk); 1372 } 1373 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1374 if (IS_ERR(vop->dclk)) { 1375 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1376 return PTR_ERR(vop->dclk); 1377 } 1378 1379 ret = pm_runtime_get_sync(vop->dev); 1380 if (ret < 0) { 1381 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1382 return ret; 1383 } 1384 1385 ret = clk_prepare(vop->dclk); 1386 if (ret < 0) { 1387 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1388 goto err_put_pm_runtime; 1389 } 1390 1391 /* Enable both the hclk and aclk to setup the vop */ 1392 ret = clk_prepare_enable(vop->hclk); 1393 if (ret < 0) { 1394 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1395 goto err_unprepare_dclk; 1396 } 1397 1398 ret = clk_prepare_enable(vop->aclk); 1399 if (ret < 0) { 1400 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1401 goto err_disable_hclk; 1402 } 1403 1404 /* 1405 * do hclk_reset, reset all vop registers. 1406 */ 1407 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1408 if (IS_ERR(ahb_rst)) { 1409 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1410 ret = PTR_ERR(ahb_rst); 1411 goto err_disable_aclk; 1412 } 1413 reset_control_assert(ahb_rst); 1414 usleep_range(10, 20); 1415 reset_control_deassert(ahb_rst); 1416 1417 memcpy(vop->regsbak, vop->regs, vop->len); 1418 1419 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1420 VOP_REG_SET(vop, common, dsp_blank, 0); 1421 1422 for (i = 0; i < vop_data->win_size; i++) { 1423 const struct vop_win_data *win = &vop_data->win[i]; 1424 int channel = i * 2 + 1; 1425 1426 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1427 VOP_WIN_SET(vop, win, enable, 0); 1428 VOP_WIN_SET(vop, win, gate, 1); 1429 } 1430 1431 vop_cfg_done(vop); 1432 1433 /* 1434 * do dclk_reset, let all config take affect. 1435 */ 1436 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1437 if (IS_ERR(vop->dclk_rst)) { 1438 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1439 ret = PTR_ERR(vop->dclk_rst); 1440 goto err_disable_aclk; 1441 } 1442 reset_control_assert(vop->dclk_rst); 1443 usleep_range(10, 20); 1444 reset_control_deassert(vop->dclk_rst); 1445 1446 clk_disable(vop->hclk); 1447 clk_disable(vop->aclk); 1448 1449 vop->is_enabled = false; 1450 1451 pm_runtime_put_sync(vop->dev); 1452 1453 return 0; 1454 1455 err_disable_aclk: 1456 clk_disable_unprepare(vop->aclk); 1457 err_disable_hclk: 1458 clk_disable_unprepare(vop->hclk); 1459 err_unprepare_dclk: 1460 clk_unprepare(vop->dclk); 1461 err_put_pm_runtime: 1462 pm_runtime_put_sync(vop->dev); 1463 return ret; 1464 } 1465 1466 /* 1467 * Initialize the vop->win array elements. 1468 */ 1469 static void vop_win_init(struct vop *vop) 1470 { 1471 const struct vop_data *vop_data = vop->data; 1472 unsigned int i; 1473 1474 for (i = 0; i < vop_data->win_size; i++) { 1475 struct vop_win *vop_win = &vop->win[i]; 1476 const struct vop_win_data *win_data = &vop_data->win[i]; 1477 1478 vop_win->data = win_data; 1479 vop_win->vop = vop; 1480 } 1481 } 1482 1483 /** 1484 * rockchip_drm_wait_vact_end 1485 * @crtc: CRTC to enable line flag 1486 * @mstimeout: millisecond for timeout 1487 * 1488 * Wait for vact_end line flag irq or timeout. 1489 * 1490 * Returns: 1491 * Zero on success, negative errno on failure. 1492 */ 1493 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1494 { 1495 struct vop *vop = to_vop(crtc); 1496 unsigned long jiffies_left; 1497 1498 if (!crtc || !vop->is_enabled) 1499 return -ENODEV; 1500 1501 if (mstimeout <= 0) 1502 return -EINVAL; 1503 1504 if (vop_line_flag_irq_is_enabled(vop)) 1505 return -EBUSY; 1506 1507 reinit_completion(&vop->line_flag_completion); 1508 vop_line_flag_irq_enable(vop); 1509 1510 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1511 msecs_to_jiffies(mstimeout)); 1512 vop_line_flag_irq_disable(vop); 1513 1514 if (jiffies_left == 0) { 1515 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1516 return -ETIMEDOUT; 1517 } 1518 1519 return 0; 1520 } 1521 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1522 1523 static int vop_bind(struct device *dev, struct device *master, void *data) 1524 { 1525 struct platform_device *pdev = to_platform_device(dev); 1526 const struct vop_data *vop_data; 1527 struct drm_device *drm_dev = data; 1528 struct vop *vop; 1529 struct resource *res; 1530 size_t alloc_size; 1531 int ret, irq; 1532 1533 vop_data = of_device_get_match_data(dev); 1534 if (!vop_data) 1535 return -ENODEV; 1536 1537 /* Allocate vop struct and its vop_win array */ 1538 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1539 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1540 if (!vop) 1541 return -ENOMEM; 1542 1543 vop->dev = dev; 1544 vop->data = vop_data; 1545 vop->drm_dev = drm_dev; 1546 dev_set_drvdata(dev, vop); 1547 1548 vop_win_init(vop); 1549 1550 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1551 vop->len = resource_size(res); 1552 vop->regs = devm_ioremap_resource(dev, res); 1553 if (IS_ERR(vop->regs)) 1554 return PTR_ERR(vop->regs); 1555 1556 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1557 if (!vop->regsbak) 1558 return -ENOMEM; 1559 1560 irq = platform_get_irq(pdev, 0); 1561 if (irq < 0) { 1562 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1563 return irq; 1564 } 1565 vop->irq = (unsigned int)irq; 1566 1567 spin_lock_init(&vop->reg_lock); 1568 spin_lock_init(&vop->irq_lock); 1569 1570 mutex_init(&vop->vsync_mutex); 1571 1572 ret = devm_request_irq(dev, vop->irq, vop_isr, 1573 IRQF_SHARED, dev_name(dev), vop); 1574 if (ret) 1575 return ret; 1576 1577 /* IRQ is initially disabled; it gets enabled in power_on */ 1578 disable_irq(vop->irq); 1579 1580 ret = vop_create_crtc(vop); 1581 if (ret) 1582 goto err_enable_irq; 1583 1584 pm_runtime_enable(&pdev->dev); 1585 1586 ret = vop_initial(vop); 1587 if (ret < 0) { 1588 DRM_DEV_ERROR(&pdev->dev, 1589 "cannot initial vop dev - err %d\n", ret); 1590 goto err_disable_pm_runtime; 1591 } 1592 1593 return 0; 1594 1595 err_disable_pm_runtime: 1596 pm_runtime_disable(&pdev->dev); 1597 vop_destroy_crtc(vop); 1598 err_enable_irq: 1599 enable_irq(vop->irq); /* To balance out the disable_irq above */ 1600 return ret; 1601 } 1602 1603 static void vop_unbind(struct device *dev, struct device *master, void *data) 1604 { 1605 struct vop *vop = dev_get_drvdata(dev); 1606 1607 pm_runtime_disable(dev); 1608 vop_destroy_crtc(vop); 1609 1610 clk_unprepare(vop->aclk); 1611 clk_unprepare(vop->hclk); 1612 clk_unprepare(vop->dclk); 1613 } 1614 1615 const struct component_ops vop_component_ops = { 1616 .bind = vop_bind, 1617 .unbind = vop_unbind, 1618 }; 1619 EXPORT_SYMBOL_GPL(vop_component_ops); 1620