1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_plane_helper.h> 22 #ifdef CONFIG_DRM_ANALOGIX_DP 23 #include <drm/bridge/analogix_dp.h> 24 #endif 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/iopoll.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/component.h> 35 36 #include <linux/reset.h> 37 #include <linux/delay.h> 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_psr.h" 43 #include "rockchip_drm_vop.h" 44 45 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ 46 vop_mask_write(x, off, mask, shift, v, write_mask, true) 47 48 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ 49 vop_mask_write(x, off, mask, shift, v, write_mask, false) 50 51 #define REG_SET(x, base, reg, v, mode) \ 52 __REG_SET_##mode(x, base + reg.offset, \ 53 reg.mask, reg.shift, v, reg.write_mask) 54 #define REG_SET_MASK(x, base, reg, mask, v, mode) \ 55 __REG_SET_##mode(x, base + reg.offset, \ 56 mask, reg.shift, v, reg.write_mask) 57 58 #define VOP_WIN_SET(x, win, name, v) \ 59 REG_SET(x, win->base, win->phy->name, v, RELAXED) 60 #define VOP_SCL_SET(x, win, name, v) \ 61 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 62 #define VOP_SCL_SET_EXT(x, win, name, v) \ 63 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) 64 #define VOP_CTRL_SET(x, name, v) \ 65 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 66 67 #define VOP_INTR_GET(vop, name) \ 68 vop_read_reg(vop, 0, &vop->data->ctrl->name) 69 70 #define VOP_INTR_SET(vop, name, mask, v) \ 71 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) 72 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 73 do { \ 74 int i, reg = 0, mask = 0; \ 75 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 76 if (vop->data->intr->intrs[i] & type) { \ 77 reg |= (v) << i; \ 78 mask |= 1 << i; \ 79 } \ 80 } \ 81 VOP_INTR_SET(vop, name, mask, reg); \ 82 } while (0) 83 #define VOP_INTR_GET_TYPE(vop, name, type) \ 84 vop_get_intr_type(vop, &vop->data->intr->name, type) 85 86 #define VOP_WIN_GET(x, win, name) \ 87 vop_read_reg(x, win->base, &win->phy->name) 88 89 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 91 92 #define to_vop(x) container_of(x, struct vop, crtc) 93 #define to_vop_win(x) container_of(x, struct vop_win, base) 94 95 enum vop_pending { 96 VOP_PENDING_FB_UNREF, 97 }; 98 99 struct vop_win { 100 struct drm_plane base; 101 const struct vop_win_data *data; 102 struct vop *vop; 103 }; 104 105 struct vop { 106 struct drm_crtc crtc; 107 struct device *dev; 108 struct drm_device *drm_dev; 109 bool is_enabled; 110 111 /* mutex vsync_ work */ 112 struct mutex vsync_mutex; 113 bool vsync_work_pending; 114 struct completion dsp_hold_completion; 115 116 /* protected by dev->event_lock */ 117 struct drm_pending_vblank_event *event; 118 119 struct drm_flip_work fb_unref_work; 120 unsigned long pending; 121 122 struct completion line_flag_completion; 123 124 const struct vop_data *data; 125 126 uint32_t *regsbak; 127 void __iomem *regs; 128 129 /* physical map length of vop register */ 130 uint32_t len; 131 132 /* one time only one process allowed to config the register */ 133 spinlock_t reg_lock; 134 /* lock vop irq reg */ 135 spinlock_t irq_lock; 136 137 unsigned int irq; 138 139 /* vop AHP clk */ 140 struct clk *hclk; 141 /* vop dclk */ 142 struct clk *dclk; 143 /* vop share memory frequency */ 144 struct clk *aclk; 145 146 /* vop dclk reset */ 147 struct reset_control *dclk_rst; 148 149 struct vop_win win[]; 150 }; 151 152 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 153 { 154 writel(v, vop->regs + offset); 155 vop->regsbak[offset >> 2] = v; 156 } 157 158 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 159 { 160 return readl(vop->regs + offset); 161 } 162 163 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 164 const struct vop_reg *reg) 165 { 166 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 167 } 168 169 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 170 uint32_t mask, uint32_t shift, uint32_t v, 171 bool write_mask, bool relaxed) 172 { 173 if (!mask) 174 return; 175 176 if (write_mask) { 177 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 178 } else { 179 uint32_t cached_val = vop->regsbak[offset >> 2]; 180 181 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 182 vop->regsbak[offset >> 2] = v; 183 } 184 185 if (relaxed) 186 writel_relaxed(v, vop->regs + offset); 187 else 188 writel(v, vop->regs + offset); 189 } 190 191 static inline uint32_t vop_get_intr_type(struct vop *vop, 192 const struct vop_reg *reg, int type) 193 { 194 uint32_t i, ret = 0; 195 uint32_t regs = vop_read_reg(vop, 0, reg); 196 197 for (i = 0; i < vop->data->intr->nintrs; i++) { 198 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 199 ret |= vop->data->intr->intrs[i]; 200 } 201 202 return ret; 203 } 204 205 static inline void vop_cfg_done(struct vop *vop) 206 { 207 VOP_CTRL_SET(vop, cfg_done, 1); 208 } 209 210 static bool has_rb_swapped(uint32_t format) 211 { 212 switch (format) { 213 case DRM_FORMAT_XBGR8888: 214 case DRM_FORMAT_ABGR8888: 215 case DRM_FORMAT_BGR888: 216 case DRM_FORMAT_BGR565: 217 return true; 218 default: 219 return false; 220 } 221 } 222 223 static enum vop_data_format vop_convert_format(uint32_t format) 224 { 225 switch (format) { 226 case DRM_FORMAT_XRGB8888: 227 case DRM_FORMAT_ARGB8888: 228 case DRM_FORMAT_XBGR8888: 229 case DRM_FORMAT_ABGR8888: 230 return VOP_FMT_ARGB8888; 231 case DRM_FORMAT_RGB888: 232 case DRM_FORMAT_BGR888: 233 return VOP_FMT_RGB888; 234 case DRM_FORMAT_RGB565: 235 case DRM_FORMAT_BGR565: 236 return VOP_FMT_RGB565; 237 case DRM_FORMAT_NV12: 238 return VOP_FMT_YUV420SP; 239 case DRM_FORMAT_NV16: 240 return VOP_FMT_YUV422SP; 241 case DRM_FORMAT_NV24: 242 return VOP_FMT_YUV444SP; 243 default: 244 DRM_ERROR("unsupported format[%08x]\n", format); 245 return -EINVAL; 246 } 247 } 248 249 static bool is_yuv_support(uint32_t format) 250 { 251 switch (format) { 252 case DRM_FORMAT_NV12: 253 case DRM_FORMAT_NV16: 254 case DRM_FORMAT_NV24: 255 return true; 256 default: 257 return false; 258 } 259 } 260 261 static bool is_alpha_support(uint32_t format) 262 { 263 switch (format) { 264 case DRM_FORMAT_ARGB8888: 265 case DRM_FORMAT_ABGR8888: 266 return true; 267 default: 268 return false; 269 } 270 } 271 272 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 273 uint32_t dst, bool is_horizontal, 274 int vsu_mode, int *vskiplines) 275 { 276 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 277 278 if (is_horizontal) { 279 if (mode == SCALE_UP) 280 val = GET_SCL_FT_BIC(src, dst); 281 else if (mode == SCALE_DOWN) 282 val = GET_SCL_FT_BILI_DN(src, dst); 283 } else { 284 if (mode == SCALE_UP) { 285 if (vsu_mode == SCALE_UP_BIL) 286 val = GET_SCL_FT_BILI_UP(src, dst); 287 else 288 val = GET_SCL_FT_BIC(src, dst); 289 } else if (mode == SCALE_DOWN) { 290 if (vskiplines) { 291 *vskiplines = scl_get_vskiplines(src, dst); 292 val = scl_get_bili_dn_vskip(src, dst, 293 *vskiplines); 294 } else { 295 val = GET_SCL_FT_BILI_DN(src, dst); 296 } 297 } 298 } 299 300 return val; 301 } 302 303 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 304 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 305 uint32_t dst_h, uint32_t pixel_format) 306 { 307 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 308 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 309 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 310 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 311 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 312 bool is_yuv = is_yuv_support(pixel_format); 313 uint16_t cbcr_src_w = src_w / hsub; 314 uint16_t cbcr_src_h = src_h / vsub; 315 uint16_t vsu_mode; 316 uint16_t lb_mode; 317 uint32_t val; 318 int vskiplines = 0; 319 320 if (dst_w > 3840) { 321 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 322 return; 323 } 324 325 if (!win->phy->scl->ext) { 326 VOP_SCL_SET(vop, win, scale_yrgb_x, 327 scl_cal_scale2(src_w, dst_w)); 328 VOP_SCL_SET(vop, win, scale_yrgb_y, 329 scl_cal_scale2(src_h, dst_h)); 330 if (is_yuv) { 331 VOP_SCL_SET(vop, win, scale_cbcr_x, 332 scl_cal_scale2(cbcr_src_w, dst_w)); 333 VOP_SCL_SET(vop, win, scale_cbcr_y, 334 scl_cal_scale2(cbcr_src_h, dst_h)); 335 } 336 return; 337 } 338 339 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 340 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 341 342 if (is_yuv) { 343 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 344 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 345 if (cbcr_hor_scl_mode == SCALE_DOWN) 346 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 347 else 348 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 349 } else { 350 if (yrgb_hor_scl_mode == SCALE_DOWN) 351 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 352 else 353 lb_mode = scl_vop_cal_lb_mode(src_w, false); 354 } 355 356 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 357 if (lb_mode == LB_RGB_3840X2) { 358 if (yrgb_ver_scl_mode != SCALE_NONE) { 359 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 360 return; 361 } 362 if (cbcr_ver_scl_mode != SCALE_NONE) { 363 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 364 return; 365 } 366 vsu_mode = SCALE_UP_BIL; 367 } else if (lb_mode == LB_RGB_2560X4) { 368 vsu_mode = SCALE_UP_BIL; 369 } else { 370 vsu_mode = SCALE_UP_BIC; 371 } 372 373 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 374 true, 0, NULL); 375 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 376 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 377 false, vsu_mode, &vskiplines); 378 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 379 380 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 381 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 382 383 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 384 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 385 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 386 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 387 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 388 if (is_yuv) { 389 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 390 dst_w, true, 0, NULL); 391 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 392 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 393 dst_h, false, vsu_mode, &vskiplines); 394 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 395 396 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 397 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 398 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 399 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 400 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 401 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 402 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 403 } 404 } 405 406 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 407 { 408 unsigned long flags; 409 410 if (WARN_ON(!vop->is_enabled)) 411 return; 412 413 spin_lock_irqsave(&vop->irq_lock, flags); 414 415 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 416 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 417 418 spin_unlock_irqrestore(&vop->irq_lock, flags); 419 } 420 421 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 422 { 423 unsigned long flags; 424 425 if (WARN_ON(!vop->is_enabled)) 426 return; 427 428 spin_lock_irqsave(&vop->irq_lock, flags); 429 430 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 431 432 spin_unlock_irqrestore(&vop->irq_lock, flags); 433 } 434 435 /* 436 * (1) each frame starts at the start of the Vsync pulse which is signaled by 437 * the "FRAME_SYNC" interrupt. 438 * (2) the active data region of each frame ends at dsp_vact_end 439 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 440 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 441 * 442 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 443 * Interrupts 444 * LINE_FLAG -------------------------------+ 445 * FRAME_SYNC ----+ | 446 * | | 447 * v v 448 * | Vsync | Vbp | Vactive | Vfp | 449 * ^ ^ ^ ^ 450 * | | | | 451 * | | | | 452 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 453 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 454 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 455 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 456 */ 457 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 458 { 459 uint32_t line_flag_irq; 460 unsigned long flags; 461 462 spin_lock_irqsave(&vop->irq_lock, flags); 463 464 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 465 466 spin_unlock_irqrestore(&vop->irq_lock, flags); 467 468 return !!line_flag_irq; 469 } 470 471 static void vop_line_flag_irq_enable(struct vop *vop, int line_num) 472 { 473 unsigned long flags; 474 475 if (WARN_ON(!vop->is_enabled)) 476 return; 477 478 spin_lock_irqsave(&vop->irq_lock, flags); 479 480 VOP_CTRL_SET(vop, line_flag_num[0], line_num); 481 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 482 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 483 484 spin_unlock_irqrestore(&vop->irq_lock, flags); 485 } 486 487 static void vop_line_flag_irq_disable(struct vop *vop) 488 { 489 unsigned long flags; 490 491 if (WARN_ON(!vop->is_enabled)) 492 return; 493 494 spin_lock_irqsave(&vop->irq_lock, flags); 495 496 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 497 498 spin_unlock_irqrestore(&vop->irq_lock, flags); 499 } 500 501 static int vop_enable(struct drm_crtc *crtc) 502 { 503 struct vop *vop = to_vop(crtc); 504 int ret; 505 506 ret = pm_runtime_get_sync(vop->dev); 507 if (ret < 0) { 508 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 509 return ret; 510 } 511 512 ret = clk_enable(vop->hclk); 513 if (WARN_ON(ret < 0)) 514 goto err_put_pm_runtime; 515 516 ret = clk_enable(vop->dclk); 517 if (WARN_ON(ret < 0)) 518 goto err_disable_hclk; 519 520 ret = clk_enable(vop->aclk); 521 if (WARN_ON(ret < 0)) 522 goto err_disable_dclk; 523 524 /* 525 * Slave iommu shares power, irq and clock with vop. It was associated 526 * automatically with this master device via common driver code. 527 * Now that we have enabled the clock we attach it to the shared drm 528 * mapping. 529 */ 530 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 531 if (ret) { 532 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 533 goto err_disable_aclk; 534 } 535 536 memcpy(vop->regs, vop->regsbak, vop->len); 537 vop_cfg_done(vop); 538 539 /* 540 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 541 */ 542 vop->is_enabled = true; 543 544 spin_lock(&vop->reg_lock); 545 546 VOP_CTRL_SET(vop, standby, 0); 547 548 spin_unlock(&vop->reg_lock); 549 550 enable_irq(vop->irq); 551 552 drm_crtc_vblank_on(crtc); 553 554 return 0; 555 556 err_disable_aclk: 557 clk_disable(vop->aclk); 558 err_disable_dclk: 559 clk_disable(vop->dclk); 560 err_disable_hclk: 561 clk_disable(vop->hclk); 562 err_put_pm_runtime: 563 pm_runtime_put_sync(vop->dev); 564 return ret; 565 } 566 567 static void vop_crtc_disable(struct drm_crtc *crtc) 568 { 569 struct vop *vop = to_vop(crtc); 570 int i; 571 572 WARN_ON(vop->event); 573 574 rockchip_drm_psr_deactivate(&vop->crtc); 575 576 /* 577 * We need to make sure that all windows are disabled before we 578 * disable that crtc. Otherwise we might try to scan from a destroyed 579 * buffer later. 580 */ 581 for (i = 0; i < vop->data->win_size; i++) { 582 struct vop_win *vop_win = &vop->win[i]; 583 const struct vop_win_data *win = vop_win->data; 584 585 spin_lock(&vop->reg_lock); 586 VOP_WIN_SET(vop, win, enable, 0); 587 spin_unlock(&vop->reg_lock); 588 } 589 590 vop_cfg_done(vop); 591 592 drm_crtc_vblank_off(crtc); 593 594 /* 595 * Vop standby will take effect at end of current frame, 596 * if dsp hold valid irq happen, it means standby complete. 597 * 598 * we must wait standby complete when we want to disable aclk, 599 * if not, memory bus maybe dead. 600 */ 601 reinit_completion(&vop->dsp_hold_completion); 602 vop_dsp_hold_valid_irq_enable(vop); 603 604 spin_lock(&vop->reg_lock); 605 606 VOP_CTRL_SET(vop, standby, 1); 607 608 spin_unlock(&vop->reg_lock); 609 610 wait_for_completion(&vop->dsp_hold_completion); 611 612 vop_dsp_hold_valid_irq_disable(vop); 613 614 disable_irq(vop->irq); 615 616 vop->is_enabled = false; 617 618 /* 619 * vop standby complete, so iommu detach is safe. 620 */ 621 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 622 623 clk_disable(vop->dclk); 624 clk_disable(vop->aclk); 625 clk_disable(vop->hclk); 626 pm_runtime_put(vop->dev); 627 628 if (crtc->state->event && !crtc->state->active) { 629 spin_lock_irq(&crtc->dev->event_lock); 630 drm_crtc_send_vblank_event(crtc, crtc->state->event); 631 spin_unlock_irq(&crtc->dev->event_lock); 632 633 crtc->state->event = NULL; 634 } 635 } 636 637 static void vop_plane_destroy(struct drm_plane *plane) 638 { 639 drm_plane_cleanup(plane); 640 } 641 642 static int vop_plane_atomic_check(struct drm_plane *plane, 643 struct drm_plane_state *state) 644 { 645 struct drm_crtc *crtc = state->crtc; 646 struct drm_crtc_state *crtc_state; 647 struct drm_framebuffer *fb = state->fb; 648 struct vop_win *vop_win = to_vop_win(plane); 649 const struct vop_win_data *win = vop_win->data; 650 int ret; 651 struct drm_rect clip; 652 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 653 DRM_PLANE_HELPER_NO_SCALING; 654 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 655 DRM_PLANE_HELPER_NO_SCALING; 656 657 if (!crtc || !fb) 658 return 0; 659 660 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 661 if (WARN_ON(!crtc_state)) 662 return -EINVAL; 663 664 clip.x1 = 0; 665 clip.y1 = 0; 666 clip.x2 = crtc_state->adjusted_mode.hdisplay; 667 clip.y2 = crtc_state->adjusted_mode.vdisplay; 668 669 ret = drm_plane_helper_check_state(state, &clip, 670 min_scale, max_scale, 671 true, true); 672 if (ret) 673 return ret; 674 675 if (!state->visible) 676 return 0; 677 678 ret = vop_convert_format(fb->format->format); 679 if (ret < 0) 680 return ret; 681 682 /* 683 * Src.x1 can be odd when do clip, but yuv plane start point 684 * need align with 2 pixel. 685 */ 686 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) 687 return -EINVAL; 688 689 return 0; 690 } 691 692 static void vop_plane_atomic_disable(struct drm_plane *plane, 693 struct drm_plane_state *old_state) 694 { 695 struct vop_win *vop_win = to_vop_win(plane); 696 const struct vop_win_data *win = vop_win->data; 697 struct vop *vop = to_vop(old_state->crtc); 698 699 if (!old_state->crtc) 700 return; 701 702 spin_lock(&vop->reg_lock); 703 704 VOP_WIN_SET(vop, win, enable, 0); 705 706 spin_unlock(&vop->reg_lock); 707 } 708 709 static void vop_plane_atomic_update(struct drm_plane *plane, 710 struct drm_plane_state *old_state) 711 { 712 struct drm_plane_state *state = plane->state; 713 struct drm_crtc *crtc = state->crtc; 714 struct vop_win *vop_win = to_vop_win(plane); 715 const struct vop_win_data *win = vop_win->data; 716 struct vop *vop = to_vop(state->crtc); 717 struct drm_framebuffer *fb = state->fb; 718 unsigned int actual_w, actual_h; 719 unsigned int dsp_stx, dsp_sty; 720 uint32_t act_info, dsp_info, dsp_st; 721 struct drm_rect *src = &state->src; 722 struct drm_rect *dest = &state->dst; 723 struct drm_gem_object *obj, *uv_obj; 724 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 725 unsigned long offset; 726 dma_addr_t dma_addr; 727 uint32_t val; 728 bool rb_swap; 729 int format; 730 731 /* 732 * can't update plane when vop is disabled. 733 */ 734 if (WARN_ON(!crtc)) 735 return; 736 737 if (WARN_ON(!vop->is_enabled)) 738 return; 739 740 if (!state->visible) { 741 vop_plane_atomic_disable(plane, old_state); 742 return; 743 } 744 745 obj = rockchip_fb_get_gem_obj(fb, 0); 746 rk_obj = to_rockchip_obj(obj); 747 748 actual_w = drm_rect_width(src) >> 16; 749 actual_h = drm_rect_height(src) >> 16; 750 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 751 752 dsp_info = (drm_rect_height(dest) - 1) << 16; 753 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 754 755 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 756 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 757 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 758 759 offset = (src->x1 >> 16) * fb->format->cpp[0]; 760 offset += (src->y1 >> 16) * fb->pitches[0]; 761 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 762 763 format = vop_convert_format(fb->format->format); 764 765 spin_lock(&vop->reg_lock); 766 767 VOP_WIN_SET(vop, win, format, format); 768 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 769 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 770 if (is_yuv_support(fb->format->format)) { 771 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 772 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 773 int bpp = fb->format->cpp[1]; 774 775 uv_obj = rockchip_fb_get_gem_obj(fb, 1); 776 rk_uv_obj = to_rockchip_obj(uv_obj); 777 778 offset = (src->x1 >> 16) * bpp / hsub; 779 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 780 781 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 782 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 783 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 784 } 785 786 if (win->phy->scl) 787 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 788 drm_rect_width(dest), drm_rect_height(dest), 789 fb->format->format); 790 791 VOP_WIN_SET(vop, win, act_info, act_info); 792 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 793 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 794 795 rb_swap = has_rb_swapped(fb->format->format); 796 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 797 798 if (is_alpha_support(fb->format->format)) { 799 VOP_WIN_SET(vop, win, dst_alpha_ctl, 800 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 801 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 802 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 803 SRC_BLEND_M0(ALPHA_PER_PIX) | 804 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 805 SRC_FACTOR_M0(ALPHA_ONE); 806 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 807 } else { 808 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 809 } 810 811 VOP_WIN_SET(vop, win, enable, 1); 812 spin_unlock(&vop->reg_lock); 813 } 814 815 static const struct drm_plane_helper_funcs plane_helper_funcs = { 816 .atomic_check = vop_plane_atomic_check, 817 .atomic_update = vop_plane_atomic_update, 818 .atomic_disable = vop_plane_atomic_disable, 819 }; 820 821 static const struct drm_plane_funcs vop_plane_funcs = { 822 .update_plane = drm_atomic_helper_update_plane, 823 .disable_plane = drm_atomic_helper_disable_plane, 824 .destroy = vop_plane_destroy, 825 .reset = drm_atomic_helper_plane_reset, 826 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 827 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 828 }; 829 830 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 831 { 832 struct vop *vop = to_vop(crtc); 833 unsigned long flags; 834 835 if (WARN_ON(!vop->is_enabled)) 836 return -EPERM; 837 838 spin_lock_irqsave(&vop->irq_lock, flags); 839 840 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 841 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 842 843 spin_unlock_irqrestore(&vop->irq_lock, flags); 844 845 return 0; 846 } 847 848 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 849 { 850 struct vop *vop = to_vop(crtc); 851 unsigned long flags; 852 853 if (WARN_ON(!vop->is_enabled)) 854 return; 855 856 spin_lock_irqsave(&vop->irq_lock, flags); 857 858 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 859 860 spin_unlock_irqrestore(&vop->irq_lock, flags); 861 } 862 863 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 864 const struct drm_display_mode *mode, 865 struct drm_display_mode *adjusted_mode) 866 { 867 struct vop *vop = to_vop(crtc); 868 869 adjusted_mode->clock = 870 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 871 872 return true; 873 } 874 875 static void vop_crtc_enable(struct drm_crtc *crtc) 876 { 877 struct vop *vop = to_vop(crtc); 878 const struct vop_data *vop_data = vop->data; 879 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 880 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 881 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 882 u16 hdisplay = adjusted_mode->hdisplay; 883 u16 htotal = adjusted_mode->htotal; 884 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 885 u16 hact_end = hact_st + hdisplay; 886 u16 vdisplay = adjusted_mode->vdisplay; 887 u16 vtotal = adjusted_mode->vtotal; 888 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 889 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 890 u16 vact_end = vact_st + vdisplay; 891 uint32_t pin_pol, val; 892 int ret; 893 894 WARN_ON(vop->event); 895 896 ret = vop_enable(crtc); 897 if (ret) { 898 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 899 return; 900 } 901 902 /* 903 * If dclk rate is zero, mean that scanout is stop, 904 * we don't need wait any more. 905 */ 906 if (clk_get_rate(vop->dclk)) { 907 /* 908 * Rk3288 vop timing register is immediately, when configure 909 * display timing on display time, may cause tearing. 910 * 911 * Vop standby will take effect at end of current frame, 912 * if dsp hold valid irq happen, it means standby complete. 913 * 914 * mode set: 915 * standby and wait complete --> |---- 916 * | display time 917 * |---- 918 * |---> dsp hold irq 919 * configure display timing --> | 920 * standby exit | 921 * | new frame start. 922 */ 923 924 reinit_completion(&vop->dsp_hold_completion); 925 vop_dsp_hold_valid_irq_enable(vop); 926 927 spin_lock(&vop->reg_lock); 928 929 VOP_CTRL_SET(vop, standby, 1); 930 931 spin_unlock(&vop->reg_lock); 932 933 wait_for_completion(&vop->dsp_hold_completion); 934 935 vop_dsp_hold_valid_irq_disable(vop); 936 } 937 938 pin_pol = BIT(DCLK_INVERT); 939 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 940 BIT(HSYNC_POSITIVE) : 0; 941 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 942 BIT(VSYNC_POSITIVE) : 0; 943 VOP_CTRL_SET(vop, pin_pol, pin_pol); 944 945 switch (s->output_type) { 946 case DRM_MODE_CONNECTOR_LVDS: 947 VOP_CTRL_SET(vop, rgb_en, 1); 948 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); 949 break; 950 case DRM_MODE_CONNECTOR_eDP: 951 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); 952 VOP_CTRL_SET(vop, edp_en, 1); 953 break; 954 case DRM_MODE_CONNECTOR_HDMIA: 955 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); 956 VOP_CTRL_SET(vop, hdmi_en, 1); 957 break; 958 case DRM_MODE_CONNECTOR_DSI: 959 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); 960 VOP_CTRL_SET(vop, mipi_en, 1); 961 break; 962 case DRM_MODE_CONNECTOR_DisplayPort: 963 pin_pol &= ~BIT(DCLK_INVERT); 964 VOP_CTRL_SET(vop, dp_pin_pol, pin_pol); 965 VOP_CTRL_SET(vop, dp_en, 1); 966 break; 967 default: 968 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 969 s->output_type); 970 } 971 972 /* 973 * if vop is not support RGB10 output, need force RGB10 to RGB888. 974 */ 975 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 976 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 977 s->output_mode = ROCKCHIP_OUT_MODE_P888; 978 VOP_CTRL_SET(vop, out_mode, s->output_mode); 979 980 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 981 val = hact_st << 16; 982 val |= hact_end; 983 VOP_CTRL_SET(vop, hact_st_end, val); 984 VOP_CTRL_SET(vop, hpost_st_end, val); 985 986 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 987 val = vact_st << 16; 988 val |= vact_end; 989 VOP_CTRL_SET(vop, vact_st_end, val); 990 VOP_CTRL_SET(vop, vpost_st_end, val); 991 992 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 993 994 VOP_CTRL_SET(vop, standby, 0); 995 996 rockchip_drm_psr_activate(&vop->crtc); 997 } 998 999 static bool vop_fs_irq_is_pending(struct vop *vop) 1000 { 1001 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1002 } 1003 1004 static void vop_wait_for_irq_handler(struct vop *vop) 1005 { 1006 bool pending; 1007 int ret; 1008 1009 /* 1010 * Spin until frame start interrupt status bit goes low, which means 1011 * that interrupt handler was invoked and cleared it. The timeout of 1012 * 10 msecs is really too long, but it is just a safety measure if 1013 * something goes really wrong. The wait will only happen in the very 1014 * unlikely case of a vblank happening exactly at the same time and 1015 * shouldn't exceed microseconds range. 1016 */ 1017 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1018 !pending, 0, 10 * 1000); 1019 if (ret) 1020 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1021 1022 synchronize_irq(vop->irq); 1023 } 1024 1025 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1026 struct drm_crtc_state *old_crtc_state) 1027 { 1028 struct drm_atomic_state *old_state = old_crtc_state->state; 1029 struct drm_plane_state *old_plane_state; 1030 struct vop *vop = to_vop(crtc); 1031 struct drm_plane *plane; 1032 int i; 1033 1034 if (WARN_ON(!vop->is_enabled)) 1035 return; 1036 1037 spin_lock(&vop->reg_lock); 1038 1039 vop_cfg_done(vop); 1040 1041 spin_unlock(&vop->reg_lock); 1042 1043 /* 1044 * There is a (rather unlikely) possiblity that a vblank interrupt 1045 * fired before we set the cfg_done bit. To avoid spuriously 1046 * signalling flip completion we need to wait for it to finish. 1047 */ 1048 vop_wait_for_irq_handler(vop); 1049 1050 spin_lock_irq(&crtc->dev->event_lock); 1051 if (crtc->state->event) { 1052 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1053 WARN_ON(vop->event); 1054 1055 vop->event = crtc->state->event; 1056 crtc->state->event = NULL; 1057 } 1058 spin_unlock_irq(&crtc->dev->event_lock); 1059 1060 for_each_plane_in_state(old_state, plane, old_plane_state, i) { 1061 if (!old_plane_state->fb) 1062 continue; 1063 1064 if (old_plane_state->fb == plane->state->fb) 1065 continue; 1066 1067 drm_framebuffer_reference(old_plane_state->fb); 1068 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1069 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1070 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1071 } 1072 } 1073 1074 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1075 struct drm_crtc_state *old_crtc_state) 1076 { 1077 rockchip_drm_psr_flush(crtc); 1078 } 1079 1080 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1081 .enable = vop_crtc_enable, 1082 .disable = vop_crtc_disable, 1083 .mode_fixup = vop_crtc_mode_fixup, 1084 .atomic_flush = vop_crtc_atomic_flush, 1085 .atomic_begin = vop_crtc_atomic_begin, 1086 }; 1087 1088 static void vop_crtc_destroy(struct drm_crtc *crtc) 1089 { 1090 drm_crtc_cleanup(crtc); 1091 } 1092 1093 static void vop_crtc_reset(struct drm_crtc *crtc) 1094 { 1095 if (crtc->state) 1096 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1097 kfree(crtc->state); 1098 1099 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1100 if (crtc->state) 1101 crtc->state->crtc = crtc; 1102 } 1103 1104 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1105 { 1106 struct rockchip_crtc_state *rockchip_state; 1107 1108 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1109 if (!rockchip_state) 1110 return NULL; 1111 1112 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1113 return &rockchip_state->base; 1114 } 1115 1116 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1117 struct drm_crtc_state *state) 1118 { 1119 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1120 1121 __drm_atomic_helper_crtc_destroy_state(&s->base); 1122 kfree(s); 1123 } 1124 1125 #ifdef CONFIG_DRM_ANALOGIX_DP 1126 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1127 { 1128 struct drm_crtc *crtc = &vop->crtc; 1129 struct drm_connector *connector; 1130 1131 mutex_lock(&crtc->dev->mode_config.mutex); 1132 drm_for_each_connector(connector, crtc->dev) 1133 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1134 mutex_unlock(&crtc->dev->mode_config.mutex); 1135 return connector; 1136 } 1137 mutex_unlock(&crtc->dev->mode_config.mutex); 1138 1139 return NULL; 1140 } 1141 1142 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1143 const char *source_name, size_t *values_cnt) 1144 { 1145 struct vop *vop = to_vop(crtc); 1146 struct drm_connector *connector; 1147 int ret; 1148 1149 connector = vop_get_edp_connector(vop); 1150 if (!connector) 1151 return -EINVAL; 1152 1153 *values_cnt = 3; 1154 1155 if (source_name && strcmp(source_name, "auto") == 0) 1156 ret = analogix_dp_start_crc(connector); 1157 else if (!source_name) 1158 ret = analogix_dp_stop_crc(connector); 1159 else 1160 ret = -EINVAL; 1161 1162 return ret; 1163 } 1164 #else 1165 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1166 const char *source_name, size_t *values_cnt) 1167 { 1168 return -ENODEV; 1169 } 1170 #endif 1171 1172 static const struct drm_crtc_funcs vop_crtc_funcs = { 1173 .set_config = drm_atomic_helper_set_config, 1174 .page_flip = drm_atomic_helper_page_flip, 1175 .destroy = vop_crtc_destroy, 1176 .reset = vop_crtc_reset, 1177 .atomic_duplicate_state = vop_crtc_duplicate_state, 1178 .atomic_destroy_state = vop_crtc_destroy_state, 1179 .enable_vblank = vop_crtc_enable_vblank, 1180 .disable_vblank = vop_crtc_disable_vblank, 1181 .set_crc_source = vop_crtc_set_crc_source, 1182 }; 1183 1184 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1185 { 1186 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1187 struct drm_framebuffer *fb = val; 1188 1189 drm_crtc_vblank_put(&vop->crtc); 1190 drm_framebuffer_unreference(fb); 1191 } 1192 1193 static void vop_handle_vblank(struct vop *vop) 1194 { 1195 struct drm_device *drm = vop->drm_dev; 1196 struct drm_crtc *crtc = &vop->crtc; 1197 unsigned long flags; 1198 1199 spin_lock_irqsave(&drm->event_lock, flags); 1200 if (vop->event) { 1201 drm_crtc_send_vblank_event(crtc, vop->event); 1202 drm_crtc_vblank_put(crtc); 1203 vop->event = NULL; 1204 } 1205 spin_unlock_irqrestore(&drm->event_lock, flags); 1206 1207 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1208 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1209 } 1210 1211 static irqreturn_t vop_isr(int irq, void *data) 1212 { 1213 struct vop *vop = data; 1214 struct drm_crtc *crtc = &vop->crtc; 1215 uint32_t active_irqs; 1216 unsigned long flags; 1217 int ret = IRQ_NONE; 1218 1219 /* 1220 * interrupt register has interrupt status, enable and clear bits, we 1221 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1222 */ 1223 spin_lock_irqsave(&vop->irq_lock, flags); 1224 1225 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1226 /* Clear all active interrupt sources */ 1227 if (active_irqs) 1228 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1229 1230 spin_unlock_irqrestore(&vop->irq_lock, flags); 1231 1232 /* This is expected for vop iommu irqs, since the irq is shared */ 1233 if (!active_irqs) 1234 return IRQ_NONE; 1235 1236 if (active_irqs & DSP_HOLD_VALID_INTR) { 1237 complete(&vop->dsp_hold_completion); 1238 active_irqs &= ~DSP_HOLD_VALID_INTR; 1239 ret = IRQ_HANDLED; 1240 } 1241 1242 if (active_irqs & LINE_FLAG_INTR) { 1243 complete(&vop->line_flag_completion); 1244 active_irqs &= ~LINE_FLAG_INTR; 1245 ret = IRQ_HANDLED; 1246 } 1247 1248 if (active_irqs & FS_INTR) { 1249 drm_crtc_handle_vblank(crtc); 1250 vop_handle_vblank(vop); 1251 active_irqs &= ~FS_INTR; 1252 ret = IRQ_HANDLED; 1253 } 1254 1255 /* Unhandled irqs are spurious. */ 1256 if (active_irqs) 1257 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1258 active_irqs); 1259 1260 return ret; 1261 } 1262 1263 static int vop_create_crtc(struct vop *vop) 1264 { 1265 const struct vop_data *vop_data = vop->data; 1266 struct device *dev = vop->dev; 1267 struct drm_device *drm_dev = vop->drm_dev; 1268 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1269 struct drm_crtc *crtc = &vop->crtc; 1270 struct device_node *port; 1271 int ret; 1272 int i; 1273 1274 /* 1275 * Create drm_plane for primary and cursor planes first, since we need 1276 * to pass them to drm_crtc_init_with_planes, which sets the 1277 * "possible_crtcs" to the newly initialized crtc. 1278 */ 1279 for (i = 0; i < vop_data->win_size; i++) { 1280 struct vop_win *vop_win = &vop->win[i]; 1281 const struct vop_win_data *win_data = vop_win->data; 1282 1283 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1284 win_data->type != DRM_PLANE_TYPE_CURSOR) 1285 continue; 1286 1287 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1288 0, &vop_plane_funcs, 1289 win_data->phy->data_formats, 1290 win_data->phy->nformats, 1291 win_data->type, NULL); 1292 if (ret) { 1293 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1294 ret); 1295 goto err_cleanup_planes; 1296 } 1297 1298 plane = &vop_win->base; 1299 drm_plane_helper_add(plane, &plane_helper_funcs); 1300 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1301 primary = plane; 1302 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1303 cursor = plane; 1304 } 1305 1306 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1307 &vop_crtc_funcs, NULL); 1308 if (ret) 1309 goto err_cleanup_planes; 1310 1311 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1312 1313 /* 1314 * Create drm_planes for overlay windows with possible_crtcs restricted 1315 * to the newly created crtc. 1316 */ 1317 for (i = 0; i < vop_data->win_size; i++) { 1318 struct vop_win *vop_win = &vop->win[i]; 1319 const struct vop_win_data *win_data = vop_win->data; 1320 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1321 1322 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1323 continue; 1324 1325 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1326 possible_crtcs, 1327 &vop_plane_funcs, 1328 win_data->phy->data_formats, 1329 win_data->phy->nformats, 1330 win_data->type, NULL); 1331 if (ret) { 1332 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1333 ret); 1334 goto err_cleanup_crtc; 1335 } 1336 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1337 } 1338 1339 port = of_get_child_by_name(dev->of_node, "port"); 1340 if (!port) { 1341 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n", 1342 dev->of_node->full_name); 1343 ret = -ENOENT; 1344 goto err_cleanup_crtc; 1345 } 1346 1347 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1348 vop_fb_unref_worker); 1349 1350 init_completion(&vop->dsp_hold_completion); 1351 init_completion(&vop->line_flag_completion); 1352 crtc->port = port; 1353 1354 return 0; 1355 1356 err_cleanup_crtc: 1357 drm_crtc_cleanup(crtc); 1358 err_cleanup_planes: 1359 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1360 head) 1361 drm_plane_cleanup(plane); 1362 return ret; 1363 } 1364 1365 static void vop_destroy_crtc(struct vop *vop) 1366 { 1367 struct drm_crtc *crtc = &vop->crtc; 1368 struct drm_device *drm_dev = vop->drm_dev; 1369 struct drm_plane *plane, *tmp; 1370 1371 of_node_put(crtc->port); 1372 1373 /* 1374 * We need to cleanup the planes now. Why? 1375 * 1376 * The planes are "&vop->win[i].base". That means the memory is 1377 * all part of the big "struct vop" chunk of memory. That memory 1378 * was devm allocated and associated with this component. We need to 1379 * free it ourselves before vop_unbind() finishes. 1380 */ 1381 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1382 head) 1383 vop_plane_destroy(plane); 1384 1385 /* 1386 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1387 * references the CRTC. 1388 */ 1389 drm_crtc_cleanup(crtc); 1390 drm_flip_work_cleanup(&vop->fb_unref_work); 1391 } 1392 1393 static int vop_initial(struct vop *vop) 1394 { 1395 const struct vop_data *vop_data = vop->data; 1396 const struct vop_reg_data *init_table = vop_data->init_table; 1397 struct reset_control *ahb_rst; 1398 int i, ret; 1399 1400 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1401 if (IS_ERR(vop->hclk)) { 1402 dev_err(vop->dev, "failed to get hclk source\n"); 1403 return PTR_ERR(vop->hclk); 1404 } 1405 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1406 if (IS_ERR(vop->aclk)) { 1407 dev_err(vop->dev, "failed to get aclk source\n"); 1408 return PTR_ERR(vop->aclk); 1409 } 1410 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1411 if (IS_ERR(vop->dclk)) { 1412 dev_err(vop->dev, "failed to get dclk source\n"); 1413 return PTR_ERR(vop->dclk); 1414 } 1415 1416 ret = pm_runtime_get_sync(vop->dev); 1417 if (ret < 0) { 1418 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 1419 return ret; 1420 } 1421 1422 ret = clk_prepare(vop->dclk); 1423 if (ret < 0) { 1424 dev_err(vop->dev, "failed to prepare dclk\n"); 1425 goto err_put_pm_runtime; 1426 } 1427 1428 /* Enable both the hclk and aclk to setup the vop */ 1429 ret = clk_prepare_enable(vop->hclk); 1430 if (ret < 0) { 1431 dev_err(vop->dev, "failed to prepare/enable hclk\n"); 1432 goto err_unprepare_dclk; 1433 } 1434 1435 ret = clk_prepare_enable(vop->aclk); 1436 if (ret < 0) { 1437 dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1438 goto err_disable_hclk; 1439 } 1440 1441 /* 1442 * do hclk_reset, reset all vop registers. 1443 */ 1444 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1445 if (IS_ERR(ahb_rst)) { 1446 dev_err(vop->dev, "failed to get ahb reset\n"); 1447 ret = PTR_ERR(ahb_rst); 1448 goto err_disable_aclk; 1449 } 1450 reset_control_assert(ahb_rst); 1451 usleep_range(10, 20); 1452 reset_control_deassert(ahb_rst); 1453 1454 memcpy(vop->regsbak, vop->regs, vop->len); 1455 1456 for (i = 0; i < vop_data->table_size; i++) 1457 vop_writel(vop, init_table[i].offset, init_table[i].value); 1458 1459 for (i = 0; i < vop_data->win_size; i++) { 1460 const struct vop_win_data *win = &vop_data->win[i]; 1461 1462 VOP_WIN_SET(vop, win, enable, 0); 1463 } 1464 1465 vop_cfg_done(vop); 1466 1467 /* 1468 * do dclk_reset, let all config take affect. 1469 */ 1470 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1471 if (IS_ERR(vop->dclk_rst)) { 1472 dev_err(vop->dev, "failed to get dclk reset\n"); 1473 ret = PTR_ERR(vop->dclk_rst); 1474 goto err_disable_aclk; 1475 } 1476 reset_control_assert(vop->dclk_rst); 1477 usleep_range(10, 20); 1478 reset_control_deassert(vop->dclk_rst); 1479 1480 clk_disable(vop->hclk); 1481 clk_disable(vop->aclk); 1482 1483 vop->is_enabled = false; 1484 1485 pm_runtime_put_sync(vop->dev); 1486 1487 return 0; 1488 1489 err_disable_aclk: 1490 clk_disable_unprepare(vop->aclk); 1491 err_disable_hclk: 1492 clk_disable_unprepare(vop->hclk); 1493 err_unprepare_dclk: 1494 clk_unprepare(vop->dclk); 1495 err_put_pm_runtime: 1496 pm_runtime_put_sync(vop->dev); 1497 return ret; 1498 } 1499 1500 /* 1501 * Initialize the vop->win array elements. 1502 */ 1503 static void vop_win_init(struct vop *vop) 1504 { 1505 const struct vop_data *vop_data = vop->data; 1506 unsigned int i; 1507 1508 for (i = 0; i < vop_data->win_size; i++) { 1509 struct vop_win *vop_win = &vop->win[i]; 1510 const struct vop_win_data *win_data = &vop_data->win[i]; 1511 1512 vop_win->data = win_data; 1513 vop_win->vop = vop; 1514 } 1515 } 1516 1517 /** 1518 * rockchip_drm_wait_line_flag - acqiure the give line flag event 1519 * @crtc: CRTC to enable line flag 1520 * @line_num: interested line number 1521 * @mstimeout: millisecond for timeout 1522 * 1523 * Driver would hold here until the interested line flag interrupt have 1524 * happened or timeout to wait. 1525 * 1526 * Returns: 1527 * Zero on success, negative errno on failure. 1528 */ 1529 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num, 1530 unsigned int mstimeout) 1531 { 1532 struct vop *vop = to_vop(crtc); 1533 unsigned long jiffies_left; 1534 1535 if (!crtc || !vop->is_enabled) 1536 return -ENODEV; 1537 1538 if (line_num > crtc->mode.vtotal || mstimeout <= 0) 1539 return -EINVAL; 1540 1541 if (vop_line_flag_irq_is_enabled(vop)) 1542 return -EBUSY; 1543 1544 reinit_completion(&vop->line_flag_completion); 1545 vop_line_flag_irq_enable(vop, line_num); 1546 1547 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1548 msecs_to_jiffies(mstimeout)); 1549 vop_line_flag_irq_disable(vop); 1550 1551 if (jiffies_left == 0) { 1552 dev_err(vop->dev, "Timeout waiting for IRQ\n"); 1553 return -ETIMEDOUT; 1554 } 1555 1556 return 0; 1557 } 1558 EXPORT_SYMBOL(rockchip_drm_wait_line_flag); 1559 1560 static int vop_bind(struct device *dev, struct device *master, void *data) 1561 { 1562 struct platform_device *pdev = to_platform_device(dev); 1563 const struct vop_data *vop_data; 1564 struct drm_device *drm_dev = data; 1565 struct vop *vop; 1566 struct resource *res; 1567 size_t alloc_size; 1568 int ret, irq; 1569 1570 vop_data = of_device_get_match_data(dev); 1571 if (!vop_data) 1572 return -ENODEV; 1573 1574 /* Allocate vop struct and its vop_win array */ 1575 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1576 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1577 if (!vop) 1578 return -ENOMEM; 1579 1580 vop->dev = dev; 1581 vop->data = vop_data; 1582 vop->drm_dev = drm_dev; 1583 dev_set_drvdata(dev, vop); 1584 1585 vop_win_init(vop); 1586 1587 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1588 vop->len = resource_size(res); 1589 vop->regs = devm_ioremap_resource(dev, res); 1590 if (IS_ERR(vop->regs)) 1591 return PTR_ERR(vop->regs); 1592 1593 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1594 if (!vop->regsbak) 1595 return -ENOMEM; 1596 1597 irq = platform_get_irq(pdev, 0); 1598 if (irq < 0) { 1599 dev_err(dev, "cannot find irq for vop\n"); 1600 return irq; 1601 } 1602 vop->irq = (unsigned int)irq; 1603 1604 spin_lock_init(&vop->reg_lock); 1605 spin_lock_init(&vop->irq_lock); 1606 1607 mutex_init(&vop->vsync_mutex); 1608 1609 ret = devm_request_irq(dev, vop->irq, vop_isr, 1610 IRQF_SHARED, dev_name(dev), vop); 1611 if (ret) 1612 return ret; 1613 1614 /* IRQ is initially disabled; it gets enabled in power_on */ 1615 disable_irq(vop->irq); 1616 1617 ret = vop_create_crtc(vop); 1618 if (ret) 1619 goto err_enable_irq; 1620 1621 pm_runtime_enable(&pdev->dev); 1622 1623 ret = vop_initial(vop); 1624 if (ret < 0) { 1625 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 1626 goto err_disable_pm_runtime; 1627 } 1628 1629 return 0; 1630 1631 err_disable_pm_runtime: 1632 pm_runtime_disable(&pdev->dev); 1633 vop_destroy_crtc(vop); 1634 err_enable_irq: 1635 enable_irq(vop->irq); /* To balance out the disable_irq above */ 1636 return ret; 1637 } 1638 1639 static void vop_unbind(struct device *dev, struct device *master, void *data) 1640 { 1641 struct vop *vop = dev_get_drvdata(dev); 1642 1643 pm_runtime_disable(dev); 1644 vop_destroy_crtc(vop); 1645 1646 clk_unprepare(vop->aclk); 1647 clk_unprepare(vop->hclk); 1648 clk_unprepare(vop->dclk); 1649 } 1650 1651 const struct component_ops vop_component_ops = { 1652 .bind = vop_bind, 1653 .unbind = vop_unbind, 1654 }; 1655 EXPORT_SYMBOL_GPL(vop_component_ops); 1656