1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/log2.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_uapi.h> 23 #include <drm/drm_blend.h> 24 #include <drm/drm_crtc.h> 25 #include <drm/drm_flip_work.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_framebuffer.h> 28 #include <drm/drm_gem_atomic_helper.h> 29 #include <drm/drm_gem_framebuffer_helper.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_self_refresh_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #ifdef CONFIG_DRM_ANALOGIX_DP 35 #include <drm/bridge/analogix_dp.h> 36 #endif 37 38 #include "rockchip_drm_drv.h" 39 #include "rockchip_drm_gem.h" 40 #include "rockchip_drm_fb.h" 41 #include "rockchip_drm_vop.h" 42 #include "rockchip_rgb.h" 43 44 #define VOP_WIN_SET(vop, win, name, v) \ 45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 46 #define VOP_SCL_SET(vop, win, name, v) \ 47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 48 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 49 vop_reg_set(vop, &win->phy->scl->ext->name, \ 50 win->base, ~0, v, #name) 51 52 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 53 do { \ 54 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 56 } while (0) 57 58 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 59 do { \ 60 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 62 } while (0) 63 64 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 65 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 66 67 #define VOP_REG_SET(vop, group, name, v) \ 68 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 69 70 #define VOP_HAS_REG(vop, group, name) \ 71 (!!(vop->data->group->name.mask)) 72 73 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 74 do { \ 75 int i, reg = 0, mask = 0; \ 76 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 77 if (vop->data->intr->intrs[i] & type) { \ 78 reg |= (v) << i; \ 79 mask |= 1 << i; \ 80 } \ 81 } \ 82 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 83 } while (0) 84 #define VOP_INTR_GET_TYPE(vop, name, type) \ 85 vop_get_intr_type(vop, &vop->data->intr->name, type) 86 87 #define VOP_WIN_GET(vop, win, name) \ 88 vop_read_reg(vop, win->base, &win->phy->name) 89 90 #define VOP_WIN_HAS_REG(win, name) \ 91 (!!(win->phy->name.mask)) 92 93 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 94 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 95 96 #define VOP_WIN_TO_INDEX(vop_win) \ 97 ((vop_win) - (vop_win)->vop->win) 98 99 #define VOP_AFBC_SET(vop, name, v) \ 100 do { \ 101 if ((vop)->data->afbc) \ 102 vop_reg_set((vop), &(vop)->data->afbc->name, \ 103 0, ~0, v, #name); \ 104 } while (0) 105 106 #define to_vop(x) container_of(x, struct vop, crtc) 107 #define to_vop_win(x) container_of(x, struct vop_win, base) 108 109 #define AFBC_FMT_RGB565 0x0 110 #define AFBC_FMT_U8U8U8U8 0x5 111 #define AFBC_FMT_U8U8U8 0x4 112 113 #define AFBC_TILE_16x16 BIT(4) 114 115 /* 116 * The coefficients of the following matrix are all fixed points. 117 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 118 * They are all represented in two's complement. 119 */ 120 static const uint32_t bt601_yuv2rgb[] = { 121 0x4A8, 0x0, 0x662, 122 0x4A8, 0x1E6F, 0x1CBF, 123 0x4A8, 0x812, 0x0, 124 0x321168, 0x0877CF, 0x2EB127 125 }; 126 127 enum vop_pending { 128 VOP_PENDING_FB_UNREF, 129 }; 130 131 struct vop_win { 132 struct drm_plane base; 133 const struct vop_win_data *data; 134 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 135 struct vop *vop; 136 }; 137 138 struct rockchip_rgb; 139 struct vop { 140 struct drm_crtc crtc; 141 struct device *dev; 142 struct drm_device *drm_dev; 143 bool is_enabled; 144 145 struct completion dsp_hold_completion; 146 unsigned int win_enabled; 147 148 /* protected by dev->event_lock */ 149 struct drm_pending_vblank_event *event; 150 151 struct drm_flip_work fb_unref_work; 152 unsigned long pending; 153 154 struct completion line_flag_completion; 155 156 const struct vop_data *data; 157 158 uint32_t *regsbak; 159 void __iomem *regs; 160 void __iomem *lut_regs; 161 162 /* physical map length of vop register */ 163 uint32_t len; 164 165 /* one time only one process allowed to config the register */ 166 spinlock_t reg_lock; 167 /* lock vop irq reg */ 168 spinlock_t irq_lock; 169 /* protects crtc enable/disable */ 170 struct mutex vop_lock; 171 172 unsigned int irq; 173 174 /* vop AHP clk */ 175 struct clk *hclk; 176 /* vop dclk */ 177 struct clk *dclk; 178 /* vop share memory frequency */ 179 struct clk *aclk; 180 181 /* vop dclk reset */ 182 struct reset_control *dclk_rst; 183 184 /* optional internal rgb encoder */ 185 struct rockchip_rgb *rgb; 186 187 struct vop_win win[]; 188 }; 189 190 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 191 { 192 return readl(vop->regs + offset); 193 } 194 195 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 196 const struct vop_reg *reg) 197 { 198 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 199 } 200 201 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 202 uint32_t _offset, uint32_t _mask, uint32_t v, 203 const char *reg_name) 204 { 205 int offset, mask, shift; 206 207 if (!reg || !reg->mask) { 208 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 209 return; 210 } 211 212 offset = reg->offset + _offset; 213 mask = reg->mask & _mask; 214 shift = reg->shift; 215 216 if (reg->write_mask) { 217 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 218 } else { 219 uint32_t cached_val = vop->regsbak[offset >> 2]; 220 221 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 222 vop->regsbak[offset >> 2] = v; 223 } 224 225 if (reg->relaxed) 226 writel_relaxed(v, vop->regs + offset); 227 else 228 writel(v, vop->regs + offset); 229 } 230 231 static inline uint32_t vop_get_intr_type(struct vop *vop, 232 const struct vop_reg *reg, int type) 233 { 234 uint32_t i, ret = 0; 235 uint32_t regs = vop_read_reg(vop, 0, reg); 236 237 for (i = 0; i < vop->data->intr->nintrs; i++) { 238 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 239 ret |= vop->data->intr->intrs[i]; 240 } 241 242 return ret; 243 } 244 245 static inline void vop_cfg_done(struct vop *vop) 246 { 247 VOP_REG_SET(vop, common, cfg_done, 1); 248 } 249 250 static bool has_rb_swapped(uint32_t format) 251 { 252 switch (format) { 253 case DRM_FORMAT_XBGR8888: 254 case DRM_FORMAT_ABGR8888: 255 case DRM_FORMAT_BGR888: 256 case DRM_FORMAT_BGR565: 257 return true; 258 default: 259 return false; 260 } 261 } 262 263 static bool has_uv_swapped(uint32_t format) 264 { 265 switch (format) { 266 case DRM_FORMAT_NV21: 267 case DRM_FORMAT_NV61: 268 case DRM_FORMAT_NV42: 269 return true; 270 default: 271 return false; 272 } 273 } 274 275 static enum vop_data_format vop_convert_format(uint32_t format) 276 { 277 switch (format) { 278 case DRM_FORMAT_XRGB8888: 279 case DRM_FORMAT_ARGB8888: 280 case DRM_FORMAT_XBGR8888: 281 case DRM_FORMAT_ABGR8888: 282 return VOP_FMT_ARGB8888; 283 case DRM_FORMAT_RGB888: 284 case DRM_FORMAT_BGR888: 285 return VOP_FMT_RGB888; 286 case DRM_FORMAT_RGB565: 287 case DRM_FORMAT_BGR565: 288 return VOP_FMT_RGB565; 289 case DRM_FORMAT_NV12: 290 case DRM_FORMAT_NV21: 291 return VOP_FMT_YUV420SP; 292 case DRM_FORMAT_NV16: 293 case DRM_FORMAT_NV61: 294 return VOP_FMT_YUV422SP; 295 case DRM_FORMAT_NV24: 296 case DRM_FORMAT_NV42: 297 return VOP_FMT_YUV444SP; 298 default: 299 DRM_ERROR("unsupported format[%08x]\n", format); 300 return -EINVAL; 301 } 302 } 303 304 static int vop_convert_afbc_format(uint32_t format) 305 { 306 switch (format) { 307 case DRM_FORMAT_XRGB8888: 308 case DRM_FORMAT_ARGB8888: 309 case DRM_FORMAT_XBGR8888: 310 case DRM_FORMAT_ABGR8888: 311 return AFBC_FMT_U8U8U8U8; 312 case DRM_FORMAT_RGB888: 313 case DRM_FORMAT_BGR888: 314 return AFBC_FMT_U8U8U8; 315 case DRM_FORMAT_RGB565: 316 case DRM_FORMAT_BGR565: 317 return AFBC_FMT_RGB565; 318 default: 319 DRM_DEBUG_KMS("unsupported AFBC format[%08x]\n", format); 320 return -EINVAL; 321 } 322 } 323 324 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 325 uint32_t dst, bool is_horizontal, 326 int vsu_mode, int *vskiplines) 327 { 328 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 329 330 if (vskiplines) 331 *vskiplines = 0; 332 333 if (is_horizontal) { 334 if (mode == SCALE_UP) 335 val = GET_SCL_FT_BIC(src, dst); 336 else if (mode == SCALE_DOWN) 337 val = GET_SCL_FT_BILI_DN(src, dst); 338 } else { 339 if (mode == SCALE_UP) { 340 if (vsu_mode == SCALE_UP_BIL) 341 val = GET_SCL_FT_BILI_UP(src, dst); 342 else 343 val = GET_SCL_FT_BIC(src, dst); 344 } else if (mode == SCALE_DOWN) { 345 if (vskiplines) { 346 *vskiplines = scl_get_vskiplines(src, dst); 347 val = scl_get_bili_dn_vskip(src, dst, 348 *vskiplines); 349 } else { 350 val = GET_SCL_FT_BILI_DN(src, dst); 351 } 352 } 353 } 354 355 return val; 356 } 357 358 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 359 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 360 uint32_t dst_h, const struct drm_format_info *info) 361 { 362 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 363 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 364 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 365 bool is_yuv = false; 366 uint16_t cbcr_src_w = src_w / info->hsub; 367 uint16_t cbcr_src_h = src_h / info->vsub; 368 uint16_t vsu_mode; 369 uint16_t lb_mode; 370 uint32_t val; 371 int vskiplines; 372 373 if (info->is_yuv) 374 is_yuv = true; 375 376 if (dst_w > 3840) { 377 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 378 return; 379 } 380 381 if (!win->phy->scl->ext) { 382 VOP_SCL_SET(vop, win, scale_yrgb_x, 383 scl_cal_scale2(src_w, dst_w)); 384 VOP_SCL_SET(vop, win, scale_yrgb_y, 385 scl_cal_scale2(src_h, dst_h)); 386 if (is_yuv) { 387 VOP_SCL_SET(vop, win, scale_cbcr_x, 388 scl_cal_scale2(cbcr_src_w, dst_w)); 389 VOP_SCL_SET(vop, win, scale_cbcr_y, 390 scl_cal_scale2(cbcr_src_h, dst_h)); 391 } 392 return; 393 } 394 395 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 396 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 397 398 if (is_yuv) { 399 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 400 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 401 if (cbcr_hor_scl_mode == SCALE_DOWN) 402 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 403 else 404 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 405 } else { 406 if (yrgb_hor_scl_mode == SCALE_DOWN) 407 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 408 else 409 lb_mode = scl_vop_cal_lb_mode(src_w, false); 410 } 411 412 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 413 if (lb_mode == LB_RGB_3840X2) { 414 if (yrgb_ver_scl_mode != SCALE_NONE) { 415 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 416 return; 417 } 418 if (cbcr_ver_scl_mode != SCALE_NONE) { 419 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 420 return; 421 } 422 vsu_mode = SCALE_UP_BIL; 423 } else if (lb_mode == LB_RGB_2560X4) { 424 vsu_mode = SCALE_UP_BIL; 425 } else { 426 vsu_mode = SCALE_UP_BIC; 427 } 428 429 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 430 true, 0, NULL); 431 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 432 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 433 false, vsu_mode, &vskiplines); 434 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 435 436 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 437 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 438 439 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 440 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 441 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 442 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 443 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 444 if (is_yuv) { 445 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 446 dst_w, true, 0, NULL); 447 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 448 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 449 dst_h, false, vsu_mode, &vskiplines); 450 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 451 452 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 453 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 454 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 455 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 456 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 457 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 458 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 459 } 460 } 461 462 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 463 { 464 unsigned long flags; 465 466 if (WARN_ON(!vop->is_enabled)) 467 return; 468 469 spin_lock_irqsave(&vop->irq_lock, flags); 470 471 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 472 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 473 474 spin_unlock_irqrestore(&vop->irq_lock, flags); 475 } 476 477 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 478 { 479 unsigned long flags; 480 481 if (WARN_ON(!vop->is_enabled)) 482 return; 483 484 spin_lock_irqsave(&vop->irq_lock, flags); 485 486 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 487 488 spin_unlock_irqrestore(&vop->irq_lock, flags); 489 } 490 491 /* 492 * (1) each frame starts at the start of the Vsync pulse which is signaled by 493 * the "FRAME_SYNC" interrupt. 494 * (2) the active data region of each frame ends at dsp_vact_end 495 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 496 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 497 * 498 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 499 * Interrupts 500 * LINE_FLAG -------------------------------+ 501 * FRAME_SYNC ----+ | 502 * | | 503 * v v 504 * | Vsync | Vbp | Vactive | Vfp | 505 * ^ ^ ^ ^ 506 * | | | | 507 * | | | | 508 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 509 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 510 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 511 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 512 */ 513 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 514 { 515 uint32_t line_flag_irq; 516 unsigned long flags; 517 518 spin_lock_irqsave(&vop->irq_lock, flags); 519 520 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 521 522 spin_unlock_irqrestore(&vop->irq_lock, flags); 523 524 return !!line_flag_irq; 525 } 526 527 static void vop_line_flag_irq_enable(struct vop *vop) 528 { 529 unsigned long flags; 530 531 if (WARN_ON(!vop->is_enabled)) 532 return; 533 534 spin_lock_irqsave(&vop->irq_lock, flags); 535 536 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 537 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 538 539 spin_unlock_irqrestore(&vop->irq_lock, flags); 540 } 541 542 static void vop_line_flag_irq_disable(struct vop *vop) 543 { 544 unsigned long flags; 545 546 if (WARN_ON(!vop->is_enabled)) 547 return; 548 549 spin_lock_irqsave(&vop->irq_lock, flags); 550 551 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 552 553 spin_unlock_irqrestore(&vop->irq_lock, flags); 554 } 555 556 static int vop_core_clks_enable(struct vop *vop) 557 { 558 int ret; 559 560 ret = clk_enable(vop->hclk); 561 if (ret < 0) 562 return ret; 563 564 ret = clk_enable(vop->aclk); 565 if (ret < 0) 566 goto err_disable_hclk; 567 568 return 0; 569 570 err_disable_hclk: 571 clk_disable(vop->hclk); 572 return ret; 573 } 574 575 static void vop_core_clks_disable(struct vop *vop) 576 { 577 clk_disable(vop->aclk); 578 clk_disable(vop->hclk); 579 } 580 581 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 582 { 583 const struct vop_win_data *win = vop_win->data; 584 585 if (win->phy->scl && win->phy->scl->ext) { 586 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 587 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 588 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 589 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 590 } 591 592 VOP_WIN_SET(vop, win, enable, 0); 593 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 594 } 595 596 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 597 { 598 struct vop *vop = to_vop(crtc); 599 int ret, i; 600 601 ret = pm_runtime_resume_and_get(vop->dev); 602 if (ret < 0) { 603 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 604 return ret; 605 } 606 607 ret = vop_core_clks_enable(vop); 608 if (WARN_ON(ret < 0)) 609 goto err_put_pm_runtime; 610 611 ret = clk_enable(vop->dclk); 612 if (WARN_ON(ret < 0)) 613 goto err_disable_core; 614 615 /* 616 * Slave iommu shares power, irq and clock with vop. It was associated 617 * automatically with this master device via common driver code. 618 * Now that we have enabled the clock we attach it to the shared drm 619 * mapping. 620 */ 621 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 622 if (ret) { 623 DRM_DEV_ERROR(vop->dev, 624 "failed to attach dma mapping, %d\n", ret); 625 goto err_disable_dclk; 626 } 627 628 spin_lock(&vop->reg_lock); 629 for (i = 0; i < vop->len; i += 4) 630 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 631 632 /* 633 * We need to make sure that all windows are disabled before we 634 * enable the crtc. Otherwise we might try to scan from a destroyed 635 * buffer later. 636 * 637 * In the case of enable-after-PSR, we don't need to worry about this 638 * case since the buffer is guaranteed to be valid and disabling the 639 * window will result in screen glitches on PSR exit. 640 */ 641 if (!old_state || !old_state->self_refresh_active) { 642 for (i = 0; i < vop->data->win_size; i++) { 643 struct vop_win *vop_win = &vop->win[i]; 644 645 vop_win_disable(vop, vop_win); 646 } 647 } 648 649 if (vop->data->afbc) { 650 struct rockchip_crtc_state *s; 651 /* 652 * Disable AFBC and forget there was a vop window with AFBC 653 */ 654 VOP_AFBC_SET(vop, enable, 0); 655 s = to_rockchip_crtc_state(crtc->state); 656 s->enable_afbc = false; 657 } 658 659 vop_cfg_done(vop); 660 661 spin_unlock(&vop->reg_lock); 662 663 /* 664 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 665 */ 666 vop->is_enabled = true; 667 668 spin_lock(&vop->reg_lock); 669 670 VOP_REG_SET(vop, common, standby, 1); 671 672 spin_unlock(&vop->reg_lock); 673 674 drm_crtc_vblank_on(crtc); 675 676 return 0; 677 678 err_disable_dclk: 679 clk_disable(vop->dclk); 680 err_disable_core: 681 vop_core_clks_disable(vop); 682 err_put_pm_runtime: 683 pm_runtime_put_sync(vop->dev); 684 return ret; 685 } 686 687 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 688 { 689 struct vop *vop = to_vop(crtc); 690 int i; 691 692 spin_lock(&vop->reg_lock); 693 694 for (i = 0; i < vop->data->win_size; i++) { 695 struct vop_win *vop_win = &vop->win[i]; 696 const struct vop_win_data *win = vop_win->data; 697 698 VOP_WIN_SET(vop, win, enable, 699 enabled && (vop->win_enabled & BIT(i))); 700 } 701 vop_cfg_done(vop); 702 703 spin_unlock(&vop->reg_lock); 704 } 705 706 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 707 struct drm_atomic_state *state) 708 { 709 struct vop *vop = to_vop(crtc); 710 711 WARN_ON(vop->event); 712 713 if (crtc->state->self_refresh_active) 714 rockchip_drm_set_win_enabled(crtc, false); 715 716 if (crtc->state->self_refresh_active) 717 goto out; 718 719 mutex_lock(&vop->vop_lock); 720 721 drm_crtc_vblank_off(crtc); 722 723 /* 724 * Vop standby will take effect at end of current frame, 725 * if dsp hold valid irq happen, it means standby complete. 726 * 727 * we must wait standby complete when we want to disable aclk, 728 * if not, memory bus maybe dead. 729 */ 730 reinit_completion(&vop->dsp_hold_completion); 731 vop_dsp_hold_valid_irq_enable(vop); 732 733 spin_lock(&vop->reg_lock); 734 735 VOP_REG_SET(vop, common, standby, 1); 736 737 spin_unlock(&vop->reg_lock); 738 739 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 740 msecs_to_jiffies(200))) 741 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 742 743 vop_dsp_hold_valid_irq_disable(vop); 744 745 vop->is_enabled = false; 746 747 /* 748 * vop standby complete, so iommu detach is safe. 749 */ 750 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 751 752 clk_disable(vop->dclk); 753 vop_core_clks_disable(vop); 754 pm_runtime_put(vop->dev); 755 756 mutex_unlock(&vop->vop_lock); 757 758 out: 759 if (crtc->state->event && !crtc->state->active) { 760 spin_lock_irq(&crtc->dev->event_lock); 761 drm_crtc_send_vblank_event(crtc, crtc->state->event); 762 spin_unlock_irq(&crtc->dev->event_lock); 763 764 crtc->state->event = NULL; 765 } 766 } 767 768 static void vop_plane_destroy(struct drm_plane *plane) 769 { 770 drm_plane_cleanup(plane); 771 } 772 773 static inline bool rockchip_afbc(u64 modifier) 774 { 775 return modifier == ROCKCHIP_AFBC_MOD; 776 } 777 778 static bool rockchip_mod_supported(struct drm_plane *plane, 779 u32 format, u64 modifier) 780 { 781 if (modifier == DRM_FORMAT_MOD_LINEAR) 782 return true; 783 784 if (!rockchip_afbc(modifier)) { 785 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 786 787 return false; 788 } 789 790 return vop_convert_afbc_format(format) >= 0; 791 } 792 793 static int vop_plane_atomic_check(struct drm_plane *plane, 794 struct drm_atomic_state *state) 795 { 796 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 797 plane); 798 struct drm_crtc *crtc = new_plane_state->crtc; 799 struct drm_crtc_state *crtc_state; 800 struct drm_framebuffer *fb = new_plane_state->fb; 801 struct vop_win *vop_win = to_vop_win(plane); 802 const struct vop_win_data *win = vop_win->data; 803 int ret; 804 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 805 DRM_PLANE_NO_SCALING; 806 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 807 DRM_PLANE_NO_SCALING; 808 809 if (!crtc || WARN_ON(!fb)) 810 return 0; 811 812 crtc_state = drm_atomic_get_existing_crtc_state(state, 813 crtc); 814 if (WARN_ON(!crtc_state)) 815 return -EINVAL; 816 817 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 818 min_scale, max_scale, 819 true, true); 820 if (ret) 821 return ret; 822 823 if (!new_plane_state->visible) 824 return 0; 825 826 ret = vop_convert_format(fb->format->format); 827 if (ret < 0) 828 return ret; 829 830 /* 831 * Src.x1 can be odd when do clip, but yuv plane start point 832 * need align with 2 pixel. 833 */ 834 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 835 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 836 return -EINVAL; 837 } 838 839 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 840 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 841 return -EINVAL; 842 } 843 844 if (rockchip_afbc(fb->modifier)) { 845 struct vop *vop = to_vop(crtc); 846 847 if (!vop->data->afbc) { 848 DRM_ERROR("vop does not support AFBC\n"); 849 return -EINVAL; 850 } 851 852 ret = vop_convert_afbc_format(fb->format->format); 853 if (ret < 0) 854 return ret; 855 856 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 857 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", 858 new_plane_state->src.x1, 859 new_plane_state->src.y1, fb->offsets[0]); 860 return -EINVAL; 861 } 862 863 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 864 DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 865 new_plane_state->rotation); 866 return -EINVAL; 867 } 868 } 869 870 return 0; 871 } 872 873 static void vop_plane_atomic_disable(struct drm_plane *plane, 874 struct drm_atomic_state *state) 875 { 876 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 877 plane); 878 struct vop_win *vop_win = to_vop_win(plane); 879 struct vop *vop = to_vop(old_state->crtc); 880 881 if (!old_state->crtc) 882 return; 883 884 spin_lock(&vop->reg_lock); 885 886 vop_win_disable(vop, vop_win); 887 888 spin_unlock(&vop->reg_lock); 889 } 890 891 static void vop_plane_atomic_update(struct drm_plane *plane, 892 struct drm_atomic_state *state) 893 { 894 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 895 plane); 896 struct drm_crtc *crtc = new_state->crtc; 897 struct vop_win *vop_win = to_vop_win(plane); 898 const struct vop_win_data *win = vop_win->data; 899 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 900 struct vop *vop = to_vop(new_state->crtc); 901 struct drm_framebuffer *fb = new_state->fb; 902 unsigned int actual_w, actual_h; 903 unsigned int dsp_stx, dsp_sty; 904 uint32_t act_info, dsp_info, dsp_st; 905 struct drm_rect *src = &new_state->src; 906 struct drm_rect *dest = &new_state->dst; 907 struct drm_gem_object *obj, *uv_obj; 908 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 909 unsigned long offset; 910 dma_addr_t dma_addr; 911 uint32_t val; 912 bool rb_swap, uv_swap; 913 int win_index = VOP_WIN_TO_INDEX(vop_win); 914 int format; 915 int is_yuv = fb->format->is_yuv; 916 int i; 917 918 /* 919 * can't update plane when vop is disabled. 920 */ 921 if (WARN_ON(!crtc)) 922 return; 923 924 if (WARN_ON(!vop->is_enabled)) 925 return; 926 927 if (!new_state->visible) { 928 vop_plane_atomic_disable(plane, state); 929 return; 930 } 931 932 obj = fb->obj[0]; 933 rk_obj = to_rockchip_obj(obj); 934 935 actual_w = drm_rect_width(src) >> 16; 936 actual_h = drm_rect_height(src) >> 16; 937 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 938 939 dsp_info = (drm_rect_height(dest) - 1) << 16; 940 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 941 942 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 943 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 944 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 945 946 offset = (src->x1 >> 16) * fb->format->cpp[0]; 947 offset += (src->y1 >> 16) * fb->pitches[0]; 948 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 949 950 /* 951 * For y-mirroring we need to move address 952 * to the beginning of the last line. 953 */ 954 if (new_state->rotation & DRM_MODE_REFLECT_Y) 955 dma_addr += (actual_h - 1) * fb->pitches[0]; 956 957 format = vop_convert_format(fb->format->format); 958 959 spin_lock(&vop->reg_lock); 960 961 if (rockchip_afbc(fb->modifier)) { 962 int afbc_format = vop_convert_afbc_format(fb->format->format); 963 964 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 965 VOP_AFBC_SET(vop, hreg_block_split, 0); 966 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 967 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 968 VOP_AFBC_SET(vop, pic_size, act_info); 969 } 970 971 VOP_WIN_SET(vop, win, format, format); 972 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 973 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 974 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 975 VOP_WIN_SET(vop, win, y_mir_en, 976 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 977 VOP_WIN_SET(vop, win, x_mir_en, 978 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 979 980 if (is_yuv) { 981 int hsub = fb->format->hsub; 982 int vsub = fb->format->vsub; 983 int bpp = fb->format->cpp[1]; 984 985 uv_obj = fb->obj[1]; 986 rk_uv_obj = to_rockchip_obj(uv_obj); 987 988 offset = (src->x1 >> 16) * bpp / hsub; 989 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 990 991 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 992 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 993 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 994 995 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 996 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 997 win_yuv2yuv, 998 y2r_coefficients[i], 999 bt601_yuv2rgb[i]); 1000 } 1001 1002 uv_swap = has_uv_swapped(fb->format->format); 1003 VOP_WIN_SET(vop, win, uv_swap, uv_swap); 1004 } 1005 1006 if (win->phy->scl) 1007 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 1008 drm_rect_width(dest), drm_rect_height(dest), 1009 fb->format); 1010 1011 VOP_WIN_SET(vop, win, act_info, act_info); 1012 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1013 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1014 1015 rb_swap = has_rb_swapped(fb->format->format); 1016 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1017 1018 /* 1019 * Blending win0 with the background color doesn't seem to work 1020 * correctly. We only get the background color, no matter the contents 1021 * of the win0 framebuffer. However, blending pre-multiplied color 1022 * with the default opaque black default background color is a no-op, 1023 * so we can just disable blending to get the correct result. 1024 */ 1025 if (fb->format->has_alpha && win_index > 0) { 1026 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1027 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1028 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1029 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1030 SRC_BLEND_M0(ALPHA_PER_PIX) | 1031 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1032 SRC_FACTOR_M0(ALPHA_ONE); 1033 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1034 1035 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1036 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1037 VOP_WIN_SET(vop, win, alpha_en, 1); 1038 } else { 1039 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1040 VOP_WIN_SET(vop, win, alpha_en, 0); 1041 } 1042 1043 VOP_WIN_SET(vop, win, enable, 1); 1044 vop->win_enabled |= BIT(win_index); 1045 spin_unlock(&vop->reg_lock); 1046 } 1047 1048 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1049 struct drm_atomic_state *state) 1050 { 1051 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1052 plane); 1053 struct vop_win *vop_win = to_vop_win(plane); 1054 const struct vop_win_data *win = vop_win->data; 1055 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1056 DRM_PLANE_NO_SCALING; 1057 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1058 DRM_PLANE_NO_SCALING; 1059 struct drm_crtc_state *crtc_state; 1060 1061 if (plane != new_plane_state->crtc->cursor) 1062 return -EINVAL; 1063 1064 if (!plane->state) 1065 return -EINVAL; 1066 1067 if (!plane->state->fb) 1068 return -EINVAL; 1069 1070 if (state) 1071 crtc_state = drm_atomic_get_existing_crtc_state(state, 1072 new_plane_state->crtc); 1073 else /* Special case for asynchronous cursor updates. */ 1074 crtc_state = plane->crtc->state; 1075 1076 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1077 min_scale, max_scale, 1078 true, true); 1079 } 1080 1081 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1082 struct drm_atomic_state *state) 1083 { 1084 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1085 plane); 1086 struct vop *vop = to_vop(plane->state->crtc); 1087 struct drm_framebuffer *old_fb = plane->state->fb; 1088 1089 plane->state->crtc_x = new_state->crtc_x; 1090 plane->state->crtc_y = new_state->crtc_y; 1091 plane->state->crtc_h = new_state->crtc_h; 1092 plane->state->crtc_w = new_state->crtc_w; 1093 plane->state->src_x = new_state->src_x; 1094 plane->state->src_y = new_state->src_y; 1095 plane->state->src_h = new_state->src_h; 1096 plane->state->src_w = new_state->src_w; 1097 swap(plane->state->fb, new_state->fb); 1098 1099 if (vop->is_enabled) { 1100 vop_plane_atomic_update(plane, state); 1101 spin_lock(&vop->reg_lock); 1102 vop_cfg_done(vop); 1103 spin_unlock(&vop->reg_lock); 1104 1105 /* 1106 * A scanout can still be occurring, so we can't drop the 1107 * reference to the old framebuffer. To solve this we get a 1108 * reference to old_fb and set a worker to release it later. 1109 * FIXME: if we perform 500 async_update calls before the 1110 * vblank, then we can have 500 different framebuffers waiting 1111 * to be released. 1112 */ 1113 if (old_fb && plane->state->fb != old_fb) { 1114 drm_framebuffer_get(old_fb); 1115 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1116 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1117 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1118 } 1119 } 1120 } 1121 1122 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1123 .atomic_check = vop_plane_atomic_check, 1124 .atomic_update = vop_plane_atomic_update, 1125 .atomic_disable = vop_plane_atomic_disable, 1126 .atomic_async_check = vop_plane_atomic_async_check, 1127 .atomic_async_update = vop_plane_atomic_async_update, 1128 }; 1129 1130 static const struct drm_plane_funcs vop_plane_funcs = { 1131 .update_plane = drm_atomic_helper_update_plane, 1132 .disable_plane = drm_atomic_helper_disable_plane, 1133 .destroy = vop_plane_destroy, 1134 .reset = drm_atomic_helper_plane_reset, 1135 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1136 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1137 .format_mod_supported = rockchip_mod_supported, 1138 }; 1139 1140 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1141 { 1142 struct vop *vop = to_vop(crtc); 1143 unsigned long flags; 1144 1145 if (WARN_ON(!vop->is_enabled)) 1146 return -EPERM; 1147 1148 spin_lock_irqsave(&vop->irq_lock, flags); 1149 1150 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1151 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1152 1153 spin_unlock_irqrestore(&vop->irq_lock, flags); 1154 1155 return 0; 1156 } 1157 1158 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1159 { 1160 struct vop *vop = to_vop(crtc); 1161 unsigned long flags; 1162 1163 if (WARN_ON(!vop->is_enabled)) 1164 return; 1165 1166 spin_lock_irqsave(&vop->irq_lock, flags); 1167 1168 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1169 1170 spin_unlock_irqrestore(&vop->irq_lock, flags); 1171 } 1172 1173 static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, 1174 const struct drm_display_mode *mode) 1175 { 1176 struct vop *vop = to_vop(crtc); 1177 1178 if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width) 1179 return MODE_BAD_HVALUE; 1180 1181 return MODE_OK; 1182 } 1183 1184 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1185 const struct drm_display_mode *mode, 1186 struct drm_display_mode *adjusted_mode) 1187 { 1188 struct vop *vop = to_vop(crtc); 1189 unsigned long rate; 1190 1191 /* 1192 * Clock craziness. 1193 * 1194 * Key points: 1195 * 1196 * - DRM works in kHz. 1197 * - Clock framework works in Hz. 1198 * - Rockchip's clock driver picks the clock rate that is the 1199 * same _OR LOWER_ than the one requested. 1200 * 1201 * Action plan: 1202 * 1203 * 1. Try to set the exact rate first, and confirm the clock framework 1204 * can provide it. 1205 * 1206 * 2. If the clock framework cannot provide the exact rate, we should 1207 * add 999 Hz to the requested rate. That way if the clock we need 1208 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 1209 * the clock framework will actually give us the right clock. 1210 * 1211 * 3. Get the clock framework to round the rate for us to tell us 1212 * what it will actually make. 1213 * 1214 * 4. Store the rounded up rate so that we don't need to worry about 1215 * this in the actual clk_set_rate(). 1216 */ 1217 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 1218 if (rate / 1000 != adjusted_mode->clock) 1219 rate = clk_round_rate(vop->dclk, 1220 adjusted_mode->clock * 1000 + 999); 1221 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1222 1223 return true; 1224 } 1225 1226 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1227 { 1228 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1229 } 1230 1231 static u32 vop_lut_buffer_index(struct vop *vop) 1232 { 1233 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); 1234 } 1235 1236 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1237 { 1238 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1239 unsigned int i, bpc = ilog2(vop->data->lut_size); 1240 1241 for (i = 0; i < crtc->gamma_size; i++) { 1242 u32 word; 1243 1244 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | 1245 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1246 drm_color_lut_extract(lut[i].blue, bpc); 1247 writel(word, vop->lut_regs + i * 4); 1248 } 1249 } 1250 1251 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1252 struct drm_crtc_state *old_state) 1253 { 1254 struct drm_crtc_state *state = crtc->state; 1255 unsigned int idle; 1256 u32 lut_idx, old_idx; 1257 int ret; 1258 1259 if (!vop->lut_regs) 1260 return; 1261 1262 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { 1263 /* 1264 * To disable gamma (gamma_lut is null) or to write 1265 * an update to the LUT, clear dsp_lut_en. 1266 */ 1267 spin_lock(&vop->reg_lock); 1268 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1269 vop_cfg_done(vop); 1270 spin_unlock(&vop->reg_lock); 1271 1272 /* 1273 * In order to write the LUT to the internal memory, 1274 * we need to first make sure the dsp_lut_en bit is cleared. 1275 */ 1276 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1277 idle, !idle, 5, 30 * 1000); 1278 if (ret) { 1279 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1280 return; 1281 } 1282 1283 if (!state->gamma_lut) 1284 return; 1285 } else { 1286 /* 1287 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, 1288 * by setting update_gamma_lut then waiting for lut_buffer_index change 1289 */ 1290 old_idx = vop_lut_buffer_index(vop); 1291 } 1292 1293 spin_lock(&vop->reg_lock); 1294 vop_crtc_write_gamma_lut(vop, crtc); 1295 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1296 VOP_REG_SET(vop, common, update_gamma_lut, 1); 1297 vop_cfg_done(vop); 1298 spin_unlock(&vop->reg_lock); 1299 1300 if (VOP_HAS_REG(vop, common, update_gamma_lut)) { 1301 ret = readx_poll_timeout(vop_lut_buffer_index, vop, 1302 lut_idx, lut_idx != old_idx, 5, 30 * 1000); 1303 if (ret) { 1304 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); 1305 return; 1306 } 1307 1308 /* 1309 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit 1310 * in our backup of the regs. 1311 */ 1312 spin_lock(&vop->reg_lock); 1313 VOP_REG_SET(vop, common, update_gamma_lut, 0); 1314 spin_unlock(&vop->reg_lock); 1315 } 1316 } 1317 1318 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1319 struct drm_atomic_state *state) 1320 { 1321 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1322 crtc); 1323 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1324 crtc); 1325 struct vop *vop = to_vop(crtc); 1326 1327 /* 1328 * Only update GAMMA if the 'active' flag is not changed, 1329 * otherwise it's updated by .atomic_enable. 1330 */ 1331 if (crtc_state->color_mgmt_changed && 1332 !crtc_state->active_changed) 1333 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1334 } 1335 1336 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1337 struct drm_atomic_state *state) 1338 { 1339 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1340 crtc); 1341 struct vop *vop = to_vop(crtc); 1342 const struct vop_data *vop_data = vop->data; 1343 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1344 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1345 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1346 u16 hdisplay = adjusted_mode->hdisplay; 1347 u16 htotal = adjusted_mode->htotal; 1348 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1349 u16 hact_end = hact_st + hdisplay; 1350 u16 vdisplay = adjusted_mode->vdisplay; 1351 u16 vtotal = adjusted_mode->vtotal; 1352 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1353 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1354 u16 vact_end = vact_st + vdisplay; 1355 uint32_t pin_pol, val; 1356 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1357 int ret; 1358 1359 if (old_state && old_state->self_refresh_active) { 1360 drm_crtc_vblank_on(crtc); 1361 rockchip_drm_set_win_enabled(crtc, true); 1362 return; 1363 } 1364 1365 mutex_lock(&vop->vop_lock); 1366 1367 WARN_ON(vop->event); 1368 1369 ret = vop_enable(crtc, old_state); 1370 if (ret) { 1371 mutex_unlock(&vop->vop_lock); 1372 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1373 return; 1374 } 1375 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1376 BIT(HSYNC_POSITIVE) : 0; 1377 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1378 BIT(VSYNC_POSITIVE) : 0; 1379 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1380 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1381 1382 switch (s->output_type) { 1383 case DRM_MODE_CONNECTOR_LVDS: 1384 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1385 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1386 VOP_REG_SET(vop, output, rgb_en, 1); 1387 break; 1388 case DRM_MODE_CONNECTOR_eDP: 1389 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1390 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1391 VOP_REG_SET(vop, output, edp_en, 1); 1392 break; 1393 case DRM_MODE_CONNECTOR_HDMIA: 1394 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1395 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1396 VOP_REG_SET(vop, output, hdmi_en, 1); 1397 break; 1398 case DRM_MODE_CONNECTOR_DSI: 1399 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1400 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1401 VOP_REG_SET(vop, output, mipi_en, 1); 1402 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1403 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1404 break; 1405 case DRM_MODE_CONNECTOR_DisplayPort: 1406 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1407 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1408 VOP_REG_SET(vop, output, dp_en, 1); 1409 break; 1410 default: 1411 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1412 s->output_type); 1413 } 1414 1415 /* 1416 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1417 */ 1418 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1419 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1420 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1421 1422 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1423 VOP_REG_SET(vop, common, pre_dither_down, 1); 1424 else 1425 VOP_REG_SET(vop, common, pre_dither_down, 0); 1426 1427 if (dither_bpc == 6) { 1428 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1429 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1430 VOP_REG_SET(vop, common, dither_down_en, 1); 1431 } else { 1432 VOP_REG_SET(vop, common, dither_down_en, 0); 1433 } 1434 1435 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1436 1437 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1438 val = hact_st << 16; 1439 val |= hact_end; 1440 VOP_REG_SET(vop, modeset, hact_st_end, val); 1441 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1442 1443 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1444 val = vact_st << 16; 1445 val |= vact_end; 1446 VOP_REG_SET(vop, modeset, vact_st_end, val); 1447 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1448 1449 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1450 1451 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1452 1453 VOP_REG_SET(vop, common, standby, 0); 1454 mutex_unlock(&vop->vop_lock); 1455 1456 /* 1457 * If we have a GAMMA LUT in the state, then let's make sure 1458 * it's updated. We might be coming out of suspend, 1459 * which means the LUT internal memory needs to be re-written. 1460 */ 1461 if (crtc->state->gamma_lut) 1462 vop_crtc_gamma_set(vop, crtc, old_state); 1463 } 1464 1465 static bool vop_fs_irq_is_pending(struct vop *vop) 1466 { 1467 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1468 } 1469 1470 static void vop_wait_for_irq_handler(struct vop *vop) 1471 { 1472 bool pending; 1473 int ret; 1474 1475 /* 1476 * Spin until frame start interrupt status bit goes low, which means 1477 * that interrupt handler was invoked and cleared it. The timeout of 1478 * 10 msecs is really too long, but it is just a safety measure if 1479 * something goes really wrong. The wait will only happen in the very 1480 * unlikely case of a vblank happening exactly at the same time and 1481 * shouldn't exceed microseconds range. 1482 */ 1483 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1484 !pending, 0, 10 * 1000); 1485 if (ret) 1486 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1487 1488 synchronize_irq(vop->irq); 1489 } 1490 1491 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1492 struct drm_atomic_state *state) 1493 { 1494 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1495 crtc); 1496 struct vop *vop = to_vop(crtc); 1497 struct drm_plane *plane; 1498 struct drm_plane_state *plane_state; 1499 struct rockchip_crtc_state *s; 1500 int afbc_planes = 0; 1501 1502 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1503 crtc_state->gamma_lut) { 1504 unsigned int len; 1505 1506 len = drm_color_lut_size(crtc_state->gamma_lut); 1507 if (len != crtc->gamma_size) { 1508 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1509 len, crtc->gamma_size); 1510 return -EINVAL; 1511 } 1512 } 1513 1514 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1515 plane_state = 1516 drm_atomic_get_plane_state(crtc_state->state, plane); 1517 if (IS_ERR(plane_state)) { 1518 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1519 plane->name); 1520 return PTR_ERR(plane_state); 1521 } 1522 1523 if (drm_is_afbc(plane_state->fb->modifier)) 1524 ++afbc_planes; 1525 } 1526 1527 if (afbc_planes > 1) { 1528 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1529 return -EINVAL; 1530 } 1531 1532 s = to_rockchip_crtc_state(crtc_state); 1533 s->enable_afbc = afbc_planes > 0; 1534 1535 return 0; 1536 } 1537 1538 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1539 struct drm_atomic_state *state) 1540 { 1541 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1542 crtc); 1543 struct drm_atomic_state *old_state = old_crtc_state->state; 1544 struct drm_plane_state *old_plane_state, *new_plane_state; 1545 struct vop *vop = to_vop(crtc); 1546 struct drm_plane *plane; 1547 struct rockchip_crtc_state *s; 1548 int i; 1549 1550 if (WARN_ON(!vop->is_enabled)) 1551 return; 1552 1553 spin_lock(&vop->reg_lock); 1554 1555 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1556 s = to_rockchip_crtc_state(crtc->state); 1557 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1558 vop_cfg_done(vop); 1559 1560 spin_unlock(&vop->reg_lock); 1561 1562 /* 1563 * There is a (rather unlikely) possiblity that a vblank interrupt 1564 * fired before we set the cfg_done bit. To avoid spuriously 1565 * signalling flip completion we need to wait for it to finish. 1566 */ 1567 vop_wait_for_irq_handler(vop); 1568 1569 spin_lock_irq(&crtc->dev->event_lock); 1570 if (crtc->state->event) { 1571 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1572 WARN_ON(vop->event); 1573 1574 vop->event = crtc->state->event; 1575 crtc->state->event = NULL; 1576 } 1577 spin_unlock_irq(&crtc->dev->event_lock); 1578 1579 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1580 new_plane_state, i) { 1581 if (!old_plane_state->fb) 1582 continue; 1583 1584 if (old_plane_state->fb == new_plane_state->fb) 1585 continue; 1586 1587 drm_framebuffer_get(old_plane_state->fb); 1588 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1589 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1590 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1591 } 1592 } 1593 1594 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1595 .mode_valid = vop_crtc_mode_valid, 1596 .mode_fixup = vop_crtc_mode_fixup, 1597 .atomic_check = vop_crtc_atomic_check, 1598 .atomic_begin = vop_crtc_atomic_begin, 1599 .atomic_flush = vop_crtc_atomic_flush, 1600 .atomic_enable = vop_crtc_atomic_enable, 1601 .atomic_disable = vop_crtc_atomic_disable, 1602 }; 1603 1604 static void vop_crtc_destroy(struct drm_crtc *crtc) 1605 { 1606 drm_crtc_cleanup(crtc); 1607 } 1608 1609 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1610 { 1611 struct rockchip_crtc_state *rockchip_state; 1612 1613 if (WARN_ON(!crtc->state)) 1614 return NULL; 1615 1616 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1617 if (!rockchip_state) 1618 return NULL; 1619 1620 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1621 return &rockchip_state->base; 1622 } 1623 1624 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1625 struct drm_crtc_state *state) 1626 { 1627 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1628 1629 __drm_atomic_helper_crtc_destroy_state(&s->base); 1630 kfree(s); 1631 } 1632 1633 static void vop_crtc_reset(struct drm_crtc *crtc) 1634 { 1635 struct rockchip_crtc_state *crtc_state = 1636 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1637 1638 if (crtc->state) 1639 vop_crtc_destroy_state(crtc, crtc->state); 1640 1641 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1642 } 1643 1644 #ifdef CONFIG_DRM_ANALOGIX_DP 1645 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1646 { 1647 struct drm_connector *connector; 1648 struct drm_connector_list_iter conn_iter; 1649 1650 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1651 drm_for_each_connector_iter(connector, &conn_iter) { 1652 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1653 drm_connector_list_iter_end(&conn_iter); 1654 return connector; 1655 } 1656 } 1657 drm_connector_list_iter_end(&conn_iter); 1658 1659 return NULL; 1660 } 1661 1662 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1663 const char *source_name) 1664 { 1665 struct vop *vop = to_vop(crtc); 1666 struct drm_connector *connector; 1667 int ret; 1668 1669 connector = vop_get_edp_connector(vop); 1670 if (!connector) 1671 return -EINVAL; 1672 1673 if (source_name && strcmp(source_name, "auto") == 0) 1674 ret = analogix_dp_start_crc(connector); 1675 else if (!source_name) 1676 ret = analogix_dp_stop_crc(connector); 1677 else 1678 ret = -EINVAL; 1679 1680 return ret; 1681 } 1682 1683 static int 1684 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1685 size_t *values_cnt) 1686 { 1687 if (source_name && strcmp(source_name, "auto") != 0) 1688 return -EINVAL; 1689 1690 *values_cnt = 3; 1691 return 0; 1692 } 1693 1694 #else 1695 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1696 const char *source_name) 1697 { 1698 return -ENODEV; 1699 } 1700 1701 static int 1702 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1703 size_t *values_cnt) 1704 { 1705 return -ENODEV; 1706 } 1707 #endif 1708 1709 static const struct drm_crtc_funcs vop_crtc_funcs = { 1710 .set_config = drm_atomic_helper_set_config, 1711 .page_flip = drm_atomic_helper_page_flip, 1712 .destroy = vop_crtc_destroy, 1713 .reset = vop_crtc_reset, 1714 .atomic_duplicate_state = vop_crtc_duplicate_state, 1715 .atomic_destroy_state = vop_crtc_destroy_state, 1716 .enable_vblank = vop_crtc_enable_vblank, 1717 .disable_vblank = vop_crtc_disable_vblank, 1718 .set_crc_source = vop_crtc_set_crc_source, 1719 .verify_crc_source = vop_crtc_verify_crc_source, 1720 }; 1721 1722 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1723 { 1724 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1725 struct drm_framebuffer *fb = val; 1726 1727 drm_crtc_vblank_put(&vop->crtc); 1728 drm_framebuffer_put(fb); 1729 } 1730 1731 static void vop_handle_vblank(struct vop *vop) 1732 { 1733 struct drm_device *drm = vop->drm_dev; 1734 struct drm_crtc *crtc = &vop->crtc; 1735 1736 spin_lock(&drm->event_lock); 1737 if (vop->event) { 1738 drm_crtc_send_vblank_event(crtc, vop->event); 1739 drm_crtc_vblank_put(crtc); 1740 vop->event = NULL; 1741 } 1742 spin_unlock(&drm->event_lock); 1743 1744 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1745 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1746 } 1747 1748 static irqreturn_t vop_isr(int irq, void *data) 1749 { 1750 struct vop *vop = data; 1751 struct drm_crtc *crtc = &vop->crtc; 1752 uint32_t active_irqs; 1753 int ret = IRQ_NONE; 1754 1755 /* 1756 * The irq is shared with the iommu. If the runtime-pm state of the 1757 * vop-device is disabled the irq has to be targeted at the iommu. 1758 */ 1759 if (!pm_runtime_get_if_in_use(vop->dev)) 1760 return IRQ_NONE; 1761 1762 if (vop_core_clks_enable(vop)) { 1763 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1764 goto out; 1765 } 1766 1767 /* 1768 * interrupt register has interrupt status, enable and clear bits, we 1769 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1770 */ 1771 spin_lock(&vop->irq_lock); 1772 1773 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1774 /* Clear all active interrupt sources */ 1775 if (active_irqs) 1776 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1777 1778 spin_unlock(&vop->irq_lock); 1779 1780 /* This is expected for vop iommu irqs, since the irq is shared */ 1781 if (!active_irqs) 1782 goto out_disable; 1783 1784 if (active_irqs & DSP_HOLD_VALID_INTR) { 1785 complete(&vop->dsp_hold_completion); 1786 active_irqs &= ~DSP_HOLD_VALID_INTR; 1787 ret = IRQ_HANDLED; 1788 } 1789 1790 if (active_irqs & LINE_FLAG_INTR) { 1791 complete(&vop->line_flag_completion); 1792 active_irqs &= ~LINE_FLAG_INTR; 1793 ret = IRQ_HANDLED; 1794 } 1795 1796 if (active_irqs & FS_INTR) { 1797 drm_crtc_handle_vblank(crtc); 1798 vop_handle_vblank(vop); 1799 active_irqs &= ~FS_INTR; 1800 ret = IRQ_HANDLED; 1801 } 1802 1803 /* Unhandled irqs are spurious. */ 1804 if (active_irqs) 1805 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1806 active_irqs); 1807 1808 out_disable: 1809 vop_core_clks_disable(vop); 1810 out: 1811 pm_runtime_put(vop->dev); 1812 return ret; 1813 } 1814 1815 static void vop_plane_add_properties(struct drm_plane *plane, 1816 const struct vop_win_data *win_data) 1817 { 1818 unsigned int flags = 0; 1819 1820 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1821 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1822 if (flags) 1823 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1824 DRM_MODE_ROTATE_0 | flags); 1825 } 1826 1827 static int vop_create_crtc(struct vop *vop) 1828 { 1829 const struct vop_data *vop_data = vop->data; 1830 struct device *dev = vop->dev; 1831 struct drm_device *drm_dev = vop->drm_dev; 1832 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1833 struct drm_crtc *crtc = &vop->crtc; 1834 struct device_node *port; 1835 int ret; 1836 int i; 1837 1838 /* 1839 * Create drm_plane for primary and cursor planes first, since we need 1840 * to pass them to drm_crtc_init_with_planes, which sets the 1841 * "possible_crtcs" to the newly initialized crtc. 1842 */ 1843 for (i = 0; i < vop_data->win_size; i++) { 1844 struct vop_win *vop_win = &vop->win[i]; 1845 const struct vop_win_data *win_data = vop_win->data; 1846 1847 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1848 win_data->type != DRM_PLANE_TYPE_CURSOR) 1849 continue; 1850 1851 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1852 0, &vop_plane_funcs, 1853 win_data->phy->data_formats, 1854 win_data->phy->nformats, 1855 win_data->phy->format_modifiers, 1856 win_data->type, NULL); 1857 if (ret) { 1858 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1859 ret); 1860 goto err_cleanup_planes; 1861 } 1862 1863 plane = &vop_win->base; 1864 drm_plane_helper_add(plane, &plane_helper_funcs); 1865 vop_plane_add_properties(plane, win_data); 1866 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1867 primary = plane; 1868 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1869 cursor = plane; 1870 } 1871 1872 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1873 &vop_crtc_funcs, NULL); 1874 if (ret) 1875 goto err_cleanup_planes; 1876 1877 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1878 if (vop->lut_regs) { 1879 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1880 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1881 } 1882 1883 /* 1884 * Create drm_planes for overlay windows with possible_crtcs restricted 1885 * to the newly created crtc. 1886 */ 1887 for (i = 0; i < vop_data->win_size; i++) { 1888 struct vop_win *vop_win = &vop->win[i]; 1889 const struct vop_win_data *win_data = vop_win->data; 1890 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1891 1892 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1893 continue; 1894 1895 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1896 possible_crtcs, 1897 &vop_plane_funcs, 1898 win_data->phy->data_formats, 1899 win_data->phy->nformats, 1900 win_data->phy->format_modifiers, 1901 win_data->type, NULL); 1902 if (ret) { 1903 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1904 ret); 1905 goto err_cleanup_crtc; 1906 } 1907 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1908 vop_plane_add_properties(&vop_win->base, win_data); 1909 } 1910 1911 port = of_get_child_by_name(dev->of_node, "port"); 1912 if (!port) { 1913 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1914 dev->of_node); 1915 ret = -ENOENT; 1916 goto err_cleanup_crtc; 1917 } 1918 1919 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1920 vop_fb_unref_worker); 1921 1922 init_completion(&vop->dsp_hold_completion); 1923 init_completion(&vop->line_flag_completion); 1924 crtc->port = port; 1925 1926 ret = drm_self_refresh_helper_init(crtc); 1927 if (ret) 1928 DRM_DEV_DEBUG_KMS(vop->dev, 1929 "Failed to init %s with SR helpers %d, ignoring\n", 1930 crtc->name, ret); 1931 1932 return 0; 1933 1934 err_cleanup_crtc: 1935 drm_crtc_cleanup(crtc); 1936 err_cleanup_planes: 1937 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1938 head) 1939 drm_plane_cleanup(plane); 1940 return ret; 1941 } 1942 1943 static void vop_destroy_crtc(struct vop *vop) 1944 { 1945 struct drm_crtc *crtc = &vop->crtc; 1946 struct drm_device *drm_dev = vop->drm_dev; 1947 struct drm_plane *plane, *tmp; 1948 1949 drm_self_refresh_helper_cleanup(crtc); 1950 1951 of_node_put(crtc->port); 1952 1953 /* 1954 * We need to cleanup the planes now. Why? 1955 * 1956 * The planes are "&vop->win[i].base". That means the memory is 1957 * all part of the big "struct vop" chunk of memory. That memory 1958 * was devm allocated and associated with this component. We need to 1959 * free it ourselves before vop_unbind() finishes. 1960 */ 1961 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1962 head) 1963 vop_plane_destroy(plane); 1964 1965 /* 1966 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1967 * references the CRTC. 1968 */ 1969 drm_crtc_cleanup(crtc); 1970 drm_flip_work_cleanup(&vop->fb_unref_work); 1971 } 1972 1973 static int vop_initial(struct vop *vop) 1974 { 1975 struct reset_control *ahb_rst; 1976 int i, ret; 1977 1978 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1979 if (IS_ERR(vop->hclk)) { 1980 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1981 return PTR_ERR(vop->hclk); 1982 } 1983 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1984 if (IS_ERR(vop->aclk)) { 1985 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1986 return PTR_ERR(vop->aclk); 1987 } 1988 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1989 if (IS_ERR(vop->dclk)) { 1990 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1991 return PTR_ERR(vop->dclk); 1992 } 1993 1994 ret = pm_runtime_resume_and_get(vop->dev); 1995 if (ret < 0) { 1996 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1997 return ret; 1998 } 1999 2000 ret = clk_prepare(vop->dclk); 2001 if (ret < 0) { 2002 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 2003 goto err_put_pm_runtime; 2004 } 2005 2006 /* Enable both the hclk and aclk to setup the vop */ 2007 ret = clk_prepare_enable(vop->hclk); 2008 if (ret < 0) { 2009 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 2010 goto err_unprepare_dclk; 2011 } 2012 2013 ret = clk_prepare_enable(vop->aclk); 2014 if (ret < 0) { 2015 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 2016 goto err_disable_hclk; 2017 } 2018 2019 /* 2020 * do hclk_reset, reset all vop registers. 2021 */ 2022 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 2023 if (IS_ERR(ahb_rst)) { 2024 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 2025 ret = PTR_ERR(ahb_rst); 2026 goto err_disable_aclk; 2027 } 2028 reset_control_assert(ahb_rst); 2029 usleep_range(10, 20); 2030 reset_control_deassert(ahb_rst); 2031 2032 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 2033 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 2034 2035 for (i = 0; i < vop->len; i += sizeof(u32)) 2036 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 2037 2038 VOP_REG_SET(vop, misc, global_regdone_en, 1); 2039 VOP_REG_SET(vop, common, dsp_blank, 0); 2040 2041 for (i = 0; i < vop->data->win_size; i++) { 2042 struct vop_win *vop_win = &vop->win[i]; 2043 const struct vop_win_data *win = vop_win->data; 2044 int channel = i * 2 + 1; 2045 2046 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 2047 vop_win_disable(vop, vop_win); 2048 VOP_WIN_SET(vop, win, gate, 1); 2049 } 2050 2051 vop_cfg_done(vop); 2052 2053 /* 2054 * do dclk_reset, let all config take affect. 2055 */ 2056 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 2057 if (IS_ERR(vop->dclk_rst)) { 2058 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2059 ret = PTR_ERR(vop->dclk_rst); 2060 goto err_disable_aclk; 2061 } 2062 reset_control_assert(vop->dclk_rst); 2063 usleep_range(10, 20); 2064 reset_control_deassert(vop->dclk_rst); 2065 2066 clk_disable(vop->hclk); 2067 clk_disable(vop->aclk); 2068 2069 vop->is_enabled = false; 2070 2071 pm_runtime_put_sync(vop->dev); 2072 2073 return 0; 2074 2075 err_disable_aclk: 2076 clk_disable_unprepare(vop->aclk); 2077 err_disable_hclk: 2078 clk_disable_unprepare(vop->hclk); 2079 err_unprepare_dclk: 2080 clk_unprepare(vop->dclk); 2081 err_put_pm_runtime: 2082 pm_runtime_put_sync(vop->dev); 2083 return ret; 2084 } 2085 2086 /* 2087 * Initialize the vop->win array elements. 2088 */ 2089 static void vop_win_init(struct vop *vop) 2090 { 2091 const struct vop_data *vop_data = vop->data; 2092 unsigned int i; 2093 2094 for (i = 0; i < vop_data->win_size; i++) { 2095 struct vop_win *vop_win = &vop->win[i]; 2096 const struct vop_win_data *win_data = &vop_data->win[i]; 2097 2098 vop_win->data = win_data; 2099 vop_win->vop = vop; 2100 2101 if (vop_data->win_yuv2yuv) 2102 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2103 } 2104 } 2105 2106 /** 2107 * rockchip_drm_wait_vact_end 2108 * @crtc: CRTC to enable line flag 2109 * @mstimeout: millisecond for timeout 2110 * 2111 * Wait for vact_end line flag irq or timeout. 2112 * 2113 * Returns: 2114 * Zero on success, negative errno on failure. 2115 */ 2116 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2117 { 2118 struct vop *vop = to_vop(crtc); 2119 unsigned long jiffies_left; 2120 int ret = 0; 2121 2122 if (!crtc || !vop->is_enabled) 2123 return -ENODEV; 2124 2125 mutex_lock(&vop->vop_lock); 2126 if (mstimeout <= 0) { 2127 ret = -EINVAL; 2128 goto out; 2129 } 2130 2131 if (vop_line_flag_irq_is_enabled(vop)) { 2132 ret = -EBUSY; 2133 goto out; 2134 } 2135 2136 reinit_completion(&vop->line_flag_completion); 2137 vop_line_flag_irq_enable(vop); 2138 2139 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2140 msecs_to_jiffies(mstimeout)); 2141 vop_line_flag_irq_disable(vop); 2142 2143 if (jiffies_left == 0) { 2144 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2145 ret = -ETIMEDOUT; 2146 goto out; 2147 } 2148 2149 out: 2150 mutex_unlock(&vop->vop_lock); 2151 return ret; 2152 } 2153 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2154 2155 static int vop_bind(struct device *dev, struct device *master, void *data) 2156 { 2157 struct platform_device *pdev = to_platform_device(dev); 2158 const struct vop_data *vop_data; 2159 struct drm_device *drm_dev = data; 2160 struct vop *vop; 2161 struct resource *res; 2162 int ret, irq; 2163 2164 vop_data = of_device_get_match_data(dev); 2165 if (!vop_data) 2166 return -ENODEV; 2167 2168 /* Allocate vop struct and its vop_win array */ 2169 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2170 GFP_KERNEL); 2171 if (!vop) 2172 return -ENOMEM; 2173 2174 vop->dev = dev; 2175 vop->data = vop_data; 2176 vop->drm_dev = drm_dev; 2177 dev_set_drvdata(dev, vop); 2178 2179 vop_win_init(vop); 2180 2181 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2182 vop->regs = devm_ioremap_resource(dev, res); 2183 if (IS_ERR(vop->regs)) 2184 return PTR_ERR(vop->regs); 2185 vop->len = resource_size(res); 2186 2187 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2188 if (res) { 2189 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { 2190 DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); 2191 return -EINVAL; 2192 } 2193 vop->lut_regs = devm_ioremap_resource(dev, res); 2194 if (IS_ERR(vop->lut_regs)) 2195 return PTR_ERR(vop->lut_regs); 2196 } 2197 2198 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2199 if (!vop->regsbak) 2200 return -ENOMEM; 2201 2202 irq = platform_get_irq(pdev, 0); 2203 if (irq < 0) { 2204 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2205 return irq; 2206 } 2207 vop->irq = (unsigned int)irq; 2208 2209 spin_lock_init(&vop->reg_lock); 2210 spin_lock_init(&vop->irq_lock); 2211 mutex_init(&vop->vop_lock); 2212 2213 ret = vop_create_crtc(vop); 2214 if (ret) 2215 return ret; 2216 2217 pm_runtime_enable(&pdev->dev); 2218 2219 ret = vop_initial(vop); 2220 if (ret < 0) { 2221 DRM_DEV_ERROR(&pdev->dev, 2222 "cannot initial vop dev - err %d\n", ret); 2223 goto err_disable_pm_runtime; 2224 } 2225 2226 ret = devm_request_irq(dev, vop->irq, vop_isr, 2227 IRQF_SHARED, dev_name(dev), vop); 2228 if (ret) 2229 goto err_disable_pm_runtime; 2230 2231 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2232 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0); 2233 if (IS_ERR(vop->rgb)) { 2234 ret = PTR_ERR(vop->rgb); 2235 goto err_disable_pm_runtime; 2236 } 2237 } 2238 2239 rockchip_drm_dma_init_device(drm_dev, dev); 2240 2241 return 0; 2242 2243 err_disable_pm_runtime: 2244 pm_runtime_disable(&pdev->dev); 2245 vop_destroy_crtc(vop); 2246 return ret; 2247 } 2248 2249 static void vop_unbind(struct device *dev, struct device *master, void *data) 2250 { 2251 struct vop *vop = dev_get_drvdata(dev); 2252 2253 if (vop->rgb) 2254 rockchip_rgb_fini(vop->rgb); 2255 2256 pm_runtime_disable(dev); 2257 vop_destroy_crtc(vop); 2258 2259 clk_unprepare(vop->aclk); 2260 clk_unprepare(vop->hclk); 2261 clk_unprepare(vop->dclk); 2262 } 2263 2264 const struct component_ops vop_component_ops = { 2265 .bind = vop_bind, 2266 .unbind = vop_unbind, 2267 }; 2268 EXPORT_SYMBOL_GPL(vop_component_ops); 2269