1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_crtc.h> 18 #include <drm/drm_crtc_helper.h> 19 #include <drm/drm_plane_helper.h> 20 21 #include <linux/kernel.h> 22 #include <linux/platform_device.h> 23 #include <linux/clk.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/component.h> 28 29 #include <linux/reset.h> 30 #include <linux/delay.h> 31 32 #include "rockchip_drm_drv.h" 33 #include "rockchip_drm_gem.h" 34 #include "rockchip_drm_fb.h" 35 #include "rockchip_drm_vop.h" 36 37 #define VOP_REG(off, _mask, s) \ 38 {.offset = off, \ 39 .mask = _mask, \ 40 .shift = s,} 41 42 #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 43 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 44 #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 45 vop_mask_write(x, off, (mask) << shift, (v) << shift) 46 47 #define REG_SET(x, base, reg, v, mode) \ 48 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 49 50 #define VOP_WIN_SET(x, win, name, v) \ 51 REG_SET(x, win->base, win->phy->name, v, RELAXED) 52 #define VOP_CTRL_SET(x, name, v) \ 53 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 54 55 #define VOP_WIN_GET(x, win, name) \ 56 vop_read_reg(x, win->base, &win->phy->name) 57 58 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 59 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 60 61 #define to_vop(x) container_of(x, struct vop, crtc) 62 #define to_vop_win(x) container_of(x, struct vop_win, base) 63 64 struct vop_win_state { 65 struct list_head head; 66 struct drm_framebuffer *fb; 67 dma_addr_t yrgb_mst; 68 struct drm_pending_vblank_event *event; 69 }; 70 71 struct vop_win { 72 struct drm_plane base; 73 const struct vop_win_data *data; 74 struct vop *vop; 75 76 struct list_head pending; 77 struct vop_win_state *active; 78 }; 79 80 struct vop { 81 struct drm_crtc crtc; 82 struct device *dev; 83 struct drm_device *drm_dev; 84 unsigned int dpms; 85 86 int connector_type; 87 int connector_out_mode; 88 89 /* mutex vsync_ work */ 90 struct mutex vsync_mutex; 91 bool vsync_work_pending; 92 93 const struct vop_data *data; 94 95 uint32_t *regsbak; 96 void __iomem *regs; 97 98 /* physical map length of vop register */ 99 uint32_t len; 100 101 /* one time only one process allowed to config the register */ 102 spinlock_t reg_lock; 103 /* lock vop irq reg */ 104 spinlock_t irq_lock; 105 106 unsigned int irq; 107 108 /* vop AHP clk */ 109 struct clk *hclk; 110 /* vop dclk */ 111 struct clk *dclk; 112 /* vop share memory frequency */ 113 struct clk *aclk; 114 115 /* vop dclk reset */ 116 struct reset_control *dclk_rst; 117 118 int pipe; 119 120 struct vop_win win[]; 121 }; 122 123 enum vop_data_format { 124 VOP_FMT_ARGB8888 = 0, 125 VOP_FMT_RGB888, 126 VOP_FMT_RGB565, 127 VOP_FMT_YUV420SP = 4, 128 VOP_FMT_YUV422SP, 129 VOP_FMT_YUV444SP, 130 }; 131 132 struct vop_reg_data { 133 uint32_t offset; 134 uint32_t value; 135 }; 136 137 struct vop_reg { 138 uint32_t offset; 139 uint32_t shift; 140 uint32_t mask; 141 }; 142 143 struct vop_ctrl { 144 struct vop_reg standby; 145 struct vop_reg data_blank; 146 struct vop_reg gate_en; 147 struct vop_reg mmu_en; 148 struct vop_reg rgb_en; 149 struct vop_reg edp_en; 150 struct vop_reg hdmi_en; 151 struct vop_reg mipi_en; 152 struct vop_reg out_mode; 153 struct vop_reg dither_down; 154 struct vop_reg dither_up; 155 struct vop_reg pin_pol; 156 157 struct vop_reg htotal_pw; 158 struct vop_reg hact_st_end; 159 struct vop_reg vtotal_pw; 160 struct vop_reg vact_st_end; 161 struct vop_reg hpost_st_end; 162 struct vop_reg vpost_st_end; 163 }; 164 165 struct vop_win_phy { 166 const uint32_t *data_formats; 167 uint32_t nformats; 168 169 struct vop_reg enable; 170 struct vop_reg format; 171 struct vop_reg act_info; 172 struct vop_reg dsp_info; 173 struct vop_reg dsp_st; 174 struct vop_reg yrgb_mst; 175 struct vop_reg uv_mst; 176 struct vop_reg yrgb_vir; 177 struct vop_reg uv_vir; 178 179 struct vop_reg dst_alpha_ctl; 180 struct vop_reg src_alpha_ctl; 181 }; 182 183 struct vop_win_data { 184 uint32_t base; 185 const struct vop_win_phy *phy; 186 enum drm_plane_type type; 187 }; 188 189 struct vop_data { 190 const struct vop_reg_data *init_table; 191 unsigned int table_size; 192 const struct vop_ctrl *ctrl; 193 const struct vop_win_data *win; 194 unsigned int win_size; 195 }; 196 197 static const uint32_t formats_01[] = { 198 DRM_FORMAT_XRGB8888, 199 DRM_FORMAT_ARGB8888, 200 DRM_FORMAT_RGB888, 201 DRM_FORMAT_RGB565, 202 DRM_FORMAT_NV12, 203 DRM_FORMAT_NV16, 204 DRM_FORMAT_NV24, 205 }; 206 207 static const uint32_t formats_234[] = { 208 DRM_FORMAT_XRGB8888, 209 DRM_FORMAT_ARGB8888, 210 DRM_FORMAT_RGB888, 211 DRM_FORMAT_RGB565, 212 }; 213 214 static const struct vop_win_phy win01_data = { 215 .data_formats = formats_01, 216 .nformats = ARRAY_SIZE(formats_01), 217 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), 218 .format = VOP_REG(WIN0_CTRL0, 0x7, 1), 219 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0), 220 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0), 221 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0), 222 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0), 223 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0), 224 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0), 225 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16), 226 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0), 227 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0), 228 }; 229 230 static const struct vop_win_phy win23_data = { 231 .data_formats = formats_234, 232 .nformats = ARRAY_SIZE(formats_234), 233 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0), 234 .format = VOP_REG(WIN2_CTRL0, 0x7, 1), 235 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0), 236 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0), 237 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0), 238 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0), 239 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0), 240 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0), 241 }; 242 243 static const struct vop_win_phy cursor_data = { 244 .data_formats = formats_234, 245 .nformats = ARRAY_SIZE(formats_234), 246 .enable = VOP_REG(HWC_CTRL0, 0x1, 0), 247 .format = VOP_REG(HWC_CTRL0, 0x7, 1), 248 .dsp_st = VOP_REG(HWC_DSP_ST, 0x1fff1fff, 0), 249 .yrgb_mst = VOP_REG(HWC_MST, 0xffffffff, 0), 250 }; 251 252 static const struct vop_ctrl ctrl_data = { 253 .standby = VOP_REG(SYS_CTRL, 0x1, 22), 254 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23), 255 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20), 256 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12), 257 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13), 258 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14), 259 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15), 260 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1), 261 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6), 262 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19), 263 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0), 264 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4), 265 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 266 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0), 267 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 268 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0), 269 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0), 270 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0), 271 }; 272 273 static const struct vop_reg_data vop_init_reg_table[] = { 274 {SYS_CTRL, 0x00c00000}, 275 {DSP_CTRL0, 0x00000000}, 276 {WIN0_CTRL0, 0x00000080}, 277 {WIN1_CTRL0, 0x00000080}, 278 }; 279 280 /* 281 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires 282 * special support to get alpha blending working. For now, just use overlay 283 * window 1 for the drm cursor. 284 */ 285 static const struct vop_win_data rk3288_vop_win_data[] = { 286 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, 287 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_CURSOR }, 288 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, 289 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, 290 { .base = 0x00, .phy = &cursor_data, .type = DRM_PLANE_TYPE_OVERLAY }, 291 }; 292 293 static const struct vop_data rk3288_vop = { 294 .init_table = vop_init_reg_table, 295 .table_size = ARRAY_SIZE(vop_init_reg_table), 296 .ctrl = &ctrl_data, 297 .win = rk3288_vop_win_data, 298 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 299 }; 300 301 static const struct of_device_id vop_driver_dt_match[] = { 302 { .compatible = "rockchip,rk3288-vop", 303 .data = &rk3288_vop }, 304 {}, 305 }; 306 307 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 308 { 309 writel(v, vop->regs + offset); 310 vop->regsbak[offset >> 2] = v; 311 } 312 313 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 314 { 315 return readl(vop->regs + offset); 316 } 317 318 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 319 const struct vop_reg *reg) 320 { 321 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 322 } 323 324 static inline void vop_cfg_done(struct vop *vop) 325 { 326 writel(0x01, vop->regs + REG_CFG_DONE); 327 } 328 329 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 330 uint32_t mask, uint32_t v) 331 { 332 if (mask) { 333 uint32_t cached_val = vop->regsbak[offset >> 2]; 334 335 cached_val = (cached_val & ~mask) | v; 336 writel(cached_val, vop->regs + offset); 337 vop->regsbak[offset >> 2] = cached_val; 338 } 339 } 340 341 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 342 uint32_t mask, uint32_t v) 343 { 344 if (mask) { 345 uint32_t cached_val = vop->regsbak[offset >> 2]; 346 347 cached_val = (cached_val & ~mask) | v; 348 writel_relaxed(cached_val, vop->regs + offset); 349 vop->regsbak[offset >> 2] = cached_val; 350 } 351 } 352 353 static enum vop_data_format vop_convert_format(uint32_t format) 354 { 355 switch (format) { 356 case DRM_FORMAT_XRGB8888: 357 case DRM_FORMAT_ARGB8888: 358 return VOP_FMT_ARGB8888; 359 case DRM_FORMAT_RGB888: 360 return VOP_FMT_RGB888; 361 case DRM_FORMAT_RGB565: 362 return VOP_FMT_RGB565; 363 case DRM_FORMAT_NV12: 364 return VOP_FMT_YUV420SP; 365 case DRM_FORMAT_NV16: 366 return VOP_FMT_YUV422SP; 367 case DRM_FORMAT_NV24: 368 return VOP_FMT_YUV444SP; 369 default: 370 DRM_ERROR("unsupport format[%08x]\n", format); 371 return -EINVAL; 372 } 373 } 374 375 static bool is_alpha_support(uint32_t format) 376 { 377 switch (format) { 378 case DRM_FORMAT_ARGB8888: 379 return true; 380 default: 381 return false; 382 } 383 } 384 385 static void vop_enable(struct drm_crtc *crtc) 386 { 387 struct vop *vop = to_vop(crtc); 388 int ret; 389 390 ret = clk_enable(vop->hclk); 391 if (ret < 0) { 392 dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 393 return; 394 } 395 396 ret = clk_enable(vop->dclk); 397 if (ret < 0) { 398 dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 399 goto err_disable_hclk; 400 } 401 402 ret = clk_enable(vop->aclk); 403 if (ret < 0) { 404 dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 405 goto err_disable_dclk; 406 } 407 408 /* 409 * Slave iommu shares power, irq and clock with vop. It was associated 410 * automatically with this master device via common driver code. 411 * Now that we have enabled the clock we attach it to the shared drm 412 * mapping. 413 */ 414 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 415 if (ret) { 416 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 417 goto err_disable_aclk; 418 } 419 420 spin_lock(&vop->reg_lock); 421 422 VOP_CTRL_SET(vop, standby, 0); 423 424 spin_unlock(&vop->reg_lock); 425 426 enable_irq(vop->irq); 427 428 drm_vblank_on(vop->drm_dev, vop->pipe); 429 430 return; 431 432 err_disable_aclk: 433 clk_disable(vop->aclk); 434 err_disable_dclk: 435 clk_disable(vop->dclk); 436 err_disable_hclk: 437 clk_disable(vop->hclk); 438 } 439 440 static void vop_disable(struct drm_crtc *crtc) 441 { 442 struct vop *vop = to_vop(crtc); 443 444 drm_vblank_off(crtc->dev, vop->pipe); 445 446 disable_irq(vop->irq); 447 448 /* 449 * TODO: Since standby doesn't take effect until the next vblank, 450 * when we turn off dclk below, the vop is probably still active. 451 */ 452 spin_lock(&vop->reg_lock); 453 454 VOP_CTRL_SET(vop, standby, 1); 455 456 spin_unlock(&vop->reg_lock); 457 /* 458 * disable dclk to stop frame scan, so we can safely detach iommu, 459 */ 460 clk_disable(vop->dclk); 461 462 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 463 464 clk_disable(vop->aclk); 465 clk_disable(vop->hclk); 466 } 467 468 /* 469 * Caller must hold vsync_mutex. 470 */ 471 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win) 472 { 473 struct vop_win_state *last; 474 struct vop_win_state *active = vop_win->active; 475 476 if (list_empty(&vop_win->pending)) 477 return active ? active->fb : NULL; 478 479 last = list_last_entry(&vop_win->pending, struct vop_win_state, head); 480 return last ? last->fb : NULL; 481 } 482 483 /* 484 * Caller must hold vsync_mutex. 485 */ 486 static int vop_win_queue_fb(struct vop_win *vop_win, 487 struct drm_framebuffer *fb, dma_addr_t yrgb_mst, 488 struct drm_pending_vblank_event *event) 489 { 490 struct vop_win_state *state; 491 492 state = kzalloc(sizeof(*state), GFP_KERNEL); 493 if (!state) 494 return -ENOMEM; 495 496 state->fb = fb; 497 state->yrgb_mst = yrgb_mst; 498 state->event = event; 499 500 list_add_tail(&state->head, &vop_win->pending); 501 502 return 0; 503 } 504 505 static int vop_update_plane_event(struct drm_plane *plane, 506 struct drm_crtc *crtc, 507 struct drm_framebuffer *fb, int crtc_x, 508 int crtc_y, unsigned int crtc_w, 509 unsigned int crtc_h, uint32_t src_x, 510 uint32_t src_y, uint32_t src_w, 511 uint32_t src_h, 512 struct drm_pending_vblank_event *event) 513 { 514 struct vop_win *vop_win = to_vop_win(plane); 515 const struct vop_win_data *win = vop_win->data; 516 struct vop *vop = to_vop(crtc); 517 struct drm_gem_object *obj; 518 struct rockchip_gem_object *rk_obj; 519 unsigned long offset; 520 unsigned int actual_w; 521 unsigned int actual_h; 522 unsigned int dsp_stx; 523 unsigned int dsp_sty; 524 unsigned int y_vir_stride; 525 dma_addr_t yrgb_mst; 526 enum vop_data_format format; 527 uint32_t val; 528 bool is_alpha; 529 bool visible; 530 int ret; 531 struct drm_rect dest = { 532 .x1 = crtc_x, 533 .y1 = crtc_y, 534 .x2 = crtc_x + crtc_w, 535 .y2 = crtc_y + crtc_h, 536 }; 537 struct drm_rect src = { 538 /* 16.16 fixed point */ 539 .x1 = src_x, 540 .y1 = src_y, 541 .x2 = src_x + src_w, 542 .y2 = src_y + src_h, 543 }; 544 const struct drm_rect clip = { 545 .x2 = crtc->mode.hdisplay, 546 .y2 = crtc->mode.vdisplay, 547 }; 548 bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY; 549 550 ret = drm_plane_helper_check_update(plane, crtc, fb, 551 &src, &dest, &clip, 552 DRM_PLANE_HELPER_NO_SCALING, 553 DRM_PLANE_HELPER_NO_SCALING, 554 can_position, false, &visible); 555 if (ret) 556 return ret; 557 558 if (!visible) 559 return 0; 560 561 is_alpha = is_alpha_support(fb->pixel_format); 562 format = vop_convert_format(fb->pixel_format); 563 if (format < 0) 564 return format; 565 566 obj = rockchip_fb_get_gem_obj(fb, 0); 567 if (!obj) { 568 DRM_ERROR("fail to get rockchip gem object from framebuffer\n"); 569 return -EINVAL; 570 } 571 572 rk_obj = to_rockchip_obj(obj); 573 574 actual_w = (src.x2 - src.x1) >> 16; 575 actual_h = (src.y2 - src.y1) >> 16; 576 crtc_x = max(0, crtc_x); 577 crtc_y = max(0, crtc_y); 578 579 dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start; 580 dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start; 581 582 offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3); 583 offset += (src.y1 >> 16) * fb->pitches[0]; 584 yrgb_mst = rk_obj->dma_addr + offset; 585 586 y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3); 587 588 /* 589 * If this plane update changes the plane's framebuffer, (or more 590 * precisely, if this update has a different framebuffer than the last 591 * update), enqueue it so we can track when it completes. 592 * 593 * Only when we discover that this update has completed, can we 594 * unreference any previous framebuffers. 595 */ 596 mutex_lock(&vop->vsync_mutex); 597 if (fb != vop_win_last_pending_fb(vop_win)) { 598 ret = drm_vblank_get(plane->dev, vop->pipe); 599 if (ret) { 600 DRM_ERROR("failed to get vblank, %d\n", ret); 601 mutex_unlock(&vop->vsync_mutex); 602 return ret; 603 } 604 605 drm_framebuffer_reference(fb); 606 607 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event); 608 if (ret) { 609 drm_vblank_put(plane->dev, vop->pipe); 610 mutex_unlock(&vop->vsync_mutex); 611 return ret; 612 } 613 614 vop->vsync_work_pending = true; 615 } 616 mutex_unlock(&vop->vsync_mutex); 617 618 spin_lock(&vop->reg_lock); 619 620 VOP_WIN_SET(vop, win, format, format); 621 VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride); 622 VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst); 623 val = (actual_h - 1) << 16; 624 val |= (actual_w - 1) & 0xffff; 625 VOP_WIN_SET(vop, win, act_info, val); 626 VOP_WIN_SET(vop, win, dsp_info, val); 627 val = (dsp_sty - 1) << 16; 628 val |= (dsp_stx - 1) & 0xffff; 629 VOP_WIN_SET(vop, win, dsp_st, val); 630 631 if (is_alpha) { 632 VOP_WIN_SET(vop, win, dst_alpha_ctl, 633 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 634 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 635 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 636 SRC_BLEND_M0(ALPHA_PER_PIX) | 637 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 638 SRC_FACTOR_M0(ALPHA_ONE); 639 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 640 } else { 641 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 642 } 643 644 VOP_WIN_SET(vop, win, enable, 1); 645 646 vop_cfg_done(vop); 647 spin_unlock(&vop->reg_lock); 648 649 return 0; 650 } 651 652 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 653 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 654 unsigned int crtc_w, unsigned int crtc_h, 655 uint32_t src_x, uint32_t src_y, uint32_t src_w, 656 uint32_t src_h) 657 { 658 return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w, 659 crtc_h, src_x, src_y, src_w, src_h, 660 NULL); 661 } 662 663 static int vop_update_primary_plane(struct drm_crtc *crtc, 664 struct drm_pending_vblank_event *event) 665 { 666 unsigned int crtc_w, crtc_h; 667 668 crtc_w = crtc->primary->fb->width - crtc->x; 669 crtc_h = crtc->primary->fb->height - crtc->y; 670 671 return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb, 672 0, 0, crtc_w, crtc_h, crtc->x << 16, 673 crtc->y << 16, crtc_w << 16, 674 crtc_h << 16, event); 675 } 676 677 static int vop_disable_plane(struct drm_plane *plane) 678 { 679 struct vop_win *vop_win = to_vop_win(plane); 680 const struct vop_win_data *win = vop_win->data; 681 struct vop *vop; 682 int ret; 683 684 if (!plane->crtc) 685 return 0; 686 687 vop = to_vop(plane->crtc); 688 689 ret = drm_vblank_get(plane->dev, vop->pipe); 690 if (ret) { 691 DRM_ERROR("failed to get vblank, %d\n", ret); 692 return ret; 693 } 694 695 mutex_lock(&vop->vsync_mutex); 696 697 ret = vop_win_queue_fb(vop_win, NULL, 0, NULL); 698 if (ret) { 699 drm_vblank_put(plane->dev, vop->pipe); 700 mutex_unlock(&vop->vsync_mutex); 701 return ret; 702 } 703 704 vop->vsync_work_pending = true; 705 mutex_unlock(&vop->vsync_mutex); 706 707 spin_lock(&vop->reg_lock); 708 VOP_WIN_SET(vop, win, enable, 0); 709 vop_cfg_done(vop); 710 spin_unlock(&vop->reg_lock); 711 712 return 0; 713 } 714 715 static void vop_plane_destroy(struct drm_plane *plane) 716 { 717 vop_disable_plane(plane); 718 drm_plane_cleanup(plane); 719 } 720 721 static const struct drm_plane_funcs vop_plane_funcs = { 722 .update_plane = vop_update_plane, 723 .disable_plane = vop_disable_plane, 724 .destroy = vop_plane_destroy, 725 }; 726 727 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, 728 int connector_type, 729 int out_mode) 730 { 731 struct vop *vop = to_vop(crtc); 732 733 vop->connector_type = connector_type; 734 vop->connector_out_mode = out_mode; 735 736 return 0; 737 } 738 739 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 740 { 741 struct vop *vop = to_vop(crtc); 742 unsigned long flags; 743 744 if (vop->dpms != DRM_MODE_DPMS_ON) 745 return -EPERM; 746 747 spin_lock_irqsave(&vop->irq_lock, flags); 748 749 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1)); 750 751 spin_unlock_irqrestore(&vop->irq_lock, flags); 752 753 return 0; 754 } 755 756 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 757 { 758 struct vop *vop = to_vop(crtc); 759 unsigned long flags; 760 761 if (vop->dpms != DRM_MODE_DPMS_ON) 762 return; 763 spin_lock_irqsave(&vop->irq_lock, flags); 764 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0)); 765 spin_unlock_irqrestore(&vop->irq_lock, flags); 766 } 767 768 static const struct rockchip_crtc_funcs private_crtc_funcs = { 769 .enable_vblank = vop_crtc_enable_vblank, 770 .disable_vblank = vop_crtc_disable_vblank, 771 }; 772 773 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode) 774 { 775 struct vop *vop = to_vop(crtc); 776 777 DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode); 778 779 if (vop->dpms == mode) { 780 DRM_DEBUG_KMS("desired dpms mode is same as previous one.\n"); 781 return; 782 } 783 784 switch (mode) { 785 case DRM_MODE_DPMS_ON: 786 vop_enable(crtc); 787 break; 788 case DRM_MODE_DPMS_STANDBY: 789 case DRM_MODE_DPMS_SUSPEND: 790 case DRM_MODE_DPMS_OFF: 791 vop_disable(crtc); 792 break; 793 default: 794 DRM_DEBUG_KMS("unspecified mode %d\n", mode); 795 break; 796 } 797 798 vop->dpms = mode; 799 } 800 801 static void vop_crtc_prepare(struct drm_crtc *crtc) 802 { 803 vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 804 } 805 806 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 807 const struct drm_display_mode *mode, 808 struct drm_display_mode *adjusted_mode) 809 { 810 if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0) 811 return false; 812 813 return true; 814 } 815 816 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 817 struct drm_framebuffer *old_fb) 818 { 819 int ret; 820 821 crtc->x = x; 822 crtc->y = y; 823 824 ret = vop_update_primary_plane(crtc, NULL); 825 if (ret < 0) { 826 DRM_ERROR("fail to update plane\n"); 827 return ret; 828 } 829 830 return 0; 831 } 832 833 static int vop_crtc_mode_set(struct drm_crtc *crtc, 834 struct drm_display_mode *mode, 835 struct drm_display_mode *adjusted_mode, 836 int x, int y, struct drm_framebuffer *fb) 837 { 838 struct vop *vop = to_vop(crtc); 839 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 840 u16 hdisplay = adjusted_mode->hdisplay; 841 u16 htotal = adjusted_mode->htotal; 842 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 843 u16 hact_end = hact_st + hdisplay; 844 u16 vdisplay = adjusted_mode->vdisplay; 845 u16 vtotal = adjusted_mode->vtotal; 846 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 847 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 848 u16 vact_end = vact_st + vdisplay; 849 int ret; 850 uint32_t val; 851 852 /* 853 * disable dclk to stop frame scan, so that we can safe config mode and 854 * enable iommu. 855 */ 856 clk_disable(vop->dclk); 857 858 switch (vop->connector_type) { 859 case DRM_MODE_CONNECTOR_LVDS: 860 VOP_CTRL_SET(vop, rgb_en, 1); 861 break; 862 case DRM_MODE_CONNECTOR_eDP: 863 VOP_CTRL_SET(vop, edp_en, 1); 864 break; 865 case DRM_MODE_CONNECTOR_HDMIA: 866 VOP_CTRL_SET(vop, hdmi_en, 1); 867 break; 868 default: 869 DRM_ERROR("unsupport connector_type[%d]\n", 870 vop->connector_type); 871 return -EINVAL; 872 }; 873 VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode); 874 875 val = 0x8; 876 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0; 877 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? (1 << 1) : 0; 878 VOP_CTRL_SET(vop, pin_pol, val); 879 880 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 881 val = hact_st << 16; 882 val |= hact_end; 883 VOP_CTRL_SET(vop, hact_st_end, val); 884 VOP_CTRL_SET(vop, hpost_st_end, val); 885 886 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 887 val = vact_st << 16; 888 val |= vact_end; 889 VOP_CTRL_SET(vop, vact_st_end, val); 890 VOP_CTRL_SET(vop, vpost_st_end, val); 891 892 ret = vop_crtc_mode_set_base(crtc, x, y, fb); 893 if (ret) 894 return ret; 895 896 /* 897 * reset dclk, take all mode config affect, so the clk would run in 898 * correct frame. 899 */ 900 reset_control_assert(vop->dclk_rst); 901 usleep_range(10, 20); 902 reset_control_deassert(vop->dclk_rst); 903 904 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 905 ret = clk_enable(vop->dclk); 906 if (ret < 0) { 907 dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 908 return ret; 909 } 910 911 return 0; 912 } 913 914 static void vop_crtc_commit(struct drm_crtc *crtc) 915 { 916 } 917 918 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 919 .dpms = vop_crtc_dpms, 920 .prepare = vop_crtc_prepare, 921 .mode_fixup = vop_crtc_mode_fixup, 922 .mode_set = vop_crtc_mode_set, 923 .mode_set_base = vop_crtc_mode_set_base, 924 .commit = vop_crtc_commit, 925 }; 926 927 static int vop_crtc_page_flip(struct drm_crtc *crtc, 928 struct drm_framebuffer *fb, 929 struct drm_pending_vblank_event *event, 930 uint32_t page_flip_flags) 931 { 932 struct vop *vop = to_vop(crtc); 933 struct drm_framebuffer *old_fb = crtc->primary->fb; 934 int ret; 935 936 /* when the page flip is requested, crtc's dpms should be on */ 937 if (vop->dpms > DRM_MODE_DPMS_ON) { 938 DRM_DEBUG("failed page flip request at dpms[%d].\n", vop->dpms); 939 return 0; 940 } 941 942 crtc->primary->fb = fb; 943 944 ret = vop_update_primary_plane(crtc, event); 945 if (ret) 946 crtc->primary->fb = old_fb; 947 948 return ret; 949 } 950 951 static void vop_win_state_complete(struct vop_win *vop_win, 952 struct vop_win_state *state) 953 { 954 struct vop *vop = vop_win->vop; 955 struct drm_crtc *crtc = &vop->crtc; 956 struct drm_device *drm = crtc->dev; 957 unsigned long flags; 958 959 if (state->event) { 960 spin_lock_irqsave(&drm->event_lock, flags); 961 drm_send_vblank_event(drm, -1, state->event); 962 spin_unlock_irqrestore(&drm->event_lock, flags); 963 } 964 965 list_del(&state->head); 966 drm_vblank_put(crtc->dev, vop->pipe); 967 } 968 969 static void vop_crtc_destroy(struct drm_crtc *crtc) 970 { 971 drm_crtc_cleanup(crtc); 972 } 973 974 static const struct drm_crtc_funcs vop_crtc_funcs = { 975 .set_config = drm_crtc_helper_set_config, 976 .page_flip = vop_crtc_page_flip, 977 .destroy = vop_crtc_destroy, 978 }; 979 980 static bool vop_win_state_is_active(struct vop_win *vop_win, 981 struct vop_win_state *state) 982 { 983 bool active = false; 984 985 if (state->fb) { 986 dma_addr_t yrgb_mst; 987 988 /* check yrgb_mst to tell if pending_fb is now front */ 989 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 990 991 active = (yrgb_mst == state->yrgb_mst); 992 } else { 993 bool enabled; 994 995 /* if enable bit is clear, plane is now disabled */ 996 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable); 997 998 active = (enabled == 0); 999 } 1000 1001 return active; 1002 } 1003 1004 static void vop_win_state_destroy(struct vop_win_state *state) 1005 { 1006 struct drm_framebuffer *fb = state->fb; 1007 1008 if (fb) 1009 drm_framebuffer_unreference(fb); 1010 1011 kfree(state); 1012 } 1013 1014 static void vop_win_update_state(struct vop_win *vop_win) 1015 { 1016 struct vop_win_state *state, *n, *new_active = NULL; 1017 1018 /* Check if any pending states are now active */ 1019 list_for_each_entry(state, &vop_win->pending, head) 1020 if (vop_win_state_is_active(vop_win, state)) { 1021 new_active = state; 1022 break; 1023 } 1024 1025 if (!new_active) 1026 return; 1027 1028 /* 1029 * Destroy any 'skipped' pending states - states that were queued 1030 * before the newly active state. 1031 */ 1032 list_for_each_entry_safe(state, n, &vop_win->pending, head) { 1033 if (state == new_active) 1034 break; 1035 vop_win_state_complete(vop_win, state); 1036 vop_win_state_destroy(state); 1037 } 1038 1039 vop_win_state_complete(vop_win, new_active); 1040 1041 if (vop_win->active) 1042 vop_win_state_destroy(vop_win->active); 1043 vop_win->active = new_active; 1044 } 1045 1046 static bool vop_win_has_pending_state(struct vop_win *vop_win) 1047 { 1048 return !list_empty(&vop_win->pending); 1049 } 1050 1051 static irqreturn_t vop_isr_thread(int irq, void *data) 1052 { 1053 struct vop *vop = data; 1054 const struct vop_data *vop_data = vop->data; 1055 unsigned int i; 1056 1057 mutex_lock(&vop->vsync_mutex); 1058 1059 if (!vop->vsync_work_pending) 1060 goto done; 1061 1062 vop->vsync_work_pending = false; 1063 1064 for (i = 0; i < vop_data->win_size; i++) { 1065 struct vop_win *vop_win = &vop->win[i]; 1066 1067 vop_win_update_state(vop_win); 1068 if (vop_win_has_pending_state(vop_win)) 1069 vop->vsync_work_pending = true; 1070 } 1071 1072 done: 1073 mutex_unlock(&vop->vsync_mutex); 1074 1075 return IRQ_HANDLED; 1076 } 1077 1078 static irqreturn_t vop_isr(int irq, void *data) 1079 { 1080 struct vop *vop = data; 1081 uint32_t intr0_reg, active_irqs; 1082 unsigned long flags; 1083 1084 /* 1085 * INTR_CTRL0 register has interrupt status, enable and clear bits, we 1086 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1087 */ 1088 spin_lock_irqsave(&vop->irq_lock, flags); 1089 intr0_reg = vop_readl(vop, INTR_CTRL0); 1090 active_irqs = intr0_reg & INTR_MASK; 1091 /* Clear all active interrupt sources */ 1092 if (active_irqs) 1093 vop_writel(vop, INTR_CTRL0, 1094 intr0_reg | (active_irqs << INTR_CLR_SHIFT)); 1095 spin_unlock_irqrestore(&vop->irq_lock, flags); 1096 1097 /* This is expected for vop iommu irqs, since the irq is shared */ 1098 if (!active_irqs) 1099 return IRQ_NONE; 1100 1101 /* Only Frame Start Interrupt is enabled; other irqs are spurious. */ 1102 if (!(active_irqs & FS_INTR)) { 1103 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 1104 return IRQ_NONE; 1105 } 1106 1107 drm_handle_vblank(vop->drm_dev, vop->pipe); 1108 1109 return (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED; 1110 } 1111 1112 static int vop_create_crtc(struct vop *vop) 1113 { 1114 const struct vop_data *vop_data = vop->data; 1115 struct device *dev = vop->dev; 1116 struct drm_device *drm_dev = vop->drm_dev; 1117 struct drm_plane *primary = NULL, *cursor = NULL, *plane; 1118 struct drm_crtc *crtc = &vop->crtc; 1119 struct device_node *port; 1120 int ret; 1121 int i; 1122 1123 /* 1124 * Create drm_plane for primary and cursor planes first, since we need 1125 * to pass them to drm_crtc_init_with_planes, which sets the 1126 * "possible_crtcs" to the newly initialized crtc. 1127 */ 1128 for (i = 0; i < vop_data->win_size; i++) { 1129 struct vop_win *vop_win = &vop->win[i]; 1130 const struct vop_win_data *win_data = vop_win->data; 1131 1132 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1133 win_data->type != DRM_PLANE_TYPE_CURSOR) 1134 continue; 1135 1136 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1137 0, &vop_plane_funcs, 1138 win_data->phy->data_formats, 1139 win_data->phy->nformats, 1140 win_data->type); 1141 if (ret) { 1142 DRM_ERROR("failed to initialize plane\n"); 1143 goto err_cleanup_planes; 1144 } 1145 1146 plane = &vop_win->base; 1147 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1148 primary = plane; 1149 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1150 cursor = plane; 1151 } 1152 1153 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1154 &vop_crtc_funcs); 1155 if (ret) 1156 return ret; 1157 1158 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1159 1160 /* 1161 * Create drm_planes for overlay windows with possible_crtcs restricted 1162 * to the newly created crtc. 1163 */ 1164 for (i = 0; i < vop_data->win_size; i++) { 1165 struct vop_win *vop_win = &vop->win[i]; 1166 const struct vop_win_data *win_data = vop_win->data; 1167 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1168 1169 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1170 continue; 1171 1172 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1173 possible_crtcs, 1174 &vop_plane_funcs, 1175 win_data->phy->data_formats, 1176 win_data->phy->nformats, 1177 win_data->type); 1178 if (ret) { 1179 DRM_ERROR("failed to initialize overlay plane\n"); 1180 goto err_cleanup_crtc; 1181 } 1182 } 1183 1184 port = of_get_child_by_name(dev->of_node, "port"); 1185 if (!port) { 1186 DRM_ERROR("no port node found in %s\n", 1187 dev->of_node->full_name); 1188 goto err_cleanup_crtc; 1189 } 1190 1191 crtc->port = port; 1192 vop->pipe = drm_crtc_index(crtc); 1193 rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe); 1194 1195 return 0; 1196 1197 err_cleanup_crtc: 1198 drm_crtc_cleanup(crtc); 1199 err_cleanup_planes: 1200 list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head) 1201 drm_plane_cleanup(plane); 1202 return ret; 1203 } 1204 1205 static void vop_destroy_crtc(struct vop *vop) 1206 { 1207 struct drm_crtc *crtc = &vop->crtc; 1208 1209 rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe); 1210 of_node_put(crtc->port); 1211 drm_crtc_cleanup(crtc); 1212 } 1213 1214 static int vop_initial(struct vop *vop) 1215 { 1216 const struct vop_data *vop_data = vop->data; 1217 const struct vop_reg_data *init_table = vop_data->init_table; 1218 struct reset_control *ahb_rst; 1219 int i, ret; 1220 1221 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1222 if (IS_ERR(vop->hclk)) { 1223 dev_err(vop->dev, "failed to get hclk source\n"); 1224 return PTR_ERR(vop->hclk); 1225 } 1226 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1227 if (IS_ERR(vop->aclk)) { 1228 dev_err(vop->dev, "failed to get aclk source\n"); 1229 return PTR_ERR(vop->aclk); 1230 } 1231 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1232 if (IS_ERR(vop->dclk)) { 1233 dev_err(vop->dev, "failed to get dclk source\n"); 1234 return PTR_ERR(vop->dclk); 1235 } 1236 1237 ret = clk_prepare(vop->hclk); 1238 if (ret < 0) { 1239 dev_err(vop->dev, "failed to prepare hclk\n"); 1240 return ret; 1241 } 1242 1243 ret = clk_prepare(vop->dclk); 1244 if (ret < 0) { 1245 dev_err(vop->dev, "failed to prepare dclk\n"); 1246 goto err_unprepare_hclk; 1247 } 1248 1249 ret = clk_prepare(vop->aclk); 1250 if (ret < 0) { 1251 dev_err(vop->dev, "failed to prepare aclk\n"); 1252 goto err_unprepare_dclk; 1253 } 1254 1255 /* 1256 * enable hclk, so that we can config vop register. 1257 */ 1258 ret = clk_enable(vop->hclk); 1259 if (ret < 0) { 1260 dev_err(vop->dev, "failed to prepare aclk\n"); 1261 goto err_unprepare_aclk; 1262 } 1263 /* 1264 * do hclk_reset, reset all vop registers. 1265 */ 1266 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1267 if (IS_ERR(ahb_rst)) { 1268 dev_err(vop->dev, "failed to get ahb reset\n"); 1269 ret = PTR_ERR(ahb_rst); 1270 goto err_disable_hclk; 1271 } 1272 reset_control_assert(ahb_rst); 1273 usleep_range(10, 20); 1274 reset_control_deassert(ahb_rst); 1275 1276 memcpy(vop->regsbak, vop->regs, vop->len); 1277 1278 for (i = 0; i < vop_data->table_size; i++) 1279 vop_writel(vop, init_table[i].offset, init_table[i].value); 1280 1281 for (i = 0; i < vop_data->win_size; i++) { 1282 const struct vop_win_data *win = &vop_data->win[i]; 1283 1284 VOP_WIN_SET(vop, win, enable, 0); 1285 } 1286 1287 vop_cfg_done(vop); 1288 1289 /* 1290 * do dclk_reset, let all config take affect. 1291 */ 1292 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1293 if (IS_ERR(vop->dclk_rst)) { 1294 dev_err(vop->dev, "failed to get dclk reset\n"); 1295 ret = PTR_ERR(vop->dclk_rst); 1296 goto err_unprepare_aclk; 1297 } 1298 reset_control_assert(vop->dclk_rst); 1299 usleep_range(10, 20); 1300 reset_control_deassert(vop->dclk_rst); 1301 1302 clk_disable(vop->hclk); 1303 1304 vop->dpms = DRM_MODE_DPMS_OFF; 1305 1306 return 0; 1307 1308 err_disable_hclk: 1309 clk_disable(vop->hclk); 1310 err_unprepare_aclk: 1311 clk_unprepare(vop->aclk); 1312 err_unprepare_dclk: 1313 clk_unprepare(vop->dclk); 1314 err_unprepare_hclk: 1315 clk_unprepare(vop->hclk); 1316 return ret; 1317 } 1318 1319 /* 1320 * Initialize the vop->win array elements. 1321 */ 1322 static void vop_win_init(struct vop *vop) 1323 { 1324 const struct vop_data *vop_data = vop->data; 1325 unsigned int i; 1326 1327 for (i = 0; i < vop_data->win_size; i++) { 1328 struct vop_win *vop_win = &vop->win[i]; 1329 const struct vop_win_data *win_data = &vop_data->win[i]; 1330 1331 vop_win->data = win_data; 1332 vop_win->vop = vop; 1333 INIT_LIST_HEAD(&vop_win->pending); 1334 } 1335 } 1336 1337 static int vop_bind(struct device *dev, struct device *master, void *data) 1338 { 1339 struct platform_device *pdev = to_platform_device(dev); 1340 const struct of_device_id *of_id; 1341 const struct vop_data *vop_data; 1342 struct drm_device *drm_dev = data; 1343 struct vop *vop; 1344 struct resource *res; 1345 size_t alloc_size; 1346 int ret; 1347 1348 of_id = of_match_device(vop_driver_dt_match, dev); 1349 vop_data = of_id->data; 1350 if (!vop_data) 1351 return -ENODEV; 1352 1353 /* Allocate vop struct and its vop_win array */ 1354 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1355 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1356 if (!vop) 1357 return -ENOMEM; 1358 1359 vop->dev = dev; 1360 vop->data = vop_data; 1361 vop->drm_dev = drm_dev; 1362 dev_set_drvdata(dev, vop); 1363 1364 vop_win_init(vop); 1365 1366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1367 vop->len = resource_size(res); 1368 vop->regs = devm_ioremap_resource(dev, res); 1369 if (IS_ERR(vop->regs)) 1370 return PTR_ERR(vop->regs); 1371 1372 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1373 if (!vop->regsbak) 1374 return -ENOMEM; 1375 1376 ret = vop_initial(vop); 1377 if (ret < 0) { 1378 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 1379 return ret; 1380 } 1381 1382 vop->irq = platform_get_irq(pdev, 0); 1383 if (vop->irq < 0) { 1384 dev_err(dev, "cannot find irq for vop\n"); 1385 return vop->irq; 1386 } 1387 1388 spin_lock_init(&vop->reg_lock); 1389 spin_lock_init(&vop->irq_lock); 1390 1391 mutex_init(&vop->vsync_mutex); 1392 1393 ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread, 1394 IRQF_SHARED, dev_name(dev), vop); 1395 if (ret) 1396 return ret; 1397 1398 /* IRQ is initially disabled; it gets enabled in power_on */ 1399 disable_irq(vop->irq); 1400 1401 ret = vop_create_crtc(vop); 1402 if (ret) 1403 return ret; 1404 1405 pm_runtime_enable(&pdev->dev); 1406 return 0; 1407 } 1408 1409 static void vop_unbind(struct device *dev, struct device *master, void *data) 1410 { 1411 struct vop *vop = dev_get_drvdata(dev); 1412 1413 pm_runtime_disable(dev); 1414 vop_destroy_crtc(vop); 1415 } 1416 1417 static const struct component_ops vop_component_ops = { 1418 .bind = vop_bind, 1419 .unbind = vop_unbind, 1420 }; 1421 1422 static int vop_probe(struct platform_device *pdev) 1423 { 1424 struct device *dev = &pdev->dev; 1425 1426 if (!dev->of_node) { 1427 dev_err(dev, "can't find vop devices\n"); 1428 return -ENODEV; 1429 } 1430 1431 return component_add(dev, &vop_component_ops); 1432 } 1433 1434 static int vop_remove(struct platform_device *pdev) 1435 { 1436 component_del(&pdev->dev, &vop_component_ops); 1437 1438 return 0; 1439 } 1440 1441 struct platform_driver vop_platform_driver = { 1442 .probe = vop_probe, 1443 .remove = vop_remove, 1444 .driver = { 1445 .name = "rockchip-vop", 1446 .owner = THIS_MODULE, 1447 .of_match_table = of_match_ptr(vop_driver_dt_match), 1448 }, 1449 }; 1450 1451 module_platform_driver(vop_platform_driver); 1452 1453 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>"); 1454 MODULE_DESCRIPTION("ROCKCHIP VOP Driver"); 1455 MODULE_LICENSE("GPL v2"); 1456