1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_plane_helper.h> 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/clk.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/component.h> 30 31 #include <linux/reset.h> 32 #include <linux/delay.h> 33 34 #include "rockchip_drm_drv.h" 35 #include "rockchip_drm_gem.h" 36 #include "rockchip_drm_fb.h" 37 #include "rockchip_drm_vop.h" 38 39 #define __REG_SET_RELAXED(x, off, mask, shift, v) \ 40 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift) 41 #define __REG_SET_NORMAL(x, off, mask, shift, v) \ 42 vop_mask_write(x, off, (mask) << shift, (v) << shift) 43 44 #define REG_SET(x, base, reg, v, mode) \ 45 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) 46 #define REG_SET_MASK(x, base, reg, mask, v, mode) \ 47 __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v) 48 49 #define VOP_WIN_SET(x, win, name, v) \ 50 REG_SET(x, win->base, win->phy->name, v, RELAXED) 51 #define VOP_SCL_SET(x, win, name, v) \ 52 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) 53 #define VOP_SCL_SET_EXT(x, win, name, v) \ 54 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) 55 #define VOP_CTRL_SET(x, name, v) \ 56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) 57 58 #define VOP_INTR_GET(vop, name) \ 59 vop_read_reg(vop, 0, &vop->data->ctrl->name) 60 61 #define VOP_INTR_SET(vop, name, mask, v) \ 62 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) 63 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 64 do { \ 65 int i, reg = 0, mask = 0; \ 66 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 67 if (vop->data->intr->intrs[i] & type) { \ 68 reg |= (v) << i; \ 69 mask |= 1 << i; \ 70 } \ 71 } \ 72 VOP_INTR_SET(vop, name, mask, reg); \ 73 } while (0) 74 #define VOP_INTR_GET_TYPE(vop, name, type) \ 75 vop_get_intr_type(vop, &vop->data->intr->name, type) 76 77 #define VOP_WIN_GET(x, win, name) \ 78 vop_read_reg(x, win->base, &win->phy->name) 79 80 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 81 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 82 83 #define to_vop(x) container_of(x, struct vop, crtc) 84 #define to_vop_win(x) container_of(x, struct vop_win, base) 85 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base) 86 87 struct vop_plane_state { 88 struct drm_plane_state base; 89 int format; 90 struct drm_rect src; 91 struct drm_rect dest; 92 dma_addr_t yrgb_mst; 93 bool enable; 94 }; 95 96 struct vop_win { 97 struct drm_plane base; 98 const struct vop_win_data *data; 99 struct vop *vop; 100 101 /* protected by dev->event_lock */ 102 bool enable; 103 dma_addr_t yrgb_mst; 104 }; 105 106 struct vop { 107 struct drm_crtc crtc; 108 struct device *dev; 109 struct drm_device *drm_dev; 110 bool is_enabled; 111 112 /* mutex vsync_ work */ 113 struct mutex vsync_mutex; 114 bool vsync_work_pending; 115 struct completion dsp_hold_completion; 116 struct completion wait_update_complete; 117 118 /* protected by dev->event_lock */ 119 struct drm_pending_vblank_event *event; 120 121 const struct vop_data *data; 122 123 uint32_t *regsbak; 124 void __iomem *regs; 125 126 /* physical map length of vop register */ 127 uint32_t len; 128 129 /* one time only one process allowed to config the register */ 130 spinlock_t reg_lock; 131 /* lock vop irq reg */ 132 spinlock_t irq_lock; 133 134 unsigned int irq; 135 136 /* vop AHP clk */ 137 struct clk *hclk; 138 /* vop dclk */ 139 struct clk *dclk; 140 /* vop share memory frequency */ 141 struct clk *aclk; 142 143 /* vop dclk reset */ 144 struct reset_control *dclk_rst; 145 146 struct vop_win win[]; 147 }; 148 149 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 150 { 151 writel(v, vop->regs + offset); 152 vop->regsbak[offset >> 2] = v; 153 } 154 155 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 156 { 157 return readl(vop->regs + offset); 158 } 159 160 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 161 const struct vop_reg *reg) 162 { 163 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 164 } 165 166 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 167 uint32_t mask, uint32_t v) 168 { 169 if (mask) { 170 uint32_t cached_val = vop->regsbak[offset >> 2]; 171 172 cached_val = (cached_val & ~mask) | v; 173 writel(cached_val, vop->regs + offset); 174 vop->regsbak[offset >> 2] = cached_val; 175 } 176 } 177 178 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, 179 uint32_t mask, uint32_t v) 180 { 181 if (mask) { 182 uint32_t cached_val = vop->regsbak[offset >> 2]; 183 184 cached_val = (cached_val & ~mask) | v; 185 writel_relaxed(cached_val, vop->regs + offset); 186 vop->regsbak[offset >> 2] = cached_val; 187 } 188 } 189 190 static inline uint32_t vop_get_intr_type(struct vop *vop, 191 const struct vop_reg *reg, int type) 192 { 193 uint32_t i, ret = 0; 194 uint32_t regs = vop_read_reg(vop, 0, reg); 195 196 for (i = 0; i < vop->data->intr->nintrs; i++) { 197 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 198 ret |= vop->data->intr->intrs[i]; 199 } 200 201 return ret; 202 } 203 204 static inline void vop_cfg_done(struct vop *vop) 205 { 206 VOP_CTRL_SET(vop, cfg_done, 1); 207 } 208 209 static bool has_rb_swapped(uint32_t format) 210 { 211 switch (format) { 212 case DRM_FORMAT_XBGR8888: 213 case DRM_FORMAT_ABGR8888: 214 case DRM_FORMAT_BGR888: 215 case DRM_FORMAT_BGR565: 216 return true; 217 default: 218 return false; 219 } 220 } 221 222 static enum vop_data_format vop_convert_format(uint32_t format) 223 { 224 switch (format) { 225 case DRM_FORMAT_XRGB8888: 226 case DRM_FORMAT_ARGB8888: 227 case DRM_FORMAT_XBGR8888: 228 case DRM_FORMAT_ABGR8888: 229 return VOP_FMT_ARGB8888; 230 case DRM_FORMAT_RGB888: 231 case DRM_FORMAT_BGR888: 232 return VOP_FMT_RGB888; 233 case DRM_FORMAT_RGB565: 234 case DRM_FORMAT_BGR565: 235 return VOP_FMT_RGB565; 236 case DRM_FORMAT_NV12: 237 return VOP_FMT_YUV420SP; 238 case DRM_FORMAT_NV16: 239 return VOP_FMT_YUV422SP; 240 case DRM_FORMAT_NV24: 241 return VOP_FMT_YUV444SP; 242 default: 243 DRM_ERROR("unsupport format[%08x]\n", format); 244 return -EINVAL; 245 } 246 } 247 248 static bool is_yuv_support(uint32_t format) 249 { 250 switch (format) { 251 case DRM_FORMAT_NV12: 252 case DRM_FORMAT_NV16: 253 case DRM_FORMAT_NV24: 254 return true; 255 default: 256 return false; 257 } 258 } 259 260 static bool is_alpha_support(uint32_t format) 261 { 262 switch (format) { 263 case DRM_FORMAT_ARGB8888: 264 case DRM_FORMAT_ABGR8888: 265 return true; 266 default: 267 return false; 268 } 269 } 270 271 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 272 uint32_t dst, bool is_horizontal, 273 int vsu_mode, int *vskiplines) 274 { 275 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 276 277 if (is_horizontal) { 278 if (mode == SCALE_UP) 279 val = GET_SCL_FT_BIC(src, dst); 280 else if (mode == SCALE_DOWN) 281 val = GET_SCL_FT_BILI_DN(src, dst); 282 } else { 283 if (mode == SCALE_UP) { 284 if (vsu_mode == SCALE_UP_BIL) 285 val = GET_SCL_FT_BILI_UP(src, dst); 286 else 287 val = GET_SCL_FT_BIC(src, dst); 288 } else if (mode == SCALE_DOWN) { 289 if (vskiplines) { 290 *vskiplines = scl_get_vskiplines(src, dst); 291 val = scl_get_bili_dn_vskip(src, dst, 292 *vskiplines); 293 } else { 294 val = GET_SCL_FT_BILI_DN(src, dst); 295 } 296 } 297 } 298 299 return val; 300 } 301 302 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 303 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 304 uint32_t dst_h, uint32_t pixel_format) 305 { 306 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 307 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 308 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 309 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 310 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 311 bool is_yuv = is_yuv_support(pixel_format); 312 uint16_t cbcr_src_w = src_w / hsub; 313 uint16_t cbcr_src_h = src_h / vsub; 314 uint16_t vsu_mode; 315 uint16_t lb_mode; 316 uint32_t val; 317 int vskiplines = 0; 318 319 if (dst_w > 3840) { 320 DRM_ERROR("Maximum destination width (3840) exceeded\n"); 321 return; 322 } 323 324 if (!win->phy->scl->ext) { 325 VOP_SCL_SET(vop, win, scale_yrgb_x, 326 scl_cal_scale2(src_w, dst_w)); 327 VOP_SCL_SET(vop, win, scale_yrgb_y, 328 scl_cal_scale2(src_h, dst_h)); 329 if (is_yuv) { 330 VOP_SCL_SET(vop, win, scale_cbcr_x, 331 scl_cal_scale2(cbcr_src_w, dst_w)); 332 VOP_SCL_SET(vop, win, scale_cbcr_y, 333 scl_cal_scale2(cbcr_src_h, dst_h)); 334 } 335 return; 336 } 337 338 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 339 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 340 341 if (is_yuv) { 342 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 343 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 344 if (cbcr_hor_scl_mode == SCALE_DOWN) 345 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 346 else 347 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 348 } else { 349 if (yrgb_hor_scl_mode == SCALE_DOWN) 350 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 351 else 352 lb_mode = scl_vop_cal_lb_mode(src_w, false); 353 } 354 355 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 356 if (lb_mode == LB_RGB_3840X2) { 357 if (yrgb_ver_scl_mode != SCALE_NONE) { 358 DRM_ERROR("ERROR : not allow yrgb ver scale\n"); 359 return; 360 } 361 if (cbcr_ver_scl_mode != SCALE_NONE) { 362 DRM_ERROR("ERROR : not allow cbcr ver scale\n"); 363 return; 364 } 365 vsu_mode = SCALE_UP_BIL; 366 } else if (lb_mode == LB_RGB_2560X4) { 367 vsu_mode = SCALE_UP_BIL; 368 } else { 369 vsu_mode = SCALE_UP_BIC; 370 } 371 372 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 373 true, 0, NULL); 374 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 375 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 376 false, vsu_mode, &vskiplines); 377 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 378 379 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 380 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 381 382 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 383 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 384 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 385 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 386 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 387 if (is_yuv) { 388 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 389 dst_w, true, 0, NULL); 390 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 391 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 392 dst_h, false, vsu_mode, &vskiplines); 393 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 394 395 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 396 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 397 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 398 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 399 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 400 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 401 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 402 } 403 } 404 405 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 406 { 407 unsigned long flags; 408 409 if (WARN_ON(!vop->is_enabled)) 410 return; 411 412 spin_lock_irqsave(&vop->irq_lock, flags); 413 414 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 415 416 spin_unlock_irqrestore(&vop->irq_lock, flags); 417 } 418 419 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 420 { 421 unsigned long flags; 422 423 if (WARN_ON(!vop->is_enabled)) 424 return; 425 426 spin_lock_irqsave(&vop->irq_lock, flags); 427 428 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 429 430 spin_unlock_irqrestore(&vop->irq_lock, flags); 431 } 432 433 static void vop_enable(struct drm_crtc *crtc) 434 { 435 struct vop *vop = to_vop(crtc); 436 int ret; 437 438 ret = pm_runtime_get_sync(vop->dev); 439 if (ret < 0) { 440 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); 441 return; 442 } 443 444 ret = clk_enable(vop->hclk); 445 if (ret < 0) { 446 dev_err(vop->dev, "failed to enable hclk - %d\n", ret); 447 return; 448 } 449 450 ret = clk_enable(vop->dclk); 451 if (ret < 0) { 452 dev_err(vop->dev, "failed to enable dclk - %d\n", ret); 453 goto err_disable_hclk; 454 } 455 456 ret = clk_enable(vop->aclk); 457 if (ret < 0) { 458 dev_err(vop->dev, "failed to enable aclk - %d\n", ret); 459 goto err_disable_dclk; 460 } 461 462 /* 463 * Slave iommu shares power, irq and clock with vop. It was associated 464 * automatically with this master device via common driver code. 465 * Now that we have enabled the clock we attach it to the shared drm 466 * mapping. 467 */ 468 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 469 if (ret) { 470 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret); 471 goto err_disable_aclk; 472 } 473 474 memcpy(vop->regs, vop->regsbak, vop->len); 475 /* 476 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 477 */ 478 vop->is_enabled = true; 479 480 spin_lock(&vop->reg_lock); 481 482 VOP_CTRL_SET(vop, standby, 0); 483 484 spin_unlock(&vop->reg_lock); 485 486 enable_irq(vop->irq); 487 488 drm_crtc_vblank_on(crtc); 489 490 return; 491 492 err_disable_aclk: 493 clk_disable(vop->aclk); 494 err_disable_dclk: 495 clk_disable(vop->dclk); 496 err_disable_hclk: 497 clk_disable(vop->hclk); 498 } 499 500 static void vop_crtc_disable(struct drm_crtc *crtc) 501 { 502 struct vop *vop = to_vop(crtc); 503 int i; 504 505 WARN_ON(vop->event); 506 507 /* 508 * We need to make sure that all windows are disabled before we 509 * disable that crtc. Otherwise we might try to scan from a destroyed 510 * buffer later. 511 */ 512 for (i = 0; i < vop->data->win_size; i++) { 513 struct vop_win *vop_win = &vop->win[i]; 514 const struct vop_win_data *win = vop_win->data; 515 516 spin_lock(&vop->reg_lock); 517 VOP_WIN_SET(vop, win, enable, 0); 518 spin_unlock(&vop->reg_lock); 519 } 520 521 drm_crtc_vblank_off(crtc); 522 523 /* 524 * Vop standby will take effect at end of current frame, 525 * if dsp hold valid irq happen, it means standby complete. 526 * 527 * we must wait standby complete when we want to disable aclk, 528 * if not, memory bus maybe dead. 529 */ 530 reinit_completion(&vop->dsp_hold_completion); 531 vop_dsp_hold_valid_irq_enable(vop); 532 533 spin_lock(&vop->reg_lock); 534 535 VOP_CTRL_SET(vop, standby, 1); 536 537 spin_unlock(&vop->reg_lock); 538 539 wait_for_completion(&vop->dsp_hold_completion); 540 541 vop_dsp_hold_valid_irq_disable(vop); 542 543 disable_irq(vop->irq); 544 545 vop->is_enabled = false; 546 547 /* 548 * vop standby complete, so iommu detach is safe. 549 */ 550 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 551 552 clk_disable(vop->dclk); 553 clk_disable(vop->aclk); 554 clk_disable(vop->hclk); 555 pm_runtime_put(vop->dev); 556 557 if (crtc->state->event && !crtc->state->active) { 558 spin_lock_irq(&crtc->dev->event_lock); 559 drm_crtc_send_vblank_event(crtc, crtc->state->event); 560 spin_unlock_irq(&crtc->dev->event_lock); 561 562 crtc->state->event = NULL; 563 } 564 } 565 566 static void vop_plane_destroy(struct drm_plane *plane) 567 { 568 drm_plane_cleanup(plane); 569 } 570 571 static int vop_plane_prepare_fb(struct drm_plane *plane, 572 const struct drm_plane_state *new_state) 573 { 574 if (plane->state->fb) 575 drm_framebuffer_reference(plane->state->fb); 576 577 return 0; 578 } 579 580 static void vop_plane_cleanup_fb(struct drm_plane *plane, 581 const struct drm_plane_state *old_state) 582 { 583 if (old_state->fb) 584 drm_framebuffer_unreference(old_state->fb); 585 } 586 587 static int vop_plane_atomic_check(struct drm_plane *plane, 588 struct drm_plane_state *state) 589 { 590 struct drm_crtc *crtc = state->crtc; 591 struct drm_crtc_state *crtc_state; 592 struct drm_framebuffer *fb = state->fb; 593 struct vop_win *vop_win = to_vop_win(plane); 594 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 595 const struct vop_win_data *win = vop_win->data; 596 bool visible; 597 int ret; 598 struct drm_rect *dest = &vop_plane_state->dest; 599 struct drm_rect *src = &vop_plane_state->src; 600 struct drm_rect clip; 601 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 602 DRM_PLANE_HELPER_NO_SCALING; 603 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 604 DRM_PLANE_HELPER_NO_SCALING; 605 606 if (!crtc || !fb) 607 goto out_disable; 608 609 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 610 if (WARN_ON(!crtc_state)) 611 return -EINVAL; 612 613 src->x1 = state->src_x; 614 src->y1 = state->src_y; 615 src->x2 = state->src_x + state->src_w; 616 src->y2 = state->src_y + state->src_h; 617 dest->x1 = state->crtc_x; 618 dest->y1 = state->crtc_y; 619 dest->x2 = state->crtc_x + state->crtc_w; 620 dest->y2 = state->crtc_y + state->crtc_h; 621 622 clip.x1 = 0; 623 clip.y1 = 0; 624 clip.x2 = crtc_state->adjusted_mode.hdisplay; 625 clip.y2 = crtc_state->adjusted_mode.vdisplay; 626 627 ret = drm_plane_helper_check_update(plane, crtc, state->fb, 628 src, dest, &clip, 629 state->rotation, 630 min_scale, 631 max_scale, 632 true, true, &visible); 633 if (ret) 634 return ret; 635 636 if (!visible) 637 goto out_disable; 638 639 vop_plane_state->format = vop_convert_format(fb->pixel_format); 640 if (vop_plane_state->format < 0) 641 return vop_plane_state->format; 642 643 /* 644 * Src.x1 can be odd when do clip, but yuv plane start point 645 * need align with 2 pixel. 646 */ 647 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) 648 return -EINVAL; 649 650 vop_plane_state->enable = true; 651 652 return 0; 653 654 out_disable: 655 vop_plane_state->enable = false; 656 return 0; 657 } 658 659 static void vop_plane_atomic_disable(struct drm_plane *plane, 660 struct drm_plane_state *old_state) 661 { 662 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state); 663 struct vop_win *vop_win = to_vop_win(plane); 664 const struct vop_win_data *win = vop_win->data; 665 struct vop *vop = to_vop(old_state->crtc); 666 667 if (!old_state->crtc) 668 return; 669 670 spin_lock_irq(&plane->dev->event_lock); 671 vop_win->enable = false; 672 vop_win->yrgb_mst = 0; 673 spin_unlock_irq(&plane->dev->event_lock); 674 675 spin_lock(&vop->reg_lock); 676 677 VOP_WIN_SET(vop, win, enable, 0); 678 679 spin_unlock(&vop->reg_lock); 680 681 vop_plane_state->enable = false; 682 } 683 684 static void vop_plane_atomic_update(struct drm_plane *plane, 685 struct drm_plane_state *old_state) 686 { 687 struct drm_plane_state *state = plane->state; 688 struct drm_crtc *crtc = state->crtc; 689 struct vop_win *vop_win = to_vop_win(plane); 690 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state); 691 const struct vop_win_data *win = vop_win->data; 692 struct vop *vop = to_vop(state->crtc); 693 struct drm_framebuffer *fb = state->fb; 694 unsigned int actual_w, actual_h; 695 unsigned int dsp_stx, dsp_sty; 696 uint32_t act_info, dsp_info, dsp_st; 697 struct drm_rect *src = &vop_plane_state->src; 698 struct drm_rect *dest = &vop_plane_state->dest; 699 struct drm_gem_object *obj, *uv_obj; 700 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 701 unsigned long offset; 702 dma_addr_t dma_addr; 703 uint32_t val; 704 bool rb_swap; 705 706 /* 707 * can't update plane when vop is disabled. 708 */ 709 if (WARN_ON(!crtc)) 710 return; 711 712 if (WARN_ON(!vop->is_enabled)) 713 return; 714 715 if (!vop_plane_state->enable) { 716 vop_plane_atomic_disable(plane, old_state); 717 return; 718 } 719 720 obj = rockchip_fb_get_gem_obj(fb, 0); 721 rk_obj = to_rockchip_obj(obj); 722 723 actual_w = drm_rect_width(src) >> 16; 724 actual_h = drm_rect_height(src) >> 16; 725 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 726 727 dsp_info = (drm_rect_height(dest) - 1) << 16; 728 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 729 730 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 731 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 732 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 733 734 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0); 735 offset += (src->y1 >> 16) * fb->pitches[0]; 736 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; 737 738 spin_lock_irq(&plane->dev->event_lock); 739 vop_win->enable = true; 740 vop_win->yrgb_mst = vop_plane_state->yrgb_mst; 741 spin_unlock_irq(&plane->dev->event_lock); 742 743 spin_lock(&vop->reg_lock); 744 745 VOP_WIN_SET(vop, win, format, vop_plane_state->format); 746 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2); 747 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst); 748 if (is_yuv_support(fb->pixel_format)) { 749 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); 750 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); 751 int bpp = drm_format_plane_cpp(fb->pixel_format, 1); 752 753 uv_obj = rockchip_fb_get_gem_obj(fb, 1); 754 rk_uv_obj = to_rockchip_obj(uv_obj); 755 756 offset = (src->x1 >> 16) * bpp / hsub; 757 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 758 759 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 760 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2); 761 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 762 } 763 764 if (win->phy->scl) 765 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 766 drm_rect_width(dest), drm_rect_height(dest), 767 fb->pixel_format); 768 769 VOP_WIN_SET(vop, win, act_info, act_info); 770 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 771 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 772 773 rb_swap = has_rb_swapped(fb->pixel_format); 774 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 775 776 if (is_alpha_support(fb->pixel_format)) { 777 VOP_WIN_SET(vop, win, dst_alpha_ctl, 778 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 779 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 780 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 781 SRC_BLEND_M0(ALPHA_PER_PIX) | 782 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 783 SRC_FACTOR_M0(ALPHA_ONE); 784 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 785 } else { 786 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 787 } 788 789 VOP_WIN_SET(vop, win, enable, 1); 790 spin_unlock(&vop->reg_lock); 791 } 792 793 static const struct drm_plane_helper_funcs plane_helper_funcs = { 794 .prepare_fb = vop_plane_prepare_fb, 795 .cleanup_fb = vop_plane_cleanup_fb, 796 .atomic_check = vop_plane_atomic_check, 797 .atomic_update = vop_plane_atomic_update, 798 .atomic_disable = vop_plane_atomic_disable, 799 }; 800 801 static void vop_atomic_plane_reset(struct drm_plane *plane) 802 { 803 struct vop_plane_state *vop_plane_state = 804 to_vop_plane_state(plane->state); 805 806 if (plane->state && plane->state->fb) 807 drm_framebuffer_unreference(plane->state->fb); 808 809 kfree(vop_plane_state); 810 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL); 811 if (!vop_plane_state) 812 return; 813 814 plane->state = &vop_plane_state->base; 815 plane->state->plane = plane; 816 } 817 818 static struct drm_plane_state * 819 vop_atomic_plane_duplicate_state(struct drm_plane *plane) 820 { 821 struct vop_plane_state *old_vop_plane_state; 822 struct vop_plane_state *vop_plane_state; 823 824 if (WARN_ON(!plane->state)) 825 return NULL; 826 827 old_vop_plane_state = to_vop_plane_state(plane->state); 828 vop_plane_state = kmemdup(old_vop_plane_state, 829 sizeof(*vop_plane_state), GFP_KERNEL); 830 if (!vop_plane_state) 831 return NULL; 832 833 __drm_atomic_helper_plane_duplicate_state(plane, 834 &vop_plane_state->base); 835 836 return &vop_plane_state->base; 837 } 838 839 static void vop_atomic_plane_destroy_state(struct drm_plane *plane, 840 struct drm_plane_state *state) 841 { 842 struct vop_plane_state *vop_state = to_vop_plane_state(state); 843 844 __drm_atomic_helper_plane_destroy_state(state); 845 846 kfree(vop_state); 847 } 848 849 static const struct drm_plane_funcs vop_plane_funcs = { 850 .update_plane = drm_atomic_helper_update_plane, 851 .disable_plane = drm_atomic_helper_disable_plane, 852 .destroy = vop_plane_destroy, 853 .reset = vop_atomic_plane_reset, 854 .atomic_duplicate_state = vop_atomic_plane_duplicate_state, 855 .atomic_destroy_state = vop_atomic_plane_destroy_state, 856 }; 857 858 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 859 { 860 struct vop *vop = to_vop(crtc); 861 unsigned long flags; 862 863 if (WARN_ON(!vop->is_enabled)) 864 return -EPERM; 865 866 spin_lock_irqsave(&vop->irq_lock, flags); 867 868 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 869 870 spin_unlock_irqrestore(&vop->irq_lock, flags); 871 872 return 0; 873 } 874 875 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 876 { 877 struct vop *vop = to_vop(crtc); 878 unsigned long flags; 879 880 if (WARN_ON(!vop->is_enabled)) 881 return; 882 883 spin_lock_irqsave(&vop->irq_lock, flags); 884 885 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 886 887 spin_unlock_irqrestore(&vop->irq_lock, flags); 888 } 889 890 static void vop_crtc_wait_for_update(struct drm_crtc *crtc) 891 { 892 struct vop *vop = to_vop(crtc); 893 894 reinit_completion(&vop->wait_update_complete); 895 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100)); 896 } 897 898 static const struct rockchip_crtc_funcs private_crtc_funcs = { 899 .enable_vblank = vop_crtc_enable_vblank, 900 .disable_vblank = vop_crtc_disable_vblank, 901 .wait_for_update = vop_crtc_wait_for_update, 902 }; 903 904 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 905 const struct drm_display_mode *mode, 906 struct drm_display_mode *adjusted_mode) 907 { 908 struct vop *vop = to_vop(crtc); 909 910 adjusted_mode->clock = 911 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 912 913 return true; 914 } 915 916 static void vop_crtc_enable(struct drm_crtc *crtc) 917 { 918 struct vop *vop = to_vop(crtc); 919 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 920 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 921 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 922 u16 hdisplay = adjusted_mode->hdisplay; 923 u16 htotal = adjusted_mode->htotal; 924 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 925 u16 hact_end = hact_st + hdisplay; 926 u16 vdisplay = adjusted_mode->vdisplay; 927 u16 vtotal = adjusted_mode->vtotal; 928 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 929 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 930 u16 vact_end = vact_st + vdisplay; 931 uint32_t val; 932 933 WARN_ON(vop->event); 934 935 vop_enable(crtc); 936 /* 937 * If dclk rate is zero, mean that scanout is stop, 938 * we don't need wait any more. 939 */ 940 if (clk_get_rate(vop->dclk)) { 941 /* 942 * Rk3288 vop timing register is immediately, when configure 943 * display timing on display time, may cause tearing. 944 * 945 * Vop standby will take effect at end of current frame, 946 * if dsp hold valid irq happen, it means standby complete. 947 * 948 * mode set: 949 * standby and wait complete --> |---- 950 * | display time 951 * |---- 952 * |---> dsp hold irq 953 * configure display timing --> | 954 * standby exit | 955 * | new frame start. 956 */ 957 958 reinit_completion(&vop->dsp_hold_completion); 959 vop_dsp_hold_valid_irq_enable(vop); 960 961 spin_lock(&vop->reg_lock); 962 963 VOP_CTRL_SET(vop, standby, 1); 964 965 spin_unlock(&vop->reg_lock); 966 967 wait_for_completion(&vop->dsp_hold_completion); 968 969 vop_dsp_hold_valid_irq_disable(vop); 970 } 971 972 val = 0x8; 973 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 974 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 975 VOP_CTRL_SET(vop, pin_pol, val); 976 switch (s->output_type) { 977 case DRM_MODE_CONNECTOR_LVDS: 978 VOP_CTRL_SET(vop, rgb_en, 1); 979 break; 980 case DRM_MODE_CONNECTOR_eDP: 981 VOP_CTRL_SET(vop, edp_en, 1); 982 break; 983 case DRM_MODE_CONNECTOR_HDMIA: 984 VOP_CTRL_SET(vop, hdmi_en, 1); 985 break; 986 case DRM_MODE_CONNECTOR_DSI: 987 VOP_CTRL_SET(vop, mipi_en, 1); 988 break; 989 default: 990 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type); 991 } 992 VOP_CTRL_SET(vop, out_mode, s->output_mode); 993 994 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 995 val = hact_st << 16; 996 val |= hact_end; 997 VOP_CTRL_SET(vop, hact_st_end, val); 998 VOP_CTRL_SET(vop, hpost_st_end, val); 999 1000 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 1001 val = vact_st << 16; 1002 val |= vact_end; 1003 VOP_CTRL_SET(vop, vact_st_end, val); 1004 VOP_CTRL_SET(vop, vpost_st_end, val); 1005 1006 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1007 1008 VOP_CTRL_SET(vop, standby, 0); 1009 } 1010 1011 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1012 struct drm_crtc_state *old_crtc_state) 1013 { 1014 struct vop *vop = to_vop(crtc); 1015 1016 if (WARN_ON(!vop->is_enabled)) 1017 return; 1018 1019 spin_lock(&vop->reg_lock); 1020 1021 vop_cfg_done(vop); 1022 1023 spin_unlock(&vop->reg_lock); 1024 } 1025 1026 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1027 struct drm_crtc_state *old_crtc_state) 1028 { 1029 struct vop *vop = to_vop(crtc); 1030 1031 spin_lock_irq(&crtc->dev->event_lock); 1032 if (crtc->state->event) { 1033 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1034 WARN_ON(vop->event); 1035 1036 vop->event = crtc->state->event; 1037 crtc->state->event = NULL; 1038 } 1039 spin_unlock_irq(&crtc->dev->event_lock); 1040 } 1041 1042 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1043 .enable = vop_crtc_enable, 1044 .disable = vop_crtc_disable, 1045 .mode_fixup = vop_crtc_mode_fixup, 1046 .atomic_flush = vop_crtc_atomic_flush, 1047 .atomic_begin = vop_crtc_atomic_begin, 1048 }; 1049 1050 static void vop_crtc_destroy(struct drm_crtc *crtc) 1051 { 1052 drm_crtc_cleanup(crtc); 1053 } 1054 1055 static void vop_crtc_reset(struct drm_crtc *crtc) 1056 { 1057 if (crtc->state) 1058 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1059 kfree(crtc->state); 1060 1061 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1062 if (crtc->state) 1063 crtc->state->crtc = crtc; 1064 } 1065 1066 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1067 { 1068 struct rockchip_crtc_state *rockchip_state; 1069 1070 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1071 if (!rockchip_state) 1072 return NULL; 1073 1074 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1075 return &rockchip_state->base; 1076 } 1077 1078 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1079 struct drm_crtc_state *state) 1080 { 1081 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1082 1083 __drm_atomic_helper_crtc_destroy_state(&s->base); 1084 kfree(s); 1085 } 1086 1087 static const struct drm_crtc_funcs vop_crtc_funcs = { 1088 .set_config = drm_atomic_helper_set_config, 1089 .page_flip = drm_atomic_helper_page_flip, 1090 .destroy = vop_crtc_destroy, 1091 .reset = vop_crtc_reset, 1092 .atomic_duplicate_state = vop_crtc_duplicate_state, 1093 .atomic_destroy_state = vop_crtc_destroy_state, 1094 }; 1095 1096 static bool vop_win_pending_is_complete(struct vop_win *vop_win) 1097 { 1098 dma_addr_t yrgb_mst; 1099 1100 if (!vop_win->enable) 1101 return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0; 1102 1103 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data); 1104 1105 return yrgb_mst == vop_win->yrgb_mst; 1106 } 1107 1108 static void vop_handle_vblank(struct vop *vop) 1109 { 1110 struct drm_device *drm = vop->drm_dev; 1111 struct drm_crtc *crtc = &vop->crtc; 1112 unsigned long flags; 1113 int i; 1114 1115 for (i = 0; i < vop->data->win_size; i++) { 1116 if (!vop_win_pending_is_complete(&vop->win[i])) 1117 return; 1118 } 1119 1120 spin_lock_irqsave(&drm->event_lock, flags); 1121 if (vop->event) { 1122 1123 drm_crtc_send_vblank_event(crtc, vop->event); 1124 drm_crtc_vblank_put(crtc); 1125 vop->event = NULL; 1126 1127 } 1128 spin_unlock_irqrestore(&drm->event_lock, flags); 1129 1130 if (!completion_done(&vop->wait_update_complete)) 1131 complete(&vop->wait_update_complete); 1132 } 1133 1134 static irqreturn_t vop_isr(int irq, void *data) 1135 { 1136 struct vop *vop = data; 1137 struct drm_crtc *crtc = &vop->crtc; 1138 uint32_t active_irqs; 1139 unsigned long flags; 1140 int ret = IRQ_NONE; 1141 1142 /* 1143 * interrupt register has interrupt status, enable and clear bits, we 1144 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1145 */ 1146 spin_lock_irqsave(&vop->irq_lock, flags); 1147 1148 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1149 /* Clear all active interrupt sources */ 1150 if (active_irqs) 1151 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1152 1153 spin_unlock_irqrestore(&vop->irq_lock, flags); 1154 1155 /* This is expected for vop iommu irqs, since the irq is shared */ 1156 if (!active_irqs) 1157 return IRQ_NONE; 1158 1159 if (active_irqs & DSP_HOLD_VALID_INTR) { 1160 complete(&vop->dsp_hold_completion); 1161 active_irqs &= ~DSP_HOLD_VALID_INTR; 1162 ret = IRQ_HANDLED; 1163 } 1164 1165 if (active_irqs & FS_INTR) { 1166 drm_crtc_handle_vblank(crtc); 1167 vop_handle_vblank(vop); 1168 active_irqs &= ~FS_INTR; 1169 ret = IRQ_HANDLED; 1170 } 1171 1172 /* Unhandled irqs are spurious. */ 1173 if (active_irqs) 1174 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs); 1175 1176 return ret; 1177 } 1178 1179 static int vop_create_crtc(struct vop *vop) 1180 { 1181 const struct vop_data *vop_data = vop->data; 1182 struct device *dev = vop->dev; 1183 struct drm_device *drm_dev = vop->drm_dev; 1184 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1185 struct drm_crtc *crtc = &vop->crtc; 1186 struct device_node *port; 1187 int ret; 1188 int i; 1189 1190 /* 1191 * Create drm_plane for primary and cursor planes first, since we need 1192 * to pass them to drm_crtc_init_with_planes, which sets the 1193 * "possible_crtcs" to the newly initialized crtc. 1194 */ 1195 for (i = 0; i < vop_data->win_size; i++) { 1196 struct vop_win *vop_win = &vop->win[i]; 1197 const struct vop_win_data *win_data = vop_win->data; 1198 1199 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1200 win_data->type != DRM_PLANE_TYPE_CURSOR) 1201 continue; 1202 1203 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1204 0, &vop_plane_funcs, 1205 win_data->phy->data_formats, 1206 win_data->phy->nformats, 1207 win_data->type, NULL); 1208 if (ret) { 1209 DRM_ERROR("failed to initialize plane\n"); 1210 goto err_cleanup_planes; 1211 } 1212 1213 plane = &vop_win->base; 1214 drm_plane_helper_add(plane, &plane_helper_funcs); 1215 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1216 primary = plane; 1217 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1218 cursor = plane; 1219 } 1220 1221 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1222 &vop_crtc_funcs, NULL); 1223 if (ret) 1224 goto err_cleanup_planes; 1225 1226 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1227 1228 /* 1229 * Create drm_planes for overlay windows with possible_crtcs restricted 1230 * to the newly created crtc. 1231 */ 1232 for (i = 0; i < vop_data->win_size; i++) { 1233 struct vop_win *vop_win = &vop->win[i]; 1234 const struct vop_win_data *win_data = vop_win->data; 1235 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1236 1237 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1238 continue; 1239 1240 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1241 possible_crtcs, 1242 &vop_plane_funcs, 1243 win_data->phy->data_formats, 1244 win_data->phy->nformats, 1245 win_data->type, NULL); 1246 if (ret) { 1247 DRM_ERROR("failed to initialize overlay plane\n"); 1248 goto err_cleanup_crtc; 1249 } 1250 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1251 } 1252 1253 port = of_get_child_by_name(dev->of_node, "port"); 1254 if (!port) { 1255 DRM_ERROR("no port node found in %s\n", 1256 dev->of_node->full_name); 1257 ret = -ENOENT; 1258 goto err_cleanup_crtc; 1259 } 1260 1261 init_completion(&vop->dsp_hold_completion); 1262 init_completion(&vop->wait_update_complete); 1263 crtc->port = port; 1264 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs); 1265 1266 return 0; 1267 1268 err_cleanup_crtc: 1269 drm_crtc_cleanup(crtc); 1270 err_cleanup_planes: 1271 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1272 head) 1273 drm_plane_cleanup(plane); 1274 return ret; 1275 } 1276 1277 static void vop_destroy_crtc(struct vop *vop) 1278 { 1279 struct drm_crtc *crtc = &vop->crtc; 1280 struct drm_device *drm_dev = vop->drm_dev; 1281 struct drm_plane *plane, *tmp; 1282 1283 rockchip_unregister_crtc_funcs(crtc); 1284 of_node_put(crtc->port); 1285 1286 /* 1287 * We need to cleanup the planes now. Why? 1288 * 1289 * The planes are "&vop->win[i].base". That means the memory is 1290 * all part of the big "struct vop" chunk of memory. That memory 1291 * was devm allocated and associated with this component. We need to 1292 * free it ourselves before vop_unbind() finishes. 1293 */ 1294 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1295 head) 1296 vop_plane_destroy(plane); 1297 1298 /* 1299 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1300 * references the CRTC. 1301 */ 1302 drm_crtc_cleanup(crtc); 1303 } 1304 1305 static int vop_initial(struct vop *vop) 1306 { 1307 const struct vop_data *vop_data = vop->data; 1308 const struct vop_reg_data *init_table = vop_data->init_table; 1309 struct reset_control *ahb_rst; 1310 int i, ret; 1311 1312 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1313 if (IS_ERR(vop->hclk)) { 1314 dev_err(vop->dev, "failed to get hclk source\n"); 1315 return PTR_ERR(vop->hclk); 1316 } 1317 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1318 if (IS_ERR(vop->aclk)) { 1319 dev_err(vop->dev, "failed to get aclk source\n"); 1320 return PTR_ERR(vop->aclk); 1321 } 1322 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1323 if (IS_ERR(vop->dclk)) { 1324 dev_err(vop->dev, "failed to get dclk source\n"); 1325 return PTR_ERR(vop->dclk); 1326 } 1327 1328 ret = clk_prepare(vop->dclk); 1329 if (ret < 0) { 1330 dev_err(vop->dev, "failed to prepare dclk\n"); 1331 return ret; 1332 } 1333 1334 /* Enable both the hclk and aclk to setup the vop */ 1335 ret = clk_prepare_enable(vop->hclk); 1336 if (ret < 0) { 1337 dev_err(vop->dev, "failed to prepare/enable hclk\n"); 1338 goto err_unprepare_dclk; 1339 } 1340 1341 ret = clk_prepare_enable(vop->aclk); 1342 if (ret < 0) { 1343 dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1344 goto err_disable_hclk; 1345 } 1346 1347 /* 1348 * do hclk_reset, reset all vop registers. 1349 */ 1350 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1351 if (IS_ERR(ahb_rst)) { 1352 dev_err(vop->dev, "failed to get ahb reset\n"); 1353 ret = PTR_ERR(ahb_rst); 1354 goto err_disable_aclk; 1355 } 1356 reset_control_assert(ahb_rst); 1357 usleep_range(10, 20); 1358 reset_control_deassert(ahb_rst); 1359 1360 memcpy(vop->regsbak, vop->regs, vop->len); 1361 1362 for (i = 0; i < vop_data->table_size; i++) 1363 vop_writel(vop, init_table[i].offset, init_table[i].value); 1364 1365 for (i = 0; i < vop_data->win_size; i++) { 1366 const struct vop_win_data *win = &vop_data->win[i]; 1367 1368 VOP_WIN_SET(vop, win, enable, 0); 1369 } 1370 1371 vop_cfg_done(vop); 1372 1373 /* 1374 * do dclk_reset, let all config take affect. 1375 */ 1376 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1377 if (IS_ERR(vop->dclk_rst)) { 1378 dev_err(vop->dev, "failed to get dclk reset\n"); 1379 ret = PTR_ERR(vop->dclk_rst); 1380 goto err_disable_aclk; 1381 } 1382 reset_control_assert(vop->dclk_rst); 1383 usleep_range(10, 20); 1384 reset_control_deassert(vop->dclk_rst); 1385 1386 clk_disable(vop->hclk); 1387 clk_disable(vop->aclk); 1388 1389 vop->is_enabled = false; 1390 1391 return 0; 1392 1393 err_disable_aclk: 1394 clk_disable_unprepare(vop->aclk); 1395 err_disable_hclk: 1396 clk_disable_unprepare(vop->hclk); 1397 err_unprepare_dclk: 1398 clk_unprepare(vop->dclk); 1399 return ret; 1400 } 1401 1402 /* 1403 * Initialize the vop->win array elements. 1404 */ 1405 static void vop_win_init(struct vop *vop) 1406 { 1407 const struct vop_data *vop_data = vop->data; 1408 unsigned int i; 1409 1410 for (i = 0; i < vop_data->win_size; i++) { 1411 struct vop_win *vop_win = &vop->win[i]; 1412 const struct vop_win_data *win_data = &vop_data->win[i]; 1413 1414 vop_win->data = win_data; 1415 vop_win->vop = vop; 1416 } 1417 } 1418 1419 static int vop_bind(struct device *dev, struct device *master, void *data) 1420 { 1421 struct platform_device *pdev = to_platform_device(dev); 1422 const struct vop_data *vop_data; 1423 struct drm_device *drm_dev = data; 1424 struct vop *vop; 1425 struct resource *res; 1426 size_t alloc_size; 1427 int ret, irq; 1428 1429 vop_data = of_device_get_match_data(dev); 1430 if (!vop_data) 1431 return -ENODEV; 1432 1433 /* Allocate vop struct and its vop_win array */ 1434 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1435 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1436 if (!vop) 1437 return -ENOMEM; 1438 1439 vop->dev = dev; 1440 vop->data = vop_data; 1441 vop->drm_dev = drm_dev; 1442 dev_set_drvdata(dev, vop); 1443 1444 vop_win_init(vop); 1445 1446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1447 vop->len = resource_size(res); 1448 vop->regs = devm_ioremap_resource(dev, res); 1449 if (IS_ERR(vop->regs)) 1450 return PTR_ERR(vop->regs); 1451 1452 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1453 if (!vop->regsbak) 1454 return -ENOMEM; 1455 1456 ret = vop_initial(vop); 1457 if (ret < 0) { 1458 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret); 1459 return ret; 1460 } 1461 1462 irq = platform_get_irq(pdev, 0); 1463 if (irq < 0) { 1464 dev_err(dev, "cannot find irq for vop\n"); 1465 return irq; 1466 } 1467 vop->irq = (unsigned int)irq; 1468 1469 spin_lock_init(&vop->reg_lock); 1470 spin_lock_init(&vop->irq_lock); 1471 1472 mutex_init(&vop->vsync_mutex); 1473 1474 ret = devm_request_irq(dev, vop->irq, vop_isr, 1475 IRQF_SHARED, dev_name(dev), vop); 1476 if (ret) 1477 return ret; 1478 1479 /* IRQ is initially disabled; it gets enabled in power_on */ 1480 disable_irq(vop->irq); 1481 1482 ret = vop_create_crtc(vop); 1483 if (ret) 1484 return ret; 1485 1486 pm_runtime_enable(&pdev->dev); 1487 return 0; 1488 } 1489 1490 static void vop_unbind(struct device *dev, struct device *master, void *data) 1491 { 1492 struct vop *vop = dev_get_drvdata(dev); 1493 1494 pm_runtime_disable(dev); 1495 vop_destroy_crtc(vop); 1496 } 1497 1498 const struct component_ops vop_component_ops = { 1499 .bind = vop_bind, 1500 .unbind = vop_unbind, 1501 }; 1502 EXPORT_SYMBOL_GPL(vop_component_ops); 1503