1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_uapi.h> 19 #include <drm/drm_crtc.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_gem_framebuffer_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_probe_helper.h> 24 #ifdef CONFIG_DRM_ANALOGIX_DP 25 #include <drm/bridge/analogix_dp.h> 26 #endif 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/platform_device.h> 31 #include <linux/clk.h> 32 #include <linux/iopoll.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/component.h> 37 #include <linux/overflow.h> 38 39 #include <linux/reset.h> 40 #include <linux/delay.h> 41 42 #include "rockchip_drm_drv.h" 43 #include "rockchip_drm_gem.h" 44 #include "rockchip_drm_fb.h" 45 #include "rockchip_drm_psr.h" 46 #include "rockchip_drm_vop.h" 47 #include "rockchip_rgb.h" 48 49 #define VOP_WIN_SET(vop, win, name, v) \ 50 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 51 #define VOP_SCL_SET(vop, win, name, v) \ 52 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 53 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 54 vop_reg_set(vop, &win->phy->scl->ext->name, \ 55 win->base, ~0, v, #name) 56 57 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 58 do { \ 59 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 60 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 61 } while (0) 62 63 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 64 do { \ 65 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 66 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 67 } while (0) 68 69 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 70 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 71 72 #define VOP_REG_SET(vop, group, name, v) \ 73 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 74 75 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 76 do { \ 77 int i, reg = 0, mask = 0; \ 78 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 79 if (vop->data->intr->intrs[i] & type) { \ 80 reg |= (v) << i; \ 81 mask |= 1 << i; \ 82 } \ 83 } \ 84 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 85 } while (0) 86 #define VOP_INTR_GET_TYPE(vop, name, type) \ 87 vop_get_intr_type(vop, &vop->data->intr->name, type) 88 89 #define VOP_WIN_GET(vop, win, name) \ 90 vop_read_reg(vop, win->offset, win->phy->name) 91 92 #define VOP_WIN_HAS_REG(win, name) \ 93 (!!(win->phy->name.mask)) 94 95 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 96 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 97 98 #define VOP_WIN_TO_INDEX(vop_win) \ 99 ((vop_win) - (vop_win)->vop->win) 100 101 #define to_vop(x) container_of(x, struct vop, crtc) 102 #define to_vop_win(x) container_of(x, struct vop_win, base) 103 104 /* 105 * The coefficients of the following matrix are all fixed points. 106 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 107 * They are all represented in two's complement. 108 */ 109 static const uint32_t bt601_yuv2rgb[] = { 110 0x4A8, 0x0, 0x662, 111 0x4A8, 0x1E6F, 0x1CBF, 112 0x4A8, 0x812, 0x0, 113 0x321168, 0x0877CF, 0x2EB127 114 }; 115 116 enum vop_pending { 117 VOP_PENDING_FB_UNREF, 118 }; 119 120 struct vop_win { 121 struct drm_plane base; 122 const struct vop_win_data *data; 123 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 124 struct vop *vop; 125 }; 126 127 struct rockchip_rgb; 128 struct vop { 129 struct drm_crtc crtc; 130 struct device *dev; 131 struct drm_device *drm_dev; 132 bool is_enabled; 133 134 struct completion dsp_hold_completion; 135 136 /* protected by dev->event_lock */ 137 struct drm_pending_vblank_event *event; 138 139 struct drm_flip_work fb_unref_work; 140 unsigned long pending; 141 142 struct completion line_flag_completion; 143 144 const struct vop_data *data; 145 146 uint32_t *regsbak; 147 void __iomem *regs; 148 149 /* physical map length of vop register */ 150 uint32_t len; 151 152 /* one time only one process allowed to config the register */ 153 spinlock_t reg_lock; 154 /* lock vop irq reg */ 155 spinlock_t irq_lock; 156 /* protects crtc enable/disable */ 157 struct mutex vop_lock; 158 159 unsigned int irq; 160 161 /* vop AHP clk */ 162 struct clk *hclk; 163 /* vop dclk */ 164 struct clk *dclk; 165 /* vop share memory frequency */ 166 struct clk *aclk; 167 168 /* vop dclk reset */ 169 struct reset_control *dclk_rst; 170 171 /* optional internal rgb encoder */ 172 struct rockchip_rgb *rgb; 173 174 struct vop_win win[]; 175 }; 176 177 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 178 { 179 writel(v, vop->regs + offset); 180 vop->regsbak[offset >> 2] = v; 181 } 182 183 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 184 { 185 return readl(vop->regs + offset); 186 } 187 188 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 189 const struct vop_reg *reg) 190 { 191 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 192 } 193 194 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 195 uint32_t _offset, uint32_t _mask, uint32_t v, 196 const char *reg_name) 197 { 198 int offset, mask, shift; 199 200 if (!reg || !reg->mask) { 201 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 202 return; 203 } 204 205 offset = reg->offset + _offset; 206 mask = reg->mask & _mask; 207 shift = reg->shift; 208 209 if (reg->write_mask) { 210 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 211 } else { 212 uint32_t cached_val = vop->regsbak[offset >> 2]; 213 214 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 215 vop->regsbak[offset >> 2] = v; 216 } 217 218 if (reg->relaxed) 219 writel_relaxed(v, vop->regs + offset); 220 else 221 writel(v, vop->regs + offset); 222 } 223 224 static inline uint32_t vop_get_intr_type(struct vop *vop, 225 const struct vop_reg *reg, int type) 226 { 227 uint32_t i, ret = 0; 228 uint32_t regs = vop_read_reg(vop, 0, reg); 229 230 for (i = 0; i < vop->data->intr->nintrs; i++) { 231 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 232 ret |= vop->data->intr->intrs[i]; 233 } 234 235 return ret; 236 } 237 238 static inline void vop_cfg_done(struct vop *vop) 239 { 240 VOP_REG_SET(vop, common, cfg_done, 1); 241 } 242 243 static bool has_rb_swapped(uint32_t format) 244 { 245 switch (format) { 246 case DRM_FORMAT_XBGR8888: 247 case DRM_FORMAT_ABGR8888: 248 case DRM_FORMAT_BGR888: 249 case DRM_FORMAT_BGR565: 250 return true; 251 default: 252 return false; 253 } 254 } 255 256 static enum vop_data_format vop_convert_format(uint32_t format) 257 { 258 switch (format) { 259 case DRM_FORMAT_XRGB8888: 260 case DRM_FORMAT_ARGB8888: 261 case DRM_FORMAT_XBGR8888: 262 case DRM_FORMAT_ABGR8888: 263 return VOP_FMT_ARGB8888; 264 case DRM_FORMAT_RGB888: 265 case DRM_FORMAT_BGR888: 266 return VOP_FMT_RGB888; 267 case DRM_FORMAT_RGB565: 268 case DRM_FORMAT_BGR565: 269 return VOP_FMT_RGB565; 270 case DRM_FORMAT_NV12: 271 return VOP_FMT_YUV420SP; 272 case DRM_FORMAT_NV16: 273 return VOP_FMT_YUV422SP; 274 case DRM_FORMAT_NV24: 275 return VOP_FMT_YUV444SP; 276 default: 277 DRM_ERROR("unsupported format[%08x]\n", format); 278 return -EINVAL; 279 } 280 } 281 282 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 283 uint32_t dst, bool is_horizontal, 284 int vsu_mode, int *vskiplines) 285 { 286 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 287 288 if (vskiplines) 289 *vskiplines = 0; 290 291 if (is_horizontal) { 292 if (mode == SCALE_UP) 293 val = GET_SCL_FT_BIC(src, dst); 294 else if (mode == SCALE_DOWN) 295 val = GET_SCL_FT_BILI_DN(src, dst); 296 } else { 297 if (mode == SCALE_UP) { 298 if (vsu_mode == SCALE_UP_BIL) 299 val = GET_SCL_FT_BILI_UP(src, dst); 300 else 301 val = GET_SCL_FT_BIC(src, dst); 302 } else if (mode == SCALE_DOWN) { 303 if (vskiplines) { 304 *vskiplines = scl_get_vskiplines(src, dst); 305 val = scl_get_bili_dn_vskip(src, dst, 306 *vskiplines); 307 } else { 308 val = GET_SCL_FT_BILI_DN(src, dst); 309 } 310 } 311 } 312 313 return val; 314 } 315 316 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 317 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 318 uint32_t dst_h, const struct drm_format_info *info) 319 { 320 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 321 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 322 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 323 bool is_yuv = false; 324 uint16_t cbcr_src_w = src_w / info->hsub; 325 uint16_t cbcr_src_h = src_h / info->vsub; 326 uint16_t vsu_mode; 327 uint16_t lb_mode; 328 uint32_t val; 329 int vskiplines; 330 331 if (info->is_yuv) 332 is_yuv = true; 333 334 if (dst_w > 3840) { 335 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 336 return; 337 } 338 339 if (!win->phy->scl->ext) { 340 VOP_SCL_SET(vop, win, scale_yrgb_x, 341 scl_cal_scale2(src_w, dst_w)); 342 VOP_SCL_SET(vop, win, scale_yrgb_y, 343 scl_cal_scale2(src_h, dst_h)); 344 if (is_yuv) { 345 VOP_SCL_SET(vop, win, scale_cbcr_x, 346 scl_cal_scale2(cbcr_src_w, dst_w)); 347 VOP_SCL_SET(vop, win, scale_cbcr_y, 348 scl_cal_scale2(cbcr_src_h, dst_h)); 349 } 350 return; 351 } 352 353 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 354 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 355 356 if (is_yuv) { 357 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 358 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 359 if (cbcr_hor_scl_mode == SCALE_DOWN) 360 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 361 else 362 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 363 } else { 364 if (yrgb_hor_scl_mode == SCALE_DOWN) 365 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 366 else 367 lb_mode = scl_vop_cal_lb_mode(src_w, false); 368 } 369 370 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 371 if (lb_mode == LB_RGB_3840X2) { 372 if (yrgb_ver_scl_mode != SCALE_NONE) { 373 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 374 return; 375 } 376 if (cbcr_ver_scl_mode != SCALE_NONE) { 377 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 378 return; 379 } 380 vsu_mode = SCALE_UP_BIL; 381 } else if (lb_mode == LB_RGB_2560X4) { 382 vsu_mode = SCALE_UP_BIL; 383 } else { 384 vsu_mode = SCALE_UP_BIC; 385 } 386 387 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 388 true, 0, NULL); 389 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 390 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 391 false, vsu_mode, &vskiplines); 392 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 393 394 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 395 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 396 397 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 398 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 399 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 400 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 401 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 402 if (is_yuv) { 403 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 404 dst_w, true, 0, NULL); 405 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 406 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 407 dst_h, false, vsu_mode, &vskiplines); 408 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 409 410 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 411 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 412 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 413 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 414 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 415 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 416 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 417 } 418 } 419 420 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 421 { 422 unsigned long flags; 423 424 if (WARN_ON(!vop->is_enabled)) 425 return; 426 427 spin_lock_irqsave(&vop->irq_lock, flags); 428 429 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 430 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 431 432 spin_unlock_irqrestore(&vop->irq_lock, flags); 433 } 434 435 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 436 { 437 unsigned long flags; 438 439 if (WARN_ON(!vop->is_enabled)) 440 return; 441 442 spin_lock_irqsave(&vop->irq_lock, flags); 443 444 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 445 446 spin_unlock_irqrestore(&vop->irq_lock, flags); 447 } 448 449 /* 450 * (1) each frame starts at the start of the Vsync pulse which is signaled by 451 * the "FRAME_SYNC" interrupt. 452 * (2) the active data region of each frame ends at dsp_vact_end 453 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 454 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 455 * 456 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 457 * Interrupts 458 * LINE_FLAG -------------------------------+ 459 * FRAME_SYNC ----+ | 460 * | | 461 * v v 462 * | Vsync | Vbp | Vactive | Vfp | 463 * ^ ^ ^ ^ 464 * | | | | 465 * | | | | 466 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 467 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 468 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 469 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 470 */ 471 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 472 { 473 uint32_t line_flag_irq; 474 unsigned long flags; 475 476 spin_lock_irqsave(&vop->irq_lock, flags); 477 478 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 479 480 spin_unlock_irqrestore(&vop->irq_lock, flags); 481 482 return !!line_flag_irq; 483 } 484 485 static void vop_line_flag_irq_enable(struct vop *vop) 486 { 487 unsigned long flags; 488 489 if (WARN_ON(!vop->is_enabled)) 490 return; 491 492 spin_lock_irqsave(&vop->irq_lock, flags); 493 494 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 495 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 496 497 spin_unlock_irqrestore(&vop->irq_lock, flags); 498 } 499 500 static void vop_line_flag_irq_disable(struct vop *vop) 501 { 502 unsigned long flags; 503 504 if (WARN_ON(!vop->is_enabled)) 505 return; 506 507 spin_lock_irqsave(&vop->irq_lock, flags); 508 509 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 510 511 spin_unlock_irqrestore(&vop->irq_lock, flags); 512 } 513 514 static int vop_core_clks_enable(struct vop *vop) 515 { 516 int ret; 517 518 ret = clk_enable(vop->hclk); 519 if (ret < 0) 520 return ret; 521 522 ret = clk_enable(vop->aclk); 523 if (ret < 0) 524 goto err_disable_hclk; 525 526 return 0; 527 528 err_disable_hclk: 529 clk_disable(vop->hclk); 530 return ret; 531 } 532 533 static void vop_core_clks_disable(struct vop *vop) 534 { 535 clk_disable(vop->aclk); 536 clk_disable(vop->hclk); 537 } 538 539 static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) 540 { 541 if (win->phy->scl && win->phy->scl->ext) { 542 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 543 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 544 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 545 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 546 } 547 548 VOP_WIN_SET(vop, win, enable, 0); 549 } 550 551 static int vop_enable(struct drm_crtc *crtc) 552 { 553 struct vop *vop = to_vop(crtc); 554 int ret, i; 555 556 ret = pm_runtime_get_sync(vop->dev); 557 if (ret < 0) { 558 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 559 return ret; 560 } 561 562 ret = vop_core_clks_enable(vop); 563 if (WARN_ON(ret < 0)) 564 goto err_put_pm_runtime; 565 566 ret = clk_enable(vop->dclk); 567 if (WARN_ON(ret < 0)) 568 goto err_disable_core; 569 570 /* 571 * Slave iommu shares power, irq and clock with vop. It was associated 572 * automatically with this master device via common driver code. 573 * Now that we have enabled the clock we attach it to the shared drm 574 * mapping. 575 */ 576 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 577 if (ret) { 578 DRM_DEV_ERROR(vop->dev, 579 "failed to attach dma mapping, %d\n", ret); 580 goto err_disable_dclk; 581 } 582 583 spin_lock(&vop->reg_lock); 584 for (i = 0; i < vop->len; i += 4) 585 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 586 587 /* 588 * We need to make sure that all windows are disabled before we 589 * enable the crtc. Otherwise we might try to scan from a destroyed 590 * buffer later. 591 */ 592 for (i = 0; i < vop->data->win_size; i++) { 593 struct vop_win *vop_win = &vop->win[i]; 594 const struct vop_win_data *win = vop_win->data; 595 596 vop_win_disable(vop, win); 597 } 598 spin_unlock(&vop->reg_lock); 599 600 vop_cfg_done(vop); 601 602 /* 603 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 604 */ 605 vop->is_enabled = true; 606 607 spin_lock(&vop->reg_lock); 608 609 VOP_REG_SET(vop, common, standby, 1); 610 611 spin_unlock(&vop->reg_lock); 612 613 drm_crtc_vblank_on(crtc); 614 615 return 0; 616 617 err_disable_dclk: 618 clk_disable(vop->dclk); 619 err_disable_core: 620 vop_core_clks_disable(vop); 621 err_put_pm_runtime: 622 pm_runtime_put_sync(vop->dev); 623 return ret; 624 } 625 626 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 627 struct drm_crtc_state *old_state) 628 { 629 struct vop *vop = to_vop(crtc); 630 631 WARN_ON(vop->event); 632 633 mutex_lock(&vop->vop_lock); 634 drm_crtc_vblank_off(crtc); 635 636 /* 637 * Vop standby will take effect at end of current frame, 638 * if dsp hold valid irq happen, it means standby complete. 639 * 640 * we must wait standby complete when we want to disable aclk, 641 * if not, memory bus maybe dead. 642 */ 643 reinit_completion(&vop->dsp_hold_completion); 644 vop_dsp_hold_valid_irq_enable(vop); 645 646 spin_lock(&vop->reg_lock); 647 648 VOP_REG_SET(vop, common, standby, 1); 649 650 spin_unlock(&vop->reg_lock); 651 652 wait_for_completion(&vop->dsp_hold_completion); 653 654 vop_dsp_hold_valid_irq_disable(vop); 655 656 vop->is_enabled = false; 657 658 /* 659 * vop standby complete, so iommu detach is safe. 660 */ 661 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 662 663 clk_disable(vop->dclk); 664 vop_core_clks_disable(vop); 665 pm_runtime_put(vop->dev); 666 mutex_unlock(&vop->vop_lock); 667 668 if (crtc->state->event && !crtc->state->active) { 669 spin_lock_irq(&crtc->dev->event_lock); 670 drm_crtc_send_vblank_event(crtc, crtc->state->event); 671 spin_unlock_irq(&crtc->dev->event_lock); 672 673 crtc->state->event = NULL; 674 } 675 } 676 677 static void vop_plane_destroy(struct drm_plane *plane) 678 { 679 drm_plane_cleanup(plane); 680 } 681 682 static int vop_plane_atomic_check(struct drm_plane *plane, 683 struct drm_plane_state *state) 684 { 685 struct drm_crtc *crtc = state->crtc; 686 struct drm_crtc_state *crtc_state; 687 struct drm_framebuffer *fb = state->fb; 688 struct vop_win *vop_win = to_vop_win(plane); 689 const struct vop_win_data *win = vop_win->data; 690 int ret; 691 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 692 DRM_PLANE_HELPER_NO_SCALING; 693 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 694 DRM_PLANE_HELPER_NO_SCALING; 695 696 if (!crtc || !fb) 697 return 0; 698 699 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 700 if (WARN_ON(!crtc_state)) 701 return -EINVAL; 702 703 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 704 min_scale, max_scale, 705 true, true); 706 if (ret) 707 return ret; 708 709 if (!state->visible) 710 return 0; 711 712 ret = vop_convert_format(fb->format->format); 713 if (ret < 0) 714 return ret; 715 716 /* 717 * Src.x1 can be odd when do clip, but yuv plane start point 718 * need align with 2 pixel. 719 */ 720 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 721 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 722 return -EINVAL; 723 } 724 725 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 726 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 727 return -EINVAL; 728 } 729 730 return 0; 731 } 732 733 static void vop_plane_atomic_disable(struct drm_plane *plane, 734 struct drm_plane_state *old_state) 735 { 736 struct vop_win *vop_win = to_vop_win(plane); 737 const struct vop_win_data *win = vop_win->data; 738 struct vop *vop = to_vop(old_state->crtc); 739 740 if (!old_state->crtc) 741 return; 742 743 spin_lock(&vop->reg_lock); 744 745 vop_win_disable(vop, win); 746 747 spin_unlock(&vop->reg_lock); 748 } 749 750 static void vop_plane_atomic_update(struct drm_plane *plane, 751 struct drm_plane_state *old_state) 752 { 753 struct drm_plane_state *state = plane->state; 754 struct drm_crtc *crtc = state->crtc; 755 struct vop_win *vop_win = to_vop_win(plane); 756 const struct vop_win_data *win = vop_win->data; 757 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 758 struct vop *vop = to_vop(state->crtc); 759 struct drm_framebuffer *fb = state->fb; 760 unsigned int actual_w, actual_h; 761 unsigned int dsp_stx, dsp_sty; 762 uint32_t act_info, dsp_info, dsp_st; 763 struct drm_rect *src = &state->src; 764 struct drm_rect *dest = &state->dst; 765 struct drm_gem_object *obj, *uv_obj; 766 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 767 unsigned long offset; 768 dma_addr_t dma_addr; 769 uint32_t val; 770 bool rb_swap; 771 int win_index = VOP_WIN_TO_INDEX(vop_win); 772 int format; 773 int is_yuv = fb->format->is_yuv; 774 int i; 775 776 /* 777 * can't update plane when vop is disabled. 778 */ 779 if (WARN_ON(!crtc)) 780 return; 781 782 if (WARN_ON(!vop->is_enabled)) 783 return; 784 785 if (!state->visible) { 786 vop_plane_atomic_disable(plane, old_state); 787 return; 788 } 789 790 obj = fb->obj[0]; 791 rk_obj = to_rockchip_obj(obj); 792 793 actual_w = drm_rect_width(src) >> 16; 794 actual_h = drm_rect_height(src) >> 16; 795 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 796 797 dsp_info = (drm_rect_height(dest) - 1) << 16; 798 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 799 800 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 801 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 802 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 803 804 offset = (src->x1 >> 16) * fb->format->cpp[0]; 805 offset += (src->y1 >> 16) * fb->pitches[0]; 806 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 807 808 /* 809 * For y-mirroring we need to move address 810 * to the beginning of the last line. 811 */ 812 if (state->rotation & DRM_MODE_REFLECT_Y) 813 dma_addr += (actual_h - 1) * fb->pitches[0]; 814 815 format = vop_convert_format(fb->format->format); 816 817 spin_lock(&vop->reg_lock); 818 819 VOP_WIN_SET(vop, win, format, format); 820 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 821 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 822 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 823 VOP_WIN_SET(vop, win, y_mir_en, 824 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 825 VOP_WIN_SET(vop, win, x_mir_en, 826 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 827 828 if (is_yuv) { 829 int hsub = fb->format->hsub; 830 int vsub = fb->format->vsub; 831 int bpp = fb->format->cpp[1]; 832 833 uv_obj = fb->obj[1]; 834 rk_uv_obj = to_rockchip_obj(uv_obj); 835 836 offset = (src->x1 >> 16) * bpp / hsub; 837 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 838 839 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 840 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 841 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 842 843 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 844 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 845 win_yuv2yuv, 846 y2r_coefficients[i], 847 bt601_yuv2rgb[i]); 848 } 849 } 850 851 if (win->phy->scl) 852 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 853 drm_rect_width(dest), drm_rect_height(dest), 854 fb->format); 855 856 VOP_WIN_SET(vop, win, act_info, act_info); 857 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 858 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 859 860 rb_swap = has_rb_swapped(fb->format->format); 861 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 862 863 /* 864 * Blending win0 with the background color doesn't seem to work 865 * correctly. We only get the background color, no matter the contents 866 * of the win0 framebuffer. However, blending pre-multiplied color 867 * with the default opaque black default background color is a no-op, 868 * so we can just disable blending to get the correct result. 869 */ 870 if (fb->format->has_alpha && win_index > 0) { 871 VOP_WIN_SET(vop, win, dst_alpha_ctl, 872 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 873 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 874 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 875 SRC_BLEND_M0(ALPHA_PER_PIX) | 876 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 877 SRC_FACTOR_M0(ALPHA_ONE); 878 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 879 } else { 880 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 881 } 882 883 VOP_WIN_SET(vop, win, enable, 1); 884 spin_unlock(&vop->reg_lock); 885 } 886 887 static int vop_plane_atomic_async_check(struct drm_plane *plane, 888 struct drm_plane_state *state) 889 { 890 struct vop_win *vop_win = to_vop_win(plane); 891 const struct vop_win_data *win = vop_win->data; 892 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 893 DRM_PLANE_HELPER_NO_SCALING; 894 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 895 DRM_PLANE_HELPER_NO_SCALING; 896 struct drm_crtc_state *crtc_state; 897 898 if (plane != state->crtc->cursor) 899 return -EINVAL; 900 901 if (!plane->state) 902 return -EINVAL; 903 904 if (!plane->state->fb) 905 return -EINVAL; 906 907 if (state->state) 908 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 909 state->crtc); 910 else /* Special case for asynchronous cursor updates. */ 911 crtc_state = plane->crtc->state; 912 913 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 914 min_scale, max_scale, 915 true, true); 916 } 917 918 static void vop_plane_atomic_async_update(struct drm_plane *plane, 919 struct drm_plane_state *new_state) 920 { 921 struct vop *vop = to_vop(plane->state->crtc); 922 struct drm_plane_state *plane_state; 923 924 plane_state = plane->funcs->atomic_duplicate_state(plane); 925 plane_state->crtc_x = new_state->crtc_x; 926 plane_state->crtc_y = new_state->crtc_y; 927 plane_state->crtc_h = new_state->crtc_h; 928 plane_state->crtc_w = new_state->crtc_w; 929 plane_state->src_x = new_state->src_x; 930 plane_state->src_y = new_state->src_y; 931 plane_state->src_h = new_state->src_h; 932 plane_state->src_w = new_state->src_w; 933 934 if (plane_state->fb != new_state->fb) 935 drm_atomic_set_fb_for_plane(plane_state, new_state->fb); 936 937 swap(plane_state, plane->state); 938 939 if (plane->state->fb && plane->state->fb != new_state->fb) { 940 drm_framebuffer_get(plane->state->fb); 941 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 942 drm_flip_work_queue(&vop->fb_unref_work, plane->state->fb); 943 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 944 } 945 946 if (vop->is_enabled) { 947 rockchip_drm_psr_inhibit_get_state(new_state->state); 948 vop_plane_atomic_update(plane, plane->state); 949 spin_lock(&vop->reg_lock); 950 vop_cfg_done(vop); 951 spin_unlock(&vop->reg_lock); 952 rockchip_drm_psr_inhibit_put_state(new_state->state); 953 } 954 955 plane->funcs->atomic_destroy_state(plane, plane_state); 956 } 957 958 static const struct drm_plane_helper_funcs plane_helper_funcs = { 959 .atomic_check = vop_plane_atomic_check, 960 .atomic_update = vop_plane_atomic_update, 961 .atomic_disable = vop_plane_atomic_disable, 962 .atomic_async_check = vop_plane_atomic_async_check, 963 .atomic_async_update = vop_plane_atomic_async_update, 964 .prepare_fb = drm_gem_fb_prepare_fb, 965 }; 966 967 static const struct drm_plane_funcs vop_plane_funcs = { 968 .update_plane = drm_atomic_helper_update_plane, 969 .disable_plane = drm_atomic_helper_disable_plane, 970 .destroy = vop_plane_destroy, 971 .reset = drm_atomic_helper_plane_reset, 972 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 973 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 974 }; 975 976 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 977 { 978 struct vop *vop = to_vop(crtc); 979 unsigned long flags; 980 981 if (WARN_ON(!vop->is_enabled)) 982 return -EPERM; 983 984 spin_lock_irqsave(&vop->irq_lock, flags); 985 986 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 987 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 988 989 spin_unlock_irqrestore(&vop->irq_lock, flags); 990 991 return 0; 992 } 993 994 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 995 { 996 struct vop *vop = to_vop(crtc); 997 unsigned long flags; 998 999 if (WARN_ON(!vop->is_enabled)) 1000 return; 1001 1002 spin_lock_irqsave(&vop->irq_lock, flags); 1003 1004 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1005 1006 spin_unlock_irqrestore(&vop->irq_lock, flags); 1007 } 1008 1009 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1010 const struct drm_display_mode *mode, 1011 struct drm_display_mode *adjusted_mode) 1012 { 1013 struct vop *vop = to_vop(crtc); 1014 1015 adjusted_mode->clock = 1016 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 1017 1018 return true; 1019 } 1020 1021 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1022 struct drm_crtc_state *old_state) 1023 { 1024 struct vop *vop = to_vop(crtc); 1025 const struct vop_data *vop_data = vop->data; 1026 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1027 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1028 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1029 u16 hdisplay = adjusted_mode->hdisplay; 1030 u16 htotal = adjusted_mode->htotal; 1031 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1032 u16 hact_end = hact_st + hdisplay; 1033 u16 vdisplay = adjusted_mode->vdisplay; 1034 u16 vtotal = adjusted_mode->vtotal; 1035 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1036 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1037 u16 vact_end = vact_st + vdisplay; 1038 uint32_t pin_pol, val; 1039 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1040 int ret; 1041 1042 mutex_lock(&vop->vop_lock); 1043 1044 WARN_ON(vop->event); 1045 1046 ret = vop_enable(crtc); 1047 if (ret) { 1048 mutex_unlock(&vop->vop_lock); 1049 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1050 return; 1051 } 1052 1053 pin_pol = BIT(DCLK_INVERT); 1054 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1055 BIT(HSYNC_POSITIVE) : 0; 1056 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1057 BIT(VSYNC_POSITIVE) : 0; 1058 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1059 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1060 1061 switch (s->output_type) { 1062 case DRM_MODE_CONNECTOR_LVDS: 1063 VOP_REG_SET(vop, output, rgb_en, 1); 1064 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1065 break; 1066 case DRM_MODE_CONNECTOR_eDP: 1067 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1068 VOP_REG_SET(vop, output, edp_en, 1); 1069 break; 1070 case DRM_MODE_CONNECTOR_HDMIA: 1071 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1072 VOP_REG_SET(vop, output, hdmi_en, 1); 1073 break; 1074 case DRM_MODE_CONNECTOR_DSI: 1075 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1076 VOP_REG_SET(vop, output, mipi_en, 1); 1077 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1078 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1079 break; 1080 case DRM_MODE_CONNECTOR_DisplayPort: 1081 pin_pol &= ~BIT(DCLK_INVERT); 1082 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1083 VOP_REG_SET(vop, output, dp_en, 1); 1084 break; 1085 default: 1086 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1087 s->output_type); 1088 } 1089 1090 /* 1091 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1092 */ 1093 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1094 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1095 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1096 1097 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1098 VOP_REG_SET(vop, common, pre_dither_down, 1); 1099 else 1100 VOP_REG_SET(vop, common, pre_dither_down, 0); 1101 1102 if (dither_bpc == 6) { 1103 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1104 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1105 VOP_REG_SET(vop, common, dither_down_en, 1); 1106 } else { 1107 VOP_REG_SET(vop, common, dither_down_en, 0); 1108 } 1109 1110 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1111 1112 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1113 val = hact_st << 16; 1114 val |= hact_end; 1115 VOP_REG_SET(vop, modeset, hact_st_end, val); 1116 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1117 1118 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1119 val = vact_st << 16; 1120 val |= vact_end; 1121 VOP_REG_SET(vop, modeset, vact_st_end, val); 1122 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1123 1124 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1125 1126 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1127 1128 VOP_REG_SET(vop, common, standby, 0); 1129 mutex_unlock(&vop->vop_lock); 1130 } 1131 1132 static bool vop_fs_irq_is_pending(struct vop *vop) 1133 { 1134 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1135 } 1136 1137 static void vop_wait_for_irq_handler(struct vop *vop) 1138 { 1139 bool pending; 1140 int ret; 1141 1142 /* 1143 * Spin until frame start interrupt status bit goes low, which means 1144 * that interrupt handler was invoked and cleared it. The timeout of 1145 * 10 msecs is really too long, but it is just a safety measure if 1146 * something goes really wrong. The wait will only happen in the very 1147 * unlikely case of a vblank happening exactly at the same time and 1148 * shouldn't exceed microseconds range. 1149 */ 1150 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1151 !pending, 0, 10 * 1000); 1152 if (ret) 1153 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1154 1155 synchronize_irq(vop->irq); 1156 } 1157 1158 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1159 struct drm_crtc_state *old_crtc_state) 1160 { 1161 struct drm_atomic_state *old_state = old_crtc_state->state; 1162 struct drm_plane_state *old_plane_state, *new_plane_state; 1163 struct vop *vop = to_vop(crtc); 1164 struct drm_plane *plane; 1165 int i; 1166 1167 if (WARN_ON(!vop->is_enabled)) 1168 return; 1169 1170 spin_lock(&vop->reg_lock); 1171 1172 vop_cfg_done(vop); 1173 1174 spin_unlock(&vop->reg_lock); 1175 1176 /* 1177 * There is a (rather unlikely) possiblity that a vblank interrupt 1178 * fired before we set the cfg_done bit. To avoid spuriously 1179 * signalling flip completion we need to wait for it to finish. 1180 */ 1181 vop_wait_for_irq_handler(vop); 1182 1183 spin_lock_irq(&crtc->dev->event_lock); 1184 if (crtc->state->event) { 1185 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1186 WARN_ON(vop->event); 1187 1188 vop->event = crtc->state->event; 1189 crtc->state->event = NULL; 1190 } 1191 spin_unlock_irq(&crtc->dev->event_lock); 1192 1193 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1194 new_plane_state, i) { 1195 if (!old_plane_state->fb) 1196 continue; 1197 1198 if (old_plane_state->fb == new_plane_state->fb) 1199 continue; 1200 1201 drm_framebuffer_get(old_plane_state->fb); 1202 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1203 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1204 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1205 } 1206 } 1207 1208 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1209 .mode_fixup = vop_crtc_mode_fixup, 1210 .atomic_flush = vop_crtc_atomic_flush, 1211 .atomic_enable = vop_crtc_atomic_enable, 1212 .atomic_disable = vop_crtc_atomic_disable, 1213 }; 1214 1215 static void vop_crtc_destroy(struct drm_crtc *crtc) 1216 { 1217 drm_crtc_cleanup(crtc); 1218 } 1219 1220 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1221 { 1222 struct rockchip_crtc_state *rockchip_state; 1223 1224 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1225 if (!rockchip_state) 1226 return NULL; 1227 1228 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1229 return &rockchip_state->base; 1230 } 1231 1232 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1233 struct drm_crtc_state *state) 1234 { 1235 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1236 1237 __drm_atomic_helper_crtc_destroy_state(&s->base); 1238 kfree(s); 1239 } 1240 1241 static void vop_crtc_reset(struct drm_crtc *crtc) 1242 { 1243 struct rockchip_crtc_state *crtc_state = 1244 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1245 1246 if (crtc->state) 1247 vop_crtc_destroy_state(crtc, crtc->state); 1248 1249 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1250 } 1251 1252 #ifdef CONFIG_DRM_ANALOGIX_DP 1253 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1254 { 1255 struct drm_connector *connector; 1256 struct drm_connector_list_iter conn_iter; 1257 1258 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1259 drm_for_each_connector_iter(connector, &conn_iter) { 1260 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1261 drm_connector_list_iter_end(&conn_iter); 1262 return connector; 1263 } 1264 } 1265 drm_connector_list_iter_end(&conn_iter); 1266 1267 return NULL; 1268 } 1269 1270 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1271 const char *source_name) 1272 { 1273 struct vop *vop = to_vop(crtc); 1274 struct drm_connector *connector; 1275 int ret; 1276 1277 connector = vop_get_edp_connector(vop); 1278 if (!connector) 1279 return -EINVAL; 1280 1281 if (source_name && strcmp(source_name, "auto") == 0) 1282 ret = analogix_dp_start_crc(connector); 1283 else if (!source_name) 1284 ret = analogix_dp_stop_crc(connector); 1285 else 1286 ret = -EINVAL; 1287 1288 return ret; 1289 } 1290 1291 static int 1292 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1293 size_t *values_cnt) 1294 { 1295 if (source_name && strcmp(source_name, "auto") != 0) 1296 return -EINVAL; 1297 1298 *values_cnt = 3; 1299 return 0; 1300 } 1301 1302 #else 1303 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1304 const char *source_name) 1305 { 1306 return -ENODEV; 1307 } 1308 1309 static int 1310 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1311 size_t *values_cnt) 1312 { 1313 return -ENODEV; 1314 } 1315 #endif 1316 1317 static const struct drm_crtc_funcs vop_crtc_funcs = { 1318 .set_config = drm_atomic_helper_set_config, 1319 .page_flip = drm_atomic_helper_page_flip, 1320 .destroy = vop_crtc_destroy, 1321 .reset = vop_crtc_reset, 1322 .atomic_duplicate_state = vop_crtc_duplicate_state, 1323 .atomic_destroy_state = vop_crtc_destroy_state, 1324 .enable_vblank = vop_crtc_enable_vblank, 1325 .disable_vblank = vop_crtc_disable_vblank, 1326 .set_crc_source = vop_crtc_set_crc_source, 1327 .verify_crc_source = vop_crtc_verify_crc_source, 1328 }; 1329 1330 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1331 { 1332 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1333 struct drm_framebuffer *fb = val; 1334 1335 drm_crtc_vblank_put(&vop->crtc); 1336 drm_framebuffer_put(fb); 1337 } 1338 1339 static void vop_handle_vblank(struct vop *vop) 1340 { 1341 struct drm_device *drm = vop->drm_dev; 1342 struct drm_crtc *crtc = &vop->crtc; 1343 1344 spin_lock(&drm->event_lock); 1345 if (vop->event) { 1346 drm_crtc_send_vblank_event(crtc, vop->event); 1347 drm_crtc_vblank_put(crtc); 1348 vop->event = NULL; 1349 } 1350 spin_unlock(&drm->event_lock); 1351 1352 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1353 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1354 } 1355 1356 static irqreturn_t vop_isr(int irq, void *data) 1357 { 1358 struct vop *vop = data; 1359 struct drm_crtc *crtc = &vop->crtc; 1360 uint32_t active_irqs; 1361 int ret = IRQ_NONE; 1362 1363 /* 1364 * The irq is shared with the iommu. If the runtime-pm state of the 1365 * vop-device is disabled the irq has to be targeted at the iommu. 1366 */ 1367 if (!pm_runtime_get_if_in_use(vop->dev)) 1368 return IRQ_NONE; 1369 1370 if (vop_core_clks_enable(vop)) { 1371 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1372 goto out; 1373 } 1374 1375 /* 1376 * interrupt register has interrupt status, enable and clear bits, we 1377 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1378 */ 1379 spin_lock(&vop->irq_lock); 1380 1381 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1382 /* Clear all active interrupt sources */ 1383 if (active_irqs) 1384 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1385 1386 spin_unlock(&vop->irq_lock); 1387 1388 /* This is expected for vop iommu irqs, since the irq is shared */ 1389 if (!active_irqs) 1390 goto out_disable; 1391 1392 if (active_irqs & DSP_HOLD_VALID_INTR) { 1393 complete(&vop->dsp_hold_completion); 1394 active_irqs &= ~DSP_HOLD_VALID_INTR; 1395 ret = IRQ_HANDLED; 1396 } 1397 1398 if (active_irqs & LINE_FLAG_INTR) { 1399 complete(&vop->line_flag_completion); 1400 active_irqs &= ~LINE_FLAG_INTR; 1401 ret = IRQ_HANDLED; 1402 } 1403 1404 if (active_irqs & FS_INTR) { 1405 drm_crtc_handle_vblank(crtc); 1406 vop_handle_vblank(vop); 1407 active_irqs &= ~FS_INTR; 1408 ret = IRQ_HANDLED; 1409 } 1410 1411 /* Unhandled irqs are spurious. */ 1412 if (active_irqs) 1413 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1414 active_irqs); 1415 1416 out_disable: 1417 vop_core_clks_disable(vop); 1418 out: 1419 pm_runtime_put(vop->dev); 1420 return ret; 1421 } 1422 1423 static void vop_plane_add_properties(struct drm_plane *plane, 1424 const struct vop_win_data *win_data) 1425 { 1426 unsigned int flags = 0; 1427 1428 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1429 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1430 if (flags) 1431 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1432 DRM_MODE_ROTATE_0 | flags); 1433 } 1434 1435 static int vop_create_crtc(struct vop *vop) 1436 { 1437 const struct vop_data *vop_data = vop->data; 1438 struct device *dev = vop->dev; 1439 struct drm_device *drm_dev = vop->drm_dev; 1440 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1441 struct drm_crtc *crtc = &vop->crtc; 1442 struct device_node *port; 1443 int ret; 1444 int i; 1445 1446 /* 1447 * Create drm_plane for primary and cursor planes first, since we need 1448 * to pass them to drm_crtc_init_with_planes, which sets the 1449 * "possible_crtcs" to the newly initialized crtc. 1450 */ 1451 for (i = 0; i < vop_data->win_size; i++) { 1452 struct vop_win *vop_win = &vop->win[i]; 1453 const struct vop_win_data *win_data = vop_win->data; 1454 1455 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1456 win_data->type != DRM_PLANE_TYPE_CURSOR) 1457 continue; 1458 1459 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1460 0, &vop_plane_funcs, 1461 win_data->phy->data_formats, 1462 win_data->phy->nformats, 1463 NULL, win_data->type, NULL); 1464 if (ret) { 1465 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1466 ret); 1467 goto err_cleanup_planes; 1468 } 1469 1470 plane = &vop_win->base; 1471 drm_plane_helper_add(plane, &plane_helper_funcs); 1472 vop_plane_add_properties(plane, win_data); 1473 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1474 primary = plane; 1475 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1476 cursor = plane; 1477 } 1478 1479 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1480 &vop_crtc_funcs, NULL); 1481 if (ret) 1482 goto err_cleanup_planes; 1483 1484 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1485 1486 /* 1487 * Create drm_planes for overlay windows with possible_crtcs restricted 1488 * to the newly created crtc. 1489 */ 1490 for (i = 0; i < vop_data->win_size; i++) { 1491 struct vop_win *vop_win = &vop->win[i]; 1492 const struct vop_win_data *win_data = vop_win->data; 1493 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1494 1495 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1496 continue; 1497 1498 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1499 possible_crtcs, 1500 &vop_plane_funcs, 1501 win_data->phy->data_formats, 1502 win_data->phy->nformats, 1503 NULL, win_data->type, NULL); 1504 if (ret) { 1505 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1506 ret); 1507 goto err_cleanup_crtc; 1508 } 1509 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1510 vop_plane_add_properties(&vop_win->base, win_data); 1511 } 1512 1513 port = of_get_child_by_name(dev->of_node, "port"); 1514 if (!port) { 1515 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1516 dev->of_node); 1517 ret = -ENOENT; 1518 goto err_cleanup_crtc; 1519 } 1520 1521 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1522 vop_fb_unref_worker); 1523 1524 init_completion(&vop->dsp_hold_completion); 1525 init_completion(&vop->line_flag_completion); 1526 crtc->port = port; 1527 1528 return 0; 1529 1530 err_cleanup_crtc: 1531 drm_crtc_cleanup(crtc); 1532 err_cleanup_planes: 1533 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1534 head) 1535 drm_plane_cleanup(plane); 1536 return ret; 1537 } 1538 1539 static void vop_destroy_crtc(struct vop *vop) 1540 { 1541 struct drm_crtc *crtc = &vop->crtc; 1542 struct drm_device *drm_dev = vop->drm_dev; 1543 struct drm_plane *plane, *tmp; 1544 1545 of_node_put(crtc->port); 1546 1547 /* 1548 * We need to cleanup the planes now. Why? 1549 * 1550 * The planes are "&vop->win[i].base". That means the memory is 1551 * all part of the big "struct vop" chunk of memory. That memory 1552 * was devm allocated and associated with this component. We need to 1553 * free it ourselves before vop_unbind() finishes. 1554 */ 1555 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1556 head) 1557 vop_plane_destroy(plane); 1558 1559 /* 1560 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1561 * references the CRTC. 1562 */ 1563 drm_crtc_cleanup(crtc); 1564 drm_flip_work_cleanup(&vop->fb_unref_work); 1565 } 1566 1567 static int vop_initial(struct vop *vop) 1568 { 1569 const struct vop_data *vop_data = vop->data; 1570 struct reset_control *ahb_rst; 1571 int i, ret; 1572 1573 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1574 if (IS_ERR(vop->hclk)) { 1575 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1576 return PTR_ERR(vop->hclk); 1577 } 1578 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1579 if (IS_ERR(vop->aclk)) { 1580 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1581 return PTR_ERR(vop->aclk); 1582 } 1583 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1584 if (IS_ERR(vop->dclk)) { 1585 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1586 return PTR_ERR(vop->dclk); 1587 } 1588 1589 ret = pm_runtime_get_sync(vop->dev); 1590 if (ret < 0) { 1591 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1592 return ret; 1593 } 1594 1595 ret = clk_prepare(vop->dclk); 1596 if (ret < 0) { 1597 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1598 goto err_put_pm_runtime; 1599 } 1600 1601 /* Enable both the hclk and aclk to setup the vop */ 1602 ret = clk_prepare_enable(vop->hclk); 1603 if (ret < 0) { 1604 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1605 goto err_unprepare_dclk; 1606 } 1607 1608 ret = clk_prepare_enable(vop->aclk); 1609 if (ret < 0) { 1610 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1611 goto err_disable_hclk; 1612 } 1613 1614 /* 1615 * do hclk_reset, reset all vop registers. 1616 */ 1617 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1618 if (IS_ERR(ahb_rst)) { 1619 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1620 ret = PTR_ERR(ahb_rst); 1621 goto err_disable_aclk; 1622 } 1623 reset_control_assert(ahb_rst); 1624 usleep_range(10, 20); 1625 reset_control_deassert(ahb_rst); 1626 1627 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1628 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1629 1630 for (i = 0; i < vop->len; i += sizeof(u32)) 1631 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1632 1633 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1634 VOP_REG_SET(vop, common, dsp_blank, 0); 1635 1636 for (i = 0; i < vop_data->win_size; i++) { 1637 const struct vop_win_data *win = &vop_data->win[i]; 1638 int channel = i * 2 + 1; 1639 1640 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1641 vop_win_disable(vop, win); 1642 VOP_WIN_SET(vop, win, gate, 1); 1643 } 1644 1645 vop_cfg_done(vop); 1646 1647 /* 1648 * do dclk_reset, let all config take affect. 1649 */ 1650 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1651 if (IS_ERR(vop->dclk_rst)) { 1652 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1653 ret = PTR_ERR(vop->dclk_rst); 1654 goto err_disable_aclk; 1655 } 1656 reset_control_assert(vop->dclk_rst); 1657 usleep_range(10, 20); 1658 reset_control_deassert(vop->dclk_rst); 1659 1660 clk_disable(vop->hclk); 1661 clk_disable(vop->aclk); 1662 1663 vop->is_enabled = false; 1664 1665 pm_runtime_put_sync(vop->dev); 1666 1667 return 0; 1668 1669 err_disable_aclk: 1670 clk_disable_unprepare(vop->aclk); 1671 err_disable_hclk: 1672 clk_disable_unprepare(vop->hclk); 1673 err_unprepare_dclk: 1674 clk_unprepare(vop->dclk); 1675 err_put_pm_runtime: 1676 pm_runtime_put_sync(vop->dev); 1677 return ret; 1678 } 1679 1680 /* 1681 * Initialize the vop->win array elements. 1682 */ 1683 static void vop_win_init(struct vop *vop) 1684 { 1685 const struct vop_data *vop_data = vop->data; 1686 unsigned int i; 1687 1688 for (i = 0; i < vop_data->win_size; i++) { 1689 struct vop_win *vop_win = &vop->win[i]; 1690 const struct vop_win_data *win_data = &vop_data->win[i]; 1691 1692 vop_win->data = win_data; 1693 vop_win->vop = vop; 1694 1695 if (vop_data->win_yuv2yuv) 1696 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 1697 } 1698 } 1699 1700 /** 1701 * rockchip_drm_wait_vact_end 1702 * @crtc: CRTC to enable line flag 1703 * @mstimeout: millisecond for timeout 1704 * 1705 * Wait for vact_end line flag irq or timeout. 1706 * 1707 * Returns: 1708 * Zero on success, negative errno on failure. 1709 */ 1710 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1711 { 1712 struct vop *vop = to_vop(crtc); 1713 unsigned long jiffies_left; 1714 int ret = 0; 1715 1716 if (!crtc || !vop->is_enabled) 1717 return -ENODEV; 1718 1719 mutex_lock(&vop->vop_lock); 1720 if (mstimeout <= 0) { 1721 ret = -EINVAL; 1722 goto out; 1723 } 1724 1725 if (vop_line_flag_irq_is_enabled(vop)) { 1726 ret = -EBUSY; 1727 goto out; 1728 } 1729 1730 reinit_completion(&vop->line_flag_completion); 1731 vop_line_flag_irq_enable(vop); 1732 1733 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1734 msecs_to_jiffies(mstimeout)); 1735 vop_line_flag_irq_disable(vop); 1736 1737 if (jiffies_left == 0) { 1738 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1739 ret = -ETIMEDOUT; 1740 goto out; 1741 } 1742 1743 out: 1744 mutex_unlock(&vop->vop_lock); 1745 return ret; 1746 } 1747 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1748 1749 static int vop_bind(struct device *dev, struct device *master, void *data) 1750 { 1751 struct platform_device *pdev = to_platform_device(dev); 1752 const struct vop_data *vop_data; 1753 struct drm_device *drm_dev = data; 1754 struct vop *vop; 1755 struct resource *res; 1756 int ret, irq; 1757 1758 vop_data = of_device_get_match_data(dev); 1759 if (!vop_data) 1760 return -ENODEV; 1761 1762 /* Allocate vop struct and its vop_win array */ 1763 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 1764 GFP_KERNEL); 1765 if (!vop) 1766 return -ENOMEM; 1767 1768 vop->dev = dev; 1769 vop->data = vop_data; 1770 vop->drm_dev = drm_dev; 1771 dev_set_drvdata(dev, vop); 1772 1773 vop_win_init(vop); 1774 1775 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1776 vop->len = resource_size(res); 1777 vop->regs = devm_ioremap_resource(dev, res); 1778 if (IS_ERR(vop->regs)) 1779 return PTR_ERR(vop->regs); 1780 1781 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1782 if (!vop->regsbak) 1783 return -ENOMEM; 1784 1785 irq = platform_get_irq(pdev, 0); 1786 if (irq < 0) { 1787 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1788 return irq; 1789 } 1790 vop->irq = (unsigned int)irq; 1791 1792 spin_lock_init(&vop->reg_lock); 1793 spin_lock_init(&vop->irq_lock); 1794 mutex_init(&vop->vop_lock); 1795 1796 ret = vop_create_crtc(vop); 1797 if (ret) 1798 return ret; 1799 1800 pm_runtime_enable(&pdev->dev); 1801 1802 ret = vop_initial(vop); 1803 if (ret < 0) { 1804 DRM_DEV_ERROR(&pdev->dev, 1805 "cannot initial vop dev - err %d\n", ret); 1806 goto err_disable_pm_runtime; 1807 } 1808 1809 ret = devm_request_irq(dev, vop->irq, vop_isr, 1810 IRQF_SHARED, dev_name(dev), vop); 1811 if (ret) 1812 goto err_disable_pm_runtime; 1813 1814 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 1815 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 1816 if (IS_ERR(vop->rgb)) { 1817 ret = PTR_ERR(vop->rgb); 1818 goto err_disable_pm_runtime; 1819 } 1820 } 1821 1822 return 0; 1823 1824 err_disable_pm_runtime: 1825 pm_runtime_disable(&pdev->dev); 1826 vop_destroy_crtc(vop); 1827 return ret; 1828 } 1829 1830 static void vop_unbind(struct device *dev, struct device *master, void *data) 1831 { 1832 struct vop *vop = dev_get_drvdata(dev); 1833 1834 if (vop->rgb) 1835 rockchip_rgb_fini(vop->rgb); 1836 1837 pm_runtime_disable(dev); 1838 vop_destroy_crtc(vop); 1839 1840 clk_unprepare(vop->aclk); 1841 clk_unprepare(vop->hclk); 1842 clk_unprepare(vop->dclk); 1843 } 1844 1845 const struct component_ops vop_component_ops = { 1846 .bind = vop_bind, 1847 .unbind = vop_unbind, 1848 }; 1849 EXPORT_SYMBOL_GPL(vop_component_ops); 1850