1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/log2.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/overflow.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 21 #include <drm/drm.h> 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_uapi.h> 24 #include <drm/drm_blend.h> 25 #include <drm/drm_crtc.h> 26 #include <drm/drm_flip_work.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_framebuffer.h> 29 #include <drm/drm_gem_atomic_helper.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_self_refresh_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #ifdef CONFIG_DRM_ANALOGIX_DP 36 #include <drm/bridge/analogix_dp.h> 37 #endif 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_vop.h" 43 #include "rockchip_rgb.h" 44 45 #define VOP_WIN_SET(vop, win, name, v) \ 46 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET(vop, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 49 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 50 vop_reg_set(vop, &win->phy->scl->ext->name, \ 51 win->base, ~0, v, #name) 52 53 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 54 do { \ 55 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 56 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 57 } while (0) 58 59 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 60 do { \ 61 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 62 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 63 } while (0) 64 65 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 66 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 67 68 #define VOP_REG_SET(vop, group, name, v) \ 69 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 70 71 #define VOP_HAS_REG(vop, group, name) \ 72 (!!(vop->data->group->name.mask)) 73 74 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 75 do { \ 76 int i, reg = 0, mask = 0; \ 77 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 78 if (vop->data->intr->intrs[i] & type) { \ 79 reg |= (v) << i; \ 80 mask |= 1 << i; \ 81 } \ 82 } \ 83 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 84 } while (0) 85 #define VOP_INTR_GET_TYPE(vop, name, type) \ 86 vop_get_intr_type(vop, &vop->data->intr->name, type) 87 88 #define VOP_WIN_GET(vop, win, name) \ 89 vop_read_reg(vop, win->base, &win->phy->name) 90 91 #define VOP_WIN_HAS_REG(win, name) \ 92 (!!(win->phy->name.mask)) 93 94 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 95 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 96 97 #define VOP_WIN_TO_INDEX(vop_win) \ 98 ((vop_win) - (vop_win)->vop->win) 99 100 #define VOP_AFBC_SET(vop, name, v) \ 101 do { \ 102 if ((vop)->data->afbc) \ 103 vop_reg_set((vop), &(vop)->data->afbc->name, \ 104 0, ~0, v, #name); \ 105 } while (0) 106 107 #define to_vop(x) container_of(x, struct vop, crtc) 108 #define to_vop_win(x) container_of(x, struct vop_win, base) 109 110 #define AFBC_FMT_RGB565 0x0 111 #define AFBC_FMT_U8U8U8U8 0x5 112 #define AFBC_FMT_U8U8U8 0x4 113 114 #define AFBC_TILE_16x16 BIT(4) 115 116 /* 117 * The coefficients of the following matrix are all fixed points. 118 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 119 * They are all represented in two's complement. 120 */ 121 static const uint32_t bt601_yuv2rgb[] = { 122 0x4A8, 0x0, 0x662, 123 0x4A8, 0x1E6F, 0x1CBF, 124 0x4A8, 0x812, 0x0, 125 0x321168, 0x0877CF, 0x2EB127 126 }; 127 128 enum vop_pending { 129 VOP_PENDING_FB_UNREF, 130 }; 131 132 struct vop_win { 133 struct drm_plane base; 134 const struct vop_win_data *data; 135 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 136 struct vop *vop; 137 }; 138 139 struct rockchip_rgb; 140 struct vop { 141 struct drm_crtc crtc; 142 struct device *dev; 143 struct drm_device *drm_dev; 144 bool is_enabled; 145 146 struct completion dsp_hold_completion; 147 unsigned int win_enabled; 148 149 /* protected by dev->event_lock */ 150 struct drm_pending_vblank_event *event; 151 152 struct drm_flip_work fb_unref_work; 153 unsigned long pending; 154 155 struct completion line_flag_completion; 156 157 const struct vop_data *data; 158 159 uint32_t *regsbak; 160 void __iomem *regs; 161 void __iomem *lut_regs; 162 163 /* physical map length of vop register */ 164 uint32_t len; 165 166 /* one time only one process allowed to config the register */ 167 spinlock_t reg_lock; 168 /* lock vop irq reg */ 169 spinlock_t irq_lock; 170 /* protects crtc enable/disable */ 171 struct mutex vop_lock; 172 173 unsigned int irq; 174 175 /* vop AHP clk */ 176 struct clk *hclk; 177 /* vop dclk */ 178 struct clk *dclk; 179 /* vop share memory frequency */ 180 struct clk *aclk; 181 182 /* vop dclk reset */ 183 struct reset_control *dclk_rst; 184 185 /* optional internal rgb encoder */ 186 struct rockchip_rgb *rgb; 187 188 struct vop_win win[]; 189 }; 190 191 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 192 { 193 return readl(vop->regs + offset); 194 } 195 196 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 197 const struct vop_reg *reg) 198 { 199 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 200 } 201 202 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 203 uint32_t _offset, uint32_t _mask, uint32_t v, 204 const char *reg_name) 205 { 206 int offset, mask, shift; 207 208 if (!reg || !reg->mask) { 209 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 210 return; 211 } 212 213 offset = reg->offset + _offset; 214 mask = reg->mask & _mask; 215 shift = reg->shift; 216 217 if (reg->write_mask) { 218 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 219 } else { 220 uint32_t cached_val = vop->regsbak[offset >> 2]; 221 222 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 223 vop->regsbak[offset >> 2] = v; 224 } 225 226 if (reg->relaxed) 227 writel_relaxed(v, vop->regs + offset); 228 else 229 writel(v, vop->regs + offset); 230 } 231 232 static inline uint32_t vop_get_intr_type(struct vop *vop, 233 const struct vop_reg *reg, int type) 234 { 235 uint32_t i, ret = 0; 236 uint32_t regs = vop_read_reg(vop, 0, reg); 237 238 for (i = 0; i < vop->data->intr->nintrs; i++) { 239 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 240 ret |= vop->data->intr->intrs[i]; 241 } 242 243 return ret; 244 } 245 246 static inline void vop_cfg_done(struct vop *vop) 247 { 248 VOP_REG_SET(vop, common, cfg_done, 1); 249 } 250 251 static bool has_rb_swapped(uint32_t format) 252 { 253 switch (format) { 254 case DRM_FORMAT_XBGR8888: 255 case DRM_FORMAT_ABGR8888: 256 case DRM_FORMAT_BGR888: 257 case DRM_FORMAT_BGR565: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static bool has_uv_swapped(uint32_t format) 265 { 266 switch (format) { 267 case DRM_FORMAT_NV21: 268 case DRM_FORMAT_NV61: 269 case DRM_FORMAT_NV42: 270 return true; 271 default: 272 return false; 273 } 274 } 275 276 static enum vop_data_format vop_convert_format(uint32_t format) 277 { 278 switch (format) { 279 case DRM_FORMAT_XRGB8888: 280 case DRM_FORMAT_ARGB8888: 281 case DRM_FORMAT_XBGR8888: 282 case DRM_FORMAT_ABGR8888: 283 return VOP_FMT_ARGB8888; 284 case DRM_FORMAT_RGB888: 285 case DRM_FORMAT_BGR888: 286 return VOP_FMT_RGB888; 287 case DRM_FORMAT_RGB565: 288 case DRM_FORMAT_BGR565: 289 return VOP_FMT_RGB565; 290 case DRM_FORMAT_NV12: 291 case DRM_FORMAT_NV21: 292 return VOP_FMT_YUV420SP; 293 case DRM_FORMAT_NV16: 294 case DRM_FORMAT_NV61: 295 return VOP_FMT_YUV422SP; 296 case DRM_FORMAT_NV24: 297 case DRM_FORMAT_NV42: 298 return VOP_FMT_YUV444SP; 299 default: 300 DRM_ERROR("unsupported format[%08x]\n", format); 301 return -EINVAL; 302 } 303 } 304 305 static int vop_convert_afbc_format(uint32_t format) 306 { 307 switch (format) { 308 case DRM_FORMAT_XRGB8888: 309 case DRM_FORMAT_ARGB8888: 310 case DRM_FORMAT_XBGR8888: 311 case DRM_FORMAT_ABGR8888: 312 return AFBC_FMT_U8U8U8U8; 313 case DRM_FORMAT_RGB888: 314 case DRM_FORMAT_BGR888: 315 return AFBC_FMT_U8U8U8; 316 case DRM_FORMAT_RGB565: 317 case DRM_FORMAT_BGR565: 318 return AFBC_FMT_RGB565; 319 /* either of the below should not be reachable */ 320 default: 321 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); 322 return -EINVAL; 323 } 324 325 return -EINVAL; 326 } 327 328 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 329 uint32_t dst, bool is_horizontal, 330 int vsu_mode, int *vskiplines) 331 { 332 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 333 334 if (vskiplines) 335 *vskiplines = 0; 336 337 if (is_horizontal) { 338 if (mode == SCALE_UP) 339 val = GET_SCL_FT_BIC(src, dst); 340 else if (mode == SCALE_DOWN) 341 val = GET_SCL_FT_BILI_DN(src, dst); 342 } else { 343 if (mode == SCALE_UP) { 344 if (vsu_mode == SCALE_UP_BIL) 345 val = GET_SCL_FT_BILI_UP(src, dst); 346 else 347 val = GET_SCL_FT_BIC(src, dst); 348 } else if (mode == SCALE_DOWN) { 349 if (vskiplines) { 350 *vskiplines = scl_get_vskiplines(src, dst); 351 val = scl_get_bili_dn_vskip(src, dst, 352 *vskiplines); 353 } else { 354 val = GET_SCL_FT_BILI_DN(src, dst); 355 } 356 } 357 } 358 359 return val; 360 } 361 362 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 363 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 364 uint32_t dst_h, const struct drm_format_info *info) 365 { 366 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 367 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 368 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 369 bool is_yuv = false; 370 uint16_t cbcr_src_w = src_w / info->hsub; 371 uint16_t cbcr_src_h = src_h / info->vsub; 372 uint16_t vsu_mode; 373 uint16_t lb_mode; 374 uint32_t val; 375 int vskiplines; 376 377 if (info->is_yuv) 378 is_yuv = true; 379 380 if (dst_w > 3840) { 381 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 382 return; 383 } 384 385 if (!win->phy->scl->ext) { 386 VOP_SCL_SET(vop, win, scale_yrgb_x, 387 scl_cal_scale2(src_w, dst_w)); 388 VOP_SCL_SET(vop, win, scale_yrgb_y, 389 scl_cal_scale2(src_h, dst_h)); 390 if (is_yuv) { 391 VOP_SCL_SET(vop, win, scale_cbcr_x, 392 scl_cal_scale2(cbcr_src_w, dst_w)); 393 VOP_SCL_SET(vop, win, scale_cbcr_y, 394 scl_cal_scale2(cbcr_src_h, dst_h)); 395 } 396 return; 397 } 398 399 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 400 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 401 402 if (is_yuv) { 403 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 404 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 405 if (cbcr_hor_scl_mode == SCALE_DOWN) 406 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 407 else 408 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 409 } else { 410 if (yrgb_hor_scl_mode == SCALE_DOWN) 411 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 412 else 413 lb_mode = scl_vop_cal_lb_mode(src_w, false); 414 } 415 416 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 417 if (lb_mode == LB_RGB_3840X2) { 418 if (yrgb_ver_scl_mode != SCALE_NONE) { 419 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 420 return; 421 } 422 if (cbcr_ver_scl_mode != SCALE_NONE) { 423 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 424 return; 425 } 426 vsu_mode = SCALE_UP_BIL; 427 } else if (lb_mode == LB_RGB_2560X4) { 428 vsu_mode = SCALE_UP_BIL; 429 } else { 430 vsu_mode = SCALE_UP_BIC; 431 } 432 433 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 434 true, 0, NULL); 435 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 436 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 437 false, vsu_mode, &vskiplines); 438 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 439 440 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 441 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 442 443 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 444 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 445 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 446 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 447 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 448 if (is_yuv) { 449 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 450 dst_w, true, 0, NULL); 451 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 452 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 453 dst_h, false, vsu_mode, &vskiplines); 454 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 455 456 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 457 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 458 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 459 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 460 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 461 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 462 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 463 } 464 } 465 466 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 467 { 468 unsigned long flags; 469 470 if (WARN_ON(!vop->is_enabled)) 471 return; 472 473 spin_lock_irqsave(&vop->irq_lock, flags); 474 475 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 476 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 477 478 spin_unlock_irqrestore(&vop->irq_lock, flags); 479 } 480 481 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 482 { 483 unsigned long flags; 484 485 if (WARN_ON(!vop->is_enabled)) 486 return; 487 488 spin_lock_irqsave(&vop->irq_lock, flags); 489 490 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 491 492 spin_unlock_irqrestore(&vop->irq_lock, flags); 493 } 494 495 /* 496 * (1) each frame starts at the start of the Vsync pulse which is signaled by 497 * the "FRAME_SYNC" interrupt. 498 * (2) the active data region of each frame ends at dsp_vact_end 499 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 500 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 501 * 502 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 503 * Interrupts 504 * LINE_FLAG -------------------------------+ 505 * FRAME_SYNC ----+ | 506 * | | 507 * v v 508 * | Vsync | Vbp | Vactive | Vfp | 509 * ^ ^ ^ ^ 510 * | | | | 511 * | | | | 512 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 513 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 514 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 515 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 516 */ 517 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 518 { 519 uint32_t line_flag_irq; 520 unsigned long flags; 521 522 spin_lock_irqsave(&vop->irq_lock, flags); 523 524 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 525 526 spin_unlock_irqrestore(&vop->irq_lock, flags); 527 528 return !!line_flag_irq; 529 } 530 531 static void vop_line_flag_irq_enable(struct vop *vop) 532 { 533 unsigned long flags; 534 535 if (WARN_ON(!vop->is_enabled)) 536 return; 537 538 spin_lock_irqsave(&vop->irq_lock, flags); 539 540 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 541 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 542 543 spin_unlock_irqrestore(&vop->irq_lock, flags); 544 } 545 546 static void vop_line_flag_irq_disable(struct vop *vop) 547 { 548 unsigned long flags; 549 550 if (WARN_ON(!vop->is_enabled)) 551 return; 552 553 spin_lock_irqsave(&vop->irq_lock, flags); 554 555 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 556 557 spin_unlock_irqrestore(&vop->irq_lock, flags); 558 } 559 560 static int vop_core_clks_enable(struct vop *vop) 561 { 562 int ret; 563 564 ret = clk_enable(vop->hclk); 565 if (ret < 0) 566 return ret; 567 568 ret = clk_enable(vop->aclk); 569 if (ret < 0) 570 goto err_disable_hclk; 571 572 return 0; 573 574 err_disable_hclk: 575 clk_disable(vop->hclk); 576 return ret; 577 } 578 579 static void vop_core_clks_disable(struct vop *vop) 580 { 581 clk_disable(vop->aclk); 582 clk_disable(vop->hclk); 583 } 584 585 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 586 { 587 const struct vop_win_data *win = vop_win->data; 588 589 if (win->phy->scl && win->phy->scl->ext) { 590 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 591 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 592 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 593 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 594 } 595 596 VOP_WIN_SET(vop, win, enable, 0); 597 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 598 } 599 600 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 601 { 602 struct vop *vop = to_vop(crtc); 603 int ret, i; 604 605 ret = pm_runtime_get_sync(vop->dev); 606 if (ret < 0) { 607 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 608 return ret; 609 } 610 611 ret = vop_core_clks_enable(vop); 612 if (WARN_ON(ret < 0)) 613 goto err_put_pm_runtime; 614 615 ret = clk_enable(vop->dclk); 616 if (WARN_ON(ret < 0)) 617 goto err_disable_core; 618 619 /* 620 * Slave iommu shares power, irq and clock with vop. It was associated 621 * automatically with this master device via common driver code. 622 * Now that we have enabled the clock we attach it to the shared drm 623 * mapping. 624 */ 625 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 626 if (ret) { 627 DRM_DEV_ERROR(vop->dev, 628 "failed to attach dma mapping, %d\n", ret); 629 goto err_disable_dclk; 630 } 631 632 spin_lock(&vop->reg_lock); 633 for (i = 0; i < vop->len; i += 4) 634 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 635 636 /* 637 * We need to make sure that all windows are disabled before we 638 * enable the crtc. Otherwise we might try to scan from a destroyed 639 * buffer later. 640 * 641 * In the case of enable-after-PSR, we don't need to worry about this 642 * case since the buffer is guaranteed to be valid and disabling the 643 * window will result in screen glitches on PSR exit. 644 */ 645 if (!old_state || !old_state->self_refresh_active) { 646 for (i = 0; i < vop->data->win_size; i++) { 647 struct vop_win *vop_win = &vop->win[i]; 648 649 vop_win_disable(vop, vop_win); 650 } 651 } 652 653 if (vop->data->afbc) { 654 struct rockchip_crtc_state *s; 655 /* 656 * Disable AFBC and forget there was a vop window with AFBC 657 */ 658 VOP_AFBC_SET(vop, enable, 0); 659 s = to_rockchip_crtc_state(crtc->state); 660 s->enable_afbc = false; 661 } 662 663 vop_cfg_done(vop); 664 665 spin_unlock(&vop->reg_lock); 666 667 /* 668 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 669 */ 670 vop->is_enabled = true; 671 672 spin_lock(&vop->reg_lock); 673 674 VOP_REG_SET(vop, common, standby, 1); 675 676 spin_unlock(&vop->reg_lock); 677 678 drm_crtc_vblank_on(crtc); 679 680 return 0; 681 682 err_disable_dclk: 683 clk_disable(vop->dclk); 684 err_disable_core: 685 vop_core_clks_disable(vop); 686 err_put_pm_runtime: 687 pm_runtime_put_sync(vop->dev); 688 return ret; 689 } 690 691 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 692 { 693 struct vop *vop = to_vop(crtc); 694 int i; 695 696 spin_lock(&vop->reg_lock); 697 698 for (i = 0; i < vop->data->win_size; i++) { 699 struct vop_win *vop_win = &vop->win[i]; 700 const struct vop_win_data *win = vop_win->data; 701 702 VOP_WIN_SET(vop, win, enable, 703 enabled && (vop->win_enabled & BIT(i))); 704 } 705 vop_cfg_done(vop); 706 707 spin_unlock(&vop->reg_lock); 708 } 709 710 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 711 struct drm_atomic_state *state) 712 { 713 struct vop *vop = to_vop(crtc); 714 715 WARN_ON(vop->event); 716 717 if (crtc->state->self_refresh_active) 718 rockchip_drm_set_win_enabled(crtc, false); 719 720 mutex_lock(&vop->vop_lock); 721 722 drm_crtc_vblank_off(crtc); 723 724 if (crtc->state->self_refresh_active) 725 goto out; 726 727 /* 728 * Vop standby will take effect at end of current frame, 729 * if dsp hold valid irq happen, it means standby complete. 730 * 731 * we must wait standby complete when we want to disable aclk, 732 * if not, memory bus maybe dead. 733 */ 734 reinit_completion(&vop->dsp_hold_completion); 735 vop_dsp_hold_valid_irq_enable(vop); 736 737 spin_lock(&vop->reg_lock); 738 739 VOP_REG_SET(vop, common, standby, 1); 740 741 spin_unlock(&vop->reg_lock); 742 743 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 744 msecs_to_jiffies(200))) 745 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 746 747 vop_dsp_hold_valid_irq_disable(vop); 748 749 vop->is_enabled = false; 750 751 /* 752 * vop standby complete, so iommu detach is safe. 753 */ 754 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 755 756 clk_disable(vop->dclk); 757 vop_core_clks_disable(vop); 758 pm_runtime_put(vop->dev); 759 760 out: 761 mutex_unlock(&vop->vop_lock); 762 763 if (crtc->state->event && !crtc->state->active) { 764 spin_lock_irq(&crtc->dev->event_lock); 765 drm_crtc_send_vblank_event(crtc, crtc->state->event); 766 spin_unlock_irq(&crtc->dev->event_lock); 767 768 crtc->state->event = NULL; 769 } 770 } 771 772 static void vop_plane_destroy(struct drm_plane *plane) 773 { 774 drm_plane_cleanup(plane); 775 } 776 777 static inline bool rockchip_afbc(u64 modifier) 778 { 779 return modifier == ROCKCHIP_AFBC_MOD; 780 } 781 782 static bool rockchip_mod_supported(struct drm_plane *plane, 783 u32 format, u64 modifier) 784 { 785 if (modifier == DRM_FORMAT_MOD_LINEAR) 786 return true; 787 788 if (!rockchip_afbc(modifier)) { 789 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 790 791 return false; 792 } 793 794 return vop_convert_afbc_format(format) >= 0; 795 } 796 797 static int vop_plane_atomic_check(struct drm_plane *plane, 798 struct drm_atomic_state *state) 799 { 800 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 801 plane); 802 struct drm_crtc *crtc = new_plane_state->crtc; 803 struct drm_crtc_state *crtc_state; 804 struct drm_framebuffer *fb = new_plane_state->fb; 805 struct vop_win *vop_win = to_vop_win(plane); 806 const struct vop_win_data *win = vop_win->data; 807 int ret; 808 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 809 DRM_PLANE_NO_SCALING; 810 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 811 DRM_PLANE_NO_SCALING; 812 813 if (!crtc || WARN_ON(!fb)) 814 return 0; 815 816 crtc_state = drm_atomic_get_existing_crtc_state(state, 817 crtc); 818 if (WARN_ON(!crtc_state)) 819 return -EINVAL; 820 821 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 822 min_scale, max_scale, 823 true, true); 824 if (ret) 825 return ret; 826 827 if (!new_plane_state->visible) 828 return 0; 829 830 ret = vop_convert_format(fb->format->format); 831 if (ret < 0) 832 return ret; 833 834 /* 835 * Src.x1 can be odd when do clip, but yuv plane start point 836 * need align with 2 pixel. 837 */ 838 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 839 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 840 return -EINVAL; 841 } 842 843 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 844 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 845 return -EINVAL; 846 } 847 848 if (rockchip_afbc(fb->modifier)) { 849 struct vop *vop = to_vop(crtc); 850 851 if (!vop->data->afbc) { 852 DRM_ERROR("vop does not support AFBC\n"); 853 return -EINVAL; 854 } 855 856 ret = vop_convert_afbc_format(fb->format->format); 857 if (ret < 0) 858 return ret; 859 860 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 861 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", 862 new_plane_state->src.x1, 863 new_plane_state->src.y1, fb->offsets[0]); 864 return -EINVAL; 865 } 866 867 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 868 DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 869 new_plane_state->rotation); 870 return -EINVAL; 871 } 872 } 873 874 return 0; 875 } 876 877 static void vop_plane_atomic_disable(struct drm_plane *plane, 878 struct drm_atomic_state *state) 879 { 880 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 881 plane); 882 struct vop_win *vop_win = to_vop_win(plane); 883 struct vop *vop = to_vop(old_state->crtc); 884 885 if (!old_state->crtc) 886 return; 887 888 spin_lock(&vop->reg_lock); 889 890 vop_win_disable(vop, vop_win); 891 892 spin_unlock(&vop->reg_lock); 893 } 894 895 static void vop_plane_atomic_update(struct drm_plane *plane, 896 struct drm_atomic_state *state) 897 { 898 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 899 plane); 900 struct drm_crtc *crtc = new_state->crtc; 901 struct vop_win *vop_win = to_vop_win(plane); 902 const struct vop_win_data *win = vop_win->data; 903 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 904 struct vop *vop = to_vop(new_state->crtc); 905 struct drm_framebuffer *fb = new_state->fb; 906 unsigned int actual_w, actual_h; 907 unsigned int dsp_stx, dsp_sty; 908 uint32_t act_info, dsp_info, dsp_st; 909 struct drm_rect *src = &new_state->src; 910 struct drm_rect *dest = &new_state->dst; 911 struct drm_gem_object *obj, *uv_obj; 912 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 913 unsigned long offset; 914 dma_addr_t dma_addr; 915 uint32_t val; 916 bool rb_swap, uv_swap; 917 int win_index = VOP_WIN_TO_INDEX(vop_win); 918 int format; 919 int is_yuv = fb->format->is_yuv; 920 int i; 921 922 /* 923 * can't update plane when vop is disabled. 924 */ 925 if (WARN_ON(!crtc)) 926 return; 927 928 if (WARN_ON(!vop->is_enabled)) 929 return; 930 931 if (!new_state->visible) { 932 vop_plane_atomic_disable(plane, state); 933 return; 934 } 935 936 obj = fb->obj[0]; 937 rk_obj = to_rockchip_obj(obj); 938 939 actual_w = drm_rect_width(src) >> 16; 940 actual_h = drm_rect_height(src) >> 16; 941 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 942 943 dsp_info = (drm_rect_height(dest) - 1) << 16; 944 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 945 946 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 947 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 948 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 949 950 offset = (src->x1 >> 16) * fb->format->cpp[0]; 951 offset += (src->y1 >> 16) * fb->pitches[0]; 952 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 953 954 /* 955 * For y-mirroring we need to move address 956 * to the beginning of the last line. 957 */ 958 if (new_state->rotation & DRM_MODE_REFLECT_Y) 959 dma_addr += (actual_h - 1) * fb->pitches[0]; 960 961 format = vop_convert_format(fb->format->format); 962 963 spin_lock(&vop->reg_lock); 964 965 if (rockchip_afbc(fb->modifier)) { 966 int afbc_format = vop_convert_afbc_format(fb->format->format); 967 968 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 969 VOP_AFBC_SET(vop, hreg_block_split, 0); 970 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 971 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 972 VOP_AFBC_SET(vop, pic_size, act_info); 973 } 974 975 VOP_WIN_SET(vop, win, format, format); 976 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 977 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 978 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 979 VOP_WIN_SET(vop, win, y_mir_en, 980 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 981 VOP_WIN_SET(vop, win, x_mir_en, 982 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 983 984 if (is_yuv) { 985 int hsub = fb->format->hsub; 986 int vsub = fb->format->vsub; 987 int bpp = fb->format->cpp[1]; 988 989 uv_obj = fb->obj[1]; 990 rk_uv_obj = to_rockchip_obj(uv_obj); 991 992 offset = (src->x1 >> 16) * bpp / hsub; 993 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 994 995 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 996 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 997 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 998 999 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 1000 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 1001 win_yuv2yuv, 1002 y2r_coefficients[i], 1003 bt601_yuv2rgb[i]); 1004 } 1005 1006 uv_swap = has_uv_swapped(fb->format->format); 1007 VOP_WIN_SET(vop, win, uv_swap, uv_swap); 1008 } 1009 1010 if (win->phy->scl) 1011 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 1012 drm_rect_width(dest), drm_rect_height(dest), 1013 fb->format); 1014 1015 VOP_WIN_SET(vop, win, act_info, act_info); 1016 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1017 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1018 1019 rb_swap = has_rb_swapped(fb->format->format); 1020 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1021 1022 /* 1023 * Blending win0 with the background color doesn't seem to work 1024 * correctly. We only get the background color, no matter the contents 1025 * of the win0 framebuffer. However, blending pre-multiplied color 1026 * with the default opaque black default background color is a no-op, 1027 * so we can just disable blending to get the correct result. 1028 */ 1029 if (fb->format->has_alpha && win_index > 0) { 1030 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1031 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1032 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1033 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1034 SRC_BLEND_M0(ALPHA_PER_PIX) | 1035 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1036 SRC_FACTOR_M0(ALPHA_ONE); 1037 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1038 1039 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1040 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1041 VOP_WIN_SET(vop, win, alpha_en, 1); 1042 } else { 1043 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1044 VOP_WIN_SET(vop, win, alpha_en, 0); 1045 } 1046 1047 VOP_WIN_SET(vop, win, enable, 1); 1048 vop->win_enabled |= BIT(win_index); 1049 spin_unlock(&vop->reg_lock); 1050 } 1051 1052 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1053 struct drm_atomic_state *state) 1054 { 1055 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1056 plane); 1057 struct vop_win *vop_win = to_vop_win(plane); 1058 const struct vop_win_data *win = vop_win->data; 1059 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1060 DRM_PLANE_NO_SCALING; 1061 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1062 DRM_PLANE_NO_SCALING; 1063 struct drm_crtc_state *crtc_state; 1064 1065 if (plane != new_plane_state->crtc->cursor) 1066 return -EINVAL; 1067 1068 if (!plane->state) 1069 return -EINVAL; 1070 1071 if (!plane->state->fb) 1072 return -EINVAL; 1073 1074 if (state) 1075 crtc_state = drm_atomic_get_existing_crtc_state(state, 1076 new_plane_state->crtc); 1077 else /* Special case for asynchronous cursor updates. */ 1078 crtc_state = plane->crtc->state; 1079 1080 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1081 min_scale, max_scale, 1082 true, true); 1083 } 1084 1085 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1086 struct drm_atomic_state *state) 1087 { 1088 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1089 plane); 1090 struct vop *vop = to_vop(plane->state->crtc); 1091 struct drm_framebuffer *old_fb = plane->state->fb; 1092 1093 plane->state->crtc_x = new_state->crtc_x; 1094 plane->state->crtc_y = new_state->crtc_y; 1095 plane->state->crtc_h = new_state->crtc_h; 1096 plane->state->crtc_w = new_state->crtc_w; 1097 plane->state->src_x = new_state->src_x; 1098 plane->state->src_y = new_state->src_y; 1099 plane->state->src_h = new_state->src_h; 1100 plane->state->src_w = new_state->src_w; 1101 swap(plane->state->fb, new_state->fb); 1102 1103 if (vop->is_enabled) { 1104 vop_plane_atomic_update(plane, state); 1105 spin_lock(&vop->reg_lock); 1106 vop_cfg_done(vop); 1107 spin_unlock(&vop->reg_lock); 1108 1109 /* 1110 * A scanout can still be occurring, so we can't drop the 1111 * reference to the old framebuffer. To solve this we get a 1112 * reference to old_fb and set a worker to release it later. 1113 * FIXME: if we perform 500 async_update calls before the 1114 * vblank, then we can have 500 different framebuffers waiting 1115 * to be released. 1116 */ 1117 if (old_fb && plane->state->fb != old_fb) { 1118 drm_framebuffer_get(old_fb); 1119 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1120 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1121 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1122 } 1123 } 1124 } 1125 1126 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1127 .atomic_check = vop_plane_atomic_check, 1128 .atomic_update = vop_plane_atomic_update, 1129 .atomic_disable = vop_plane_atomic_disable, 1130 .atomic_async_check = vop_plane_atomic_async_check, 1131 .atomic_async_update = vop_plane_atomic_async_update, 1132 }; 1133 1134 static const struct drm_plane_funcs vop_plane_funcs = { 1135 .update_plane = drm_atomic_helper_update_plane, 1136 .disable_plane = drm_atomic_helper_disable_plane, 1137 .destroy = vop_plane_destroy, 1138 .reset = drm_atomic_helper_plane_reset, 1139 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1140 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1141 .format_mod_supported = rockchip_mod_supported, 1142 }; 1143 1144 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1145 { 1146 struct vop *vop = to_vop(crtc); 1147 unsigned long flags; 1148 1149 if (WARN_ON(!vop->is_enabled)) 1150 return -EPERM; 1151 1152 spin_lock_irqsave(&vop->irq_lock, flags); 1153 1154 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1155 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1156 1157 spin_unlock_irqrestore(&vop->irq_lock, flags); 1158 1159 return 0; 1160 } 1161 1162 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1163 { 1164 struct vop *vop = to_vop(crtc); 1165 unsigned long flags; 1166 1167 if (WARN_ON(!vop->is_enabled)) 1168 return; 1169 1170 spin_lock_irqsave(&vop->irq_lock, flags); 1171 1172 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1173 1174 spin_unlock_irqrestore(&vop->irq_lock, flags); 1175 } 1176 1177 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1178 const struct drm_display_mode *mode, 1179 struct drm_display_mode *adjusted_mode) 1180 { 1181 struct vop *vop = to_vop(crtc); 1182 unsigned long rate; 1183 1184 /* 1185 * Clock craziness. 1186 * 1187 * Key points: 1188 * 1189 * - DRM works in kHz. 1190 * - Clock framework works in Hz. 1191 * - Rockchip's clock driver picks the clock rate that is the 1192 * same _OR LOWER_ than the one requested. 1193 * 1194 * Action plan: 1195 * 1196 * 1. Try to set the exact rate first, and confirm the clock framework 1197 * can provide it. 1198 * 1199 * 2. If the clock framework cannot provide the exact rate, we should 1200 * add 999 Hz to the requested rate. That way if the clock we need 1201 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then 1202 * the clock framework will actually give us the right clock. 1203 * 1204 * 3. Get the clock framework to round the rate for us to tell us 1205 * what it will actually make. 1206 * 1207 * 4. Store the rounded up rate so that we don't need to worry about 1208 * this in the actual clk_set_rate(). 1209 */ 1210 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000); 1211 if (rate / 1000 != adjusted_mode->clock) 1212 rate = clk_round_rate(vop->dclk, 1213 adjusted_mode->clock * 1000 + 999); 1214 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1215 1216 return true; 1217 } 1218 1219 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1220 { 1221 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1222 } 1223 1224 static u32 vop_lut_buffer_index(struct vop *vop) 1225 { 1226 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); 1227 } 1228 1229 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1230 { 1231 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1232 unsigned int i, bpc = ilog2(vop->data->lut_size); 1233 1234 for (i = 0; i < crtc->gamma_size; i++) { 1235 u32 word; 1236 1237 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | 1238 (drm_color_lut_extract(lut[i].green, bpc) << bpc) | 1239 drm_color_lut_extract(lut[i].blue, bpc); 1240 writel(word, vop->lut_regs + i * 4); 1241 } 1242 } 1243 1244 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1245 struct drm_crtc_state *old_state) 1246 { 1247 struct drm_crtc_state *state = crtc->state; 1248 unsigned int idle; 1249 u32 lut_idx, old_idx; 1250 int ret; 1251 1252 if (!vop->lut_regs) 1253 return; 1254 1255 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { 1256 /* 1257 * To disable gamma (gamma_lut is null) or to write 1258 * an update to the LUT, clear dsp_lut_en. 1259 */ 1260 spin_lock(&vop->reg_lock); 1261 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1262 vop_cfg_done(vop); 1263 spin_unlock(&vop->reg_lock); 1264 1265 /* 1266 * In order to write the LUT to the internal memory, 1267 * we need to first make sure the dsp_lut_en bit is cleared. 1268 */ 1269 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1270 idle, !idle, 5, 30 * 1000); 1271 if (ret) { 1272 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1273 return; 1274 } 1275 1276 if (!state->gamma_lut) 1277 return; 1278 } else { 1279 /* 1280 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, 1281 * by setting update_gamma_lut then waiting for lut_buffer_index change 1282 */ 1283 old_idx = vop_lut_buffer_index(vop); 1284 } 1285 1286 spin_lock(&vop->reg_lock); 1287 vop_crtc_write_gamma_lut(vop, crtc); 1288 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1289 VOP_REG_SET(vop, common, update_gamma_lut, 1); 1290 vop_cfg_done(vop); 1291 spin_unlock(&vop->reg_lock); 1292 1293 if (VOP_HAS_REG(vop, common, update_gamma_lut)) { 1294 ret = readx_poll_timeout(vop_lut_buffer_index, vop, 1295 lut_idx, lut_idx != old_idx, 5, 30 * 1000); 1296 if (ret) { 1297 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); 1298 return; 1299 } 1300 1301 /* 1302 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit 1303 * in our backup of the regs. 1304 */ 1305 spin_lock(&vop->reg_lock); 1306 VOP_REG_SET(vop, common, update_gamma_lut, 0); 1307 spin_unlock(&vop->reg_lock); 1308 } 1309 } 1310 1311 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1312 struct drm_atomic_state *state) 1313 { 1314 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1315 crtc); 1316 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1317 crtc); 1318 struct vop *vop = to_vop(crtc); 1319 1320 /* 1321 * Only update GAMMA if the 'active' flag is not changed, 1322 * otherwise it's updated by .atomic_enable. 1323 */ 1324 if (crtc_state->color_mgmt_changed && 1325 !crtc_state->active_changed) 1326 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1327 } 1328 1329 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1330 struct drm_atomic_state *state) 1331 { 1332 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1333 crtc); 1334 struct vop *vop = to_vop(crtc); 1335 const struct vop_data *vop_data = vop->data; 1336 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1337 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1338 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1339 u16 hdisplay = adjusted_mode->hdisplay; 1340 u16 htotal = adjusted_mode->htotal; 1341 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1342 u16 hact_end = hact_st + hdisplay; 1343 u16 vdisplay = adjusted_mode->vdisplay; 1344 u16 vtotal = adjusted_mode->vtotal; 1345 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1346 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1347 u16 vact_end = vact_st + vdisplay; 1348 uint32_t pin_pol, val; 1349 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1350 int ret; 1351 1352 if (old_state && old_state->self_refresh_active) { 1353 drm_crtc_vblank_on(crtc); 1354 rockchip_drm_set_win_enabled(crtc, true); 1355 return; 1356 } 1357 1358 mutex_lock(&vop->vop_lock); 1359 1360 WARN_ON(vop->event); 1361 1362 ret = vop_enable(crtc, old_state); 1363 if (ret) { 1364 mutex_unlock(&vop->vop_lock); 1365 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1366 return; 1367 } 1368 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1369 BIT(HSYNC_POSITIVE) : 0; 1370 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1371 BIT(VSYNC_POSITIVE) : 0; 1372 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1373 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1374 1375 switch (s->output_type) { 1376 case DRM_MODE_CONNECTOR_LVDS: 1377 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1378 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1379 VOP_REG_SET(vop, output, rgb_en, 1); 1380 break; 1381 case DRM_MODE_CONNECTOR_eDP: 1382 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1383 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1384 VOP_REG_SET(vop, output, edp_en, 1); 1385 break; 1386 case DRM_MODE_CONNECTOR_HDMIA: 1387 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1388 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1389 VOP_REG_SET(vop, output, hdmi_en, 1); 1390 break; 1391 case DRM_MODE_CONNECTOR_DSI: 1392 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1393 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1394 VOP_REG_SET(vop, output, mipi_en, 1); 1395 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1396 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1397 break; 1398 case DRM_MODE_CONNECTOR_DisplayPort: 1399 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1400 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1401 VOP_REG_SET(vop, output, dp_en, 1); 1402 break; 1403 default: 1404 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1405 s->output_type); 1406 } 1407 1408 /* 1409 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1410 */ 1411 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1412 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1413 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1414 1415 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1416 VOP_REG_SET(vop, common, pre_dither_down, 1); 1417 else 1418 VOP_REG_SET(vop, common, pre_dither_down, 0); 1419 1420 if (dither_bpc == 6) { 1421 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1422 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1423 VOP_REG_SET(vop, common, dither_down_en, 1); 1424 } else { 1425 VOP_REG_SET(vop, common, dither_down_en, 0); 1426 } 1427 1428 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1429 1430 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1431 val = hact_st << 16; 1432 val |= hact_end; 1433 VOP_REG_SET(vop, modeset, hact_st_end, val); 1434 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1435 1436 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1437 val = vact_st << 16; 1438 val |= vact_end; 1439 VOP_REG_SET(vop, modeset, vact_st_end, val); 1440 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1441 1442 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1443 1444 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1445 1446 VOP_REG_SET(vop, common, standby, 0); 1447 mutex_unlock(&vop->vop_lock); 1448 1449 /* 1450 * If we have a GAMMA LUT in the state, then let's make sure 1451 * it's updated. We might be coming out of suspend, 1452 * which means the LUT internal memory needs to be re-written. 1453 */ 1454 if (crtc->state->gamma_lut) 1455 vop_crtc_gamma_set(vop, crtc, old_state); 1456 } 1457 1458 static bool vop_fs_irq_is_pending(struct vop *vop) 1459 { 1460 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1461 } 1462 1463 static void vop_wait_for_irq_handler(struct vop *vop) 1464 { 1465 bool pending; 1466 int ret; 1467 1468 /* 1469 * Spin until frame start interrupt status bit goes low, which means 1470 * that interrupt handler was invoked and cleared it. The timeout of 1471 * 10 msecs is really too long, but it is just a safety measure if 1472 * something goes really wrong. The wait will only happen in the very 1473 * unlikely case of a vblank happening exactly at the same time and 1474 * shouldn't exceed microseconds range. 1475 */ 1476 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1477 !pending, 0, 10 * 1000); 1478 if (ret) 1479 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1480 1481 synchronize_irq(vop->irq); 1482 } 1483 1484 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1485 struct drm_atomic_state *state) 1486 { 1487 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1488 crtc); 1489 struct vop *vop = to_vop(crtc); 1490 struct drm_plane *plane; 1491 struct drm_plane_state *plane_state; 1492 struct rockchip_crtc_state *s; 1493 int afbc_planes = 0; 1494 1495 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1496 crtc_state->gamma_lut) { 1497 unsigned int len; 1498 1499 len = drm_color_lut_size(crtc_state->gamma_lut); 1500 if (len != crtc->gamma_size) { 1501 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1502 len, crtc->gamma_size); 1503 return -EINVAL; 1504 } 1505 } 1506 1507 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1508 plane_state = 1509 drm_atomic_get_plane_state(crtc_state->state, plane); 1510 if (IS_ERR(plane_state)) { 1511 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1512 plane->name); 1513 return PTR_ERR(plane_state); 1514 } 1515 1516 if (drm_is_afbc(plane_state->fb->modifier)) 1517 ++afbc_planes; 1518 } 1519 1520 if (afbc_planes > 1) { 1521 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1522 return -EINVAL; 1523 } 1524 1525 s = to_rockchip_crtc_state(crtc_state); 1526 s->enable_afbc = afbc_planes > 0; 1527 1528 return 0; 1529 } 1530 1531 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1532 struct drm_atomic_state *state) 1533 { 1534 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1535 crtc); 1536 struct drm_atomic_state *old_state = old_crtc_state->state; 1537 struct drm_plane_state *old_plane_state, *new_plane_state; 1538 struct vop *vop = to_vop(crtc); 1539 struct drm_plane *plane; 1540 struct rockchip_crtc_state *s; 1541 int i; 1542 1543 if (WARN_ON(!vop->is_enabled)) 1544 return; 1545 1546 spin_lock(&vop->reg_lock); 1547 1548 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1549 s = to_rockchip_crtc_state(crtc->state); 1550 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1551 vop_cfg_done(vop); 1552 1553 spin_unlock(&vop->reg_lock); 1554 1555 /* 1556 * There is a (rather unlikely) possiblity that a vblank interrupt 1557 * fired before we set the cfg_done bit. To avoid spuriously 1558 * signalling flip completion we need to wait for it to finish. 1559 */ 1560 vop_wait_for_irq_handler(vop); 1561 1562 spin_lock_irq(&crtc->dev->event_lock); 1563 if (crtc->state->event) { 1564 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1565 WARN_ON(vop->event); 1566 1567 vop->event = crtc->state->event; 1568 crtc->state->event = NULL; 1569 } 1570 spin_unlock_irq(&crtc->dev->event_lock); 1571 1572 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1573 new_plane_state, i) { 1574 if (!old_plane_state->fb) 1575 continue; 1576 1577 if (old_plane_state->fb == new_plane_state->fb) 1578 continue; 1579 1580 drm_framebuffer_get(old_plane_state->fb); 1581 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1582 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1583 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1584 } 1585 } 1586 1587 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1588 .mode_fixup = vop_crtc_mode_fixup, 1589 .atomic_check = vop_crtc_atomic_check, 1590 .atomic_begin = vop_crtc_atomic_begin, 1591 .atomic_flush = vop_crtc_atomic_flush, 1592 .atomic_enable = vop_crtc_atomic_enable, 1593 .atomic_disable = vop_crtc_atomic_disable, 1594 }; 1595 1596 static void vop_crtc_destroy(struct drm_crtc *crtc) 1597 { 1598 drm_crtc_cleanup(crtc); 1599 } 1600 1601 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1602 { 1603 struct rockchip_crtc_state *rockchip_state; 1604 1605 if (WARN_ON(!crtc->state)) 1606 return NULL; 1607 1608 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1609 if (!rockchip_state) 1610 return NULL; 1611 1612 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1613 return &rockchip_state->base; 1614 } 1615 1616 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1617 struct drm_crtc_state *state) 1618 { 1619 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1620 1621 __drm_atomic_helper_crtc_destroy_state(&s->base); 1622 kfree(s); 1623 } 1624 1625 static void vop_crtc_reset(struct drm_crtc *crtc) 1626 { 1627 struct rockchip_crtc_state *crtc_state = 1628 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1629 1630 if (crtc->state) 1631 vop_crtc_destroy_state(crtc, crtc->state); 1632 1633 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1634 } 1635 1636 #ifdef CONFIG_DRM_ANALOGIX_DP 1637 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1638 { 1639 struct drm_connector *connector; 1640 struct drm_connector_list_iter conn_iter; 1641 1642 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1643 drm_for_each_connector_iter(connector, &conn_iter) { 1644 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1645 drm_connector_list_iter_end(&conn_iter); 1646 return connector; 1647 } 1648 } 1649 drm_connector_list_iter_end(&conn_iter); 1650 1651 return NULL; 1652 } 1653 1654 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1655 const char *source_name) 1656 { 1657 struct vop *vop = to_vop(crtc); 1658 struct drm_connector *connector; 1659 int ret; 1660 1661 connector = vop_get_edp_connector(vop); 1662 if (!connector) 1663 return -EINVAL; 1664 1665 if (source_name && strcmp(source_name, "auto") == 0) 1666 ret = analogix_dp_start_crc(connector); 1667 else if (!source_name) 1668 ret = analogix_dp_stop_crc(connector); 1669 else 1670 ret = -EINVAL; 1671 1672 return ret; 1673 } 1674 1675 static int 1676 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1677 size_t *values_cnt) 1678 { 1679 if (source_name && strcmp(source_name, "auto") != 0) 1680 return -EINVAL; 1681 1682 *values_cnt = 3; 1683 return 0; 1684 } 1685 1686 #else 1687 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1688 const char *source_name) 1689 { 1690 return -ENODEV; 1691 } 1692 1693 static int 1694 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1695 size_t *values_cnt) 1696 { 1697 return -ENODEV; 1698 } 1699 #endif 1700 1701 static const struct drm_crtc_funcs vop_crtc_funcs = { 1702 .set_config = drm_atomic_helper_set_config, 1703 .page_flip = drm_atomic_helper_page_flip, 1704 .destroy = vop_crtc_destroy, 1705 .reset = vop_crtc_reset, 1706 .atomic_duplicate_state = vop_crtc_duplicate_state, 1707 .atomic_destroy_state = vop_crtc_destroy_state, 1708 .enable_vblank = vop_crtc_enable_vblank, 1709 .disable_vblank = vop_crtc_disable_vblank, 1710 .set_crc_source = vop_crtc_set_crc_source, 1711 .verify_crc_source = vop_crtc_verify_crc_source, 1712 }; 1713 1714 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1715 { 1716 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1717 struct drm_framebuffer *fb = val; 1718 1719 drm_crtc_vblank_put(&vop->crtc); 1720 drm_framebuffer_put(fb); 1721 } 1722 1723 static void vop_handle_vblank(struct vop *vop) 1724 { 1725 struct drm_device *drm = vop->drm_dev; 1726 struct drm_crtc *crtc = &vop->crtc; 1727 1728 spin_lock(&drm->event_lock); 1729 if (vop->event) { 1730 drm_crtc_send_vblank_event(crtc, vop->event); 1731 drm_crtc_vblank_put(crtc); 1732 vop->event = NULL; 1733 } 1734 spin_unlock(&drm->event_lock); 1735 1736 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1737 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1738 } 1739 1740 static irqreturn_t vop_isr(int irq, void *data) 1741 { 1742 struct vop *vop = data; 1743 struct drm_crtc *crtc = &vop->crtc; 1744 uint32_t active_irqs; 1745 int ret = IRQ_NONE; 1746 1747 /* 1748 * The irq is shared with the iommu. If the runtime-pm state of the 1749 * vop-device is disabled the irq has to be targeted at the iommu. 1750 */ 1751 if (!pm_runtime_get_if_in_use(vop->dev)) 1752 return IRQ_NONE; 1753 1754 if (vop_core_clks_enable(vop)) { 1755 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1756 goto out; 1757 } 1758 1759 /* 1760 * interrupt register has interrupt status, enable and clear bits, we 1761 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1762 */ 1763 spin_lock(&vop->irq_lock); 1764 1765 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1766 /* Clear all active interrupt sources */ 1767 if (active_irqs) 1768 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1769 1770 spin_unlock(&vop->irq_lock); 1771 1772 /* This is expected for vop iommu irqs, since the irq is shared */ 1773 if (!active_irqs) 1774 goto out_disable; 1775 1776 if (active_irqs & DSP_HOLD_VALID_INTR) { 1777 complete(&vop->dsp_hold_completion); 1778 active_irqs &= ~DSP_HOLD_VALID_INTR; 1779 ret = IRQ_HANDLED; 1780 } 1781 1782 if (active_irqs & LINE_FLAG_INTR) { 1783 complete(&vop->line_flag_completion); 1784 active_irqs &= ~LINE_FLAG_INTR; 1785 ret = IRQ_HANDLED; 1786 } 1787 1788 if (active_irqs & FS_INTR) { 1789 drm_crtc_handle_vblank(crtc); 1790 vop_handle_vblank(vop); 1791 active_irqs &= ~FS_INTR; 1792 ret = IRQ_HANDLED; 1793 } 1794 1795 /* Unhandled irqs are spurious. */ 1796 if (active_irqs) 1797 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1798 active_irqs); 1799 1800 out_disable: 1801 vop_core_clks_disable(vop); 1802 out: 1803 pm_runtime_put(vop->dev); 1804 return ret; 1805 } 1806 1807 static void vop_plane_add_properties(struct drm_plane *plane, 1808 const struct vop_win_data *win_data) 1809 { 1810 unsigned int flags = 0; 1811 1812 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1813 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1814 if (flags) 1815 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1816 DRM_MODE_ROTATE_0 | flags); 1817 } 1818 1819 static int vop_create_crtc(struct vop *vop) 1820 { 1821 const struct vop_data *vop_data = vop->data; 1822 struct device *dev = vop->dev; 1823 struct drm_device *drm_dev = vop->drm_dev; 1824 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1825 struct drm_crtc *crtc = &vop->crtc; 1826 struct device_node *port; 1827 int ret; 1828 int i; 1829 1830 /* 1831 * Create drm_plane for primary and cursor planes first, since we need 1832 * to pass them to drm_crtc_init_with_planes, which sets the 1833 * "possible_crtcs" to the newly initialized crtc. 1834 */ 1835 for (i = 0; i < vop_data->win_size; i++) { 1836 struct vop_win *vop_win = &vop->win[i]; 1837 const struct vop_win_data *win_data = vop_win->data; 1838 1839 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1840 win_data->type != DRM_PLANE_TYPE_CURSOR) 1841 continue; 1842 1843 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1844 0, &vop_plane_funcs, 1845 win_data->phy->data_formats, 1846 win_data->phy->nformats, 1847 win_data->phy->format_modifiers, 1848 win_data->type, NULL); 1849 if (ret) { 1850 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1851 ret); 1852 goto err_cleanup_planes; 1853 } 1854 1855 plane = &vop_win->base; 1856 drm_plane_helper_add(plane, &plane_helper_funcs); 1857 vop_plane_add_properties(plane, win_data); 1858 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1859 primary = plane; 1860 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1861 cursor = plane; 1862 } 1863 1864 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1865 &vop_crtc_funcs, NULL); 1866 if (ret) 1867 goto err_cleanup_planes; 1868 1869 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1870 if (vop->lut_regs) { 1871 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1872 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1873 } 1874 1875 /* 1876 * Create drm_planes for overlay windows with possible_crtcs restricted 1877 * to the newly created crtc. 1878 */ 1879 for (i = 0; i < vop_data->win_size; i++) { 1880 struct vop_win *vop_win = &vop->win[i]; 1881 const struct vop_win_data *win_data = vop_win->data; 1882 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1883 1884 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1885 continue; 1886 1887 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1888 possible_crtcs, 1889 &vop_plane_funcs, 1890 win_data->phy->data_formats, 1891 win_data->phy->nformats, 1892 win_data->phy->format_modifiers, 1893 win_data->type, NULL); 1894 if (ret) { 1895 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1896 ret); 1897 goto err_cleanup_crtc; 1898 } 1899 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1900 vop_plane_add_properties(&vop_win->base, win_data); 1901 } 1902 1903 port = of_get_child_by_name(dev->of_node, "port"); 1904 if (!port) { 1905 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1906 dev->of_node); 1907 ret = -ENOENT; 1908 goto err_cleanup_crtc; 1909 } 1910 1911 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1912 vop_fb_unref_worker); 1913 1914 init_completion(&vop->dsp_hold_completion); 1915 init_completion(&vop->line_flag_completion); 1916 crtc->port = port; 1917 1918 ret = drm_self_refresh_helper_init(crtc); 1919 if (ret) 1920 DRM_DEV_DEBUG_KMS(vop->dev, 1921 "Failed to init %s with SR helpers %d, ignoring\n", 1922 crtc->name, ret); 1923 1924 return 0; 1925 1926 err_cleanup_crtc: 1927 drm_crtc_cleanup(crtc); 1928 err_cleanup_planes: 1929 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1930 head) 1931 drm_plane_cleanup(plane); 1932 return ret; 1933 } 1934 1935 static void vop_destroy_crtc(struct vop *vop) 1936 { 1937 struct drm_crtc *crtc = &vop->crtc; 1938 struct drm_device *drm_dev = vop->drm_dev; 1939 struct drm_plane *plane, *tmp; 1940 1941 drm_self_refresh_helper_cleanup(crtc); 1942 1943 of_node_put(crtc->port); 1944 1945 /* 1946 * We need to cleanup the planes now. Why? 1947 * 1948 * The planes are "&vop->win[i].base". That means the memory is 1949 * all part of the big "struct vop" chunk of memory. That memory 1950 * was devm allocated and associated with this component. We need to 1951 * free it ourselves before vop_unbind() finishes. 1952 */ 1953 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1954 head) 1955 vop_plane_destroy(plane); 1956 1957 /* 1958 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1959 * references the CRTC. 1960 */ 1961 drm_crtc_cleanup(crtc); 1962 drm_flip_work_cleanup(&vop->fb_unref_work); 1963 } 1964 1965 static int vop_initial(struct vop *vop) 1966 { 1967 struct reset_control *ahb_rst; 1968 int i, ret; 1969 1970 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1971 if (IS_ERR(vop->hclk)) { 1972 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1973 return PTR_ERR(vop->hclk); 1974 } 1975 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1976 if (IS_ERR(vop->aclk)) { 1977 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1978 return PTR_ERR(vop->aclk); 1979 } 1980 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1981 if (IS_ERR(vop->dclk)) { 1982 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1983 return PTR_ERR(vop->dclk); 1984 } 1985 1986 ret = pm_runtime_get_sync(vop->dev); 1987 if (ret < 0) { 1988 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1989 return ret; 1990 } 1991 1992 ret = clk_prepare(vop->dclk); 1993 if (ret < 0) { 1994 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1995 goto err_put_pm_runtime; 1996 } 1997 1998 /* Enable both the hclk and aclk to setup the vop */ 1999 ret = clk_prepare_enable(vop->hclk); 2000 if (ret < 0) { 2001 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 2002 goto err_unprepare_dclk; 2003 } 2004 2005 ret = clk_prepare_enable(vop->aclk); 2006 if (ret < 0) { 2007 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 2008 goto err_disable_hclk; 2009 } 2010 2011 /* 2012 * do hclk_reset, reset all vop registers. 2013 */ 2014 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 2015 if (IS_ERR(ahb_rst)) { 2016 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 2017 ret = PTR_ERR(ahb_rst); 2018 goto err_disable_aclk; 2019 } 2020 reset_control_assert(ahb_rst); 2021 usleep_range(10, 20); 2022 reset_control_deassert(ahb_rst); 2023 2024 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 2025 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 2026 2027 for (i = 0; i < vop->len; i += sizeof(u32)) 2028 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 2029 2030 VOP_REG_SET(vop, misc, global_regdone_en, 1); 2031 VOP_REG_SET(vop, common, dsp_blank, 0); 2032 2033 for (i = 0; i < vop->data->win_size; i++) { 2034 struct vop_win *vop_win = &vop->win[i]; 2035 const struct vop_win_data *win = vop_win->data; 2036 int channel = i * 2 + 1; 2037 2038 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 2039 vop_win_disable(vop, vop_win); 2040 VOP_WIN_SET(vop, win, gate, 1); 2041 } 2042 2043 vop_cfg_done(vop); 2044 2045 /* 2046 * do dclk_reset, let all config take affect. 2047 */ 2048 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 2049 if (IS_ERR(vop->dclk_rst)) { 2050 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2051 ret = PTR_ERR(vop->dclk_rst); 2052 goto err_disable_aclk; 2053 } 2054 reset_control_assert(vop->dclk_rst); 2055 usleep_range(10, 20); 2056 reset_control_deassert(vop->dclk_rst); 2057 2058 clk_disable(vop->hclk); 2059 clk_disable(vop->aclk); 2060 2061 vop->is_enabled = false; 2062 2063 pm_runtime_put_sync(vop->dev); 2064 2065 return 0; 2066 2067 err_disable_aclk: 2068 clk_disable_unprepare(vop->aclk); 2069 err_disable_hclk: 2070 clk_disable_unprepare(vop->hclk); 2071 err_unprepare_dclk: 2072 clk_unprepare(vop->dclk); 2073 err_put_pm_runtime: 2074 pm_runtime_put_sync(vop->dev); 2075 return ret; 2076 } 2077 2078 /* 2079 * Initialize the vop->win array elements. 2080 */ 2081 static void vop_win_init(struct vop *vop) 2082 { 2083 const struct vop_data *vop_data = vop->data; 2084 unsigned int i; 2085 2086 for (i = 0; i < vop_data->win_size; i++) { 2087 struct vop_win *vop_win = &vop->win[i]; 2088 const struct vop_win_data *win_data = &vop_data->win[i]; 2089 2090 vop_win->data = win_data; 2091 vop_win->vop = vop; 2092 2093 if (vop_data->win_yuv2yuv) 2094 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2095 } 2096 } 2097 2098 /** 2099 * rockchip_drm_wait_vact_end 2100 * @crtc: CRTC to enable line flag 2101 * @mstimeout: millisecond for timeout 2102 * 2103 * Wait for vact_end line flag irq or timeout. 2104 * 2105 * Returns: 2106 * Zero on success, negative errno on failure. 2107 */ 2108 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2109 { 2110 struct vop *vop = to_vop(crtc); 2111 unsigned long jiffies_left; 2112 int ret = 0; 2113 2114 if (!crtc || !vop->is_enabled) 2115 return -ENODEV; 2116 2117 mutex_lock(&vop->vop_lock); 2118 if (mstimeout <= 0) { 2119 ret = -EINVAL; 2120 goto out; 2121 } 2122 2123 if (vop_line_flag_irq_is_enabled(vop)) { 2124 ret = -EBUSY; 2125 goto out; 2126 } 2127 2128 reinit_completion(&vop->line_flag_completion); 2129 vop_line_flag_irq_enable(vop); 2130 2131 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2132 msecs_to_jiffies(mstimeout)); 2133 vop_line_flag_irq_disable(vop); 2134 2135 if (jiffies_left == 0) { 2136 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2137 ret = -ETIMEDOUT; 2138 goto out; 2139 } 2140 2141 out: 2142 mutex_unlock(&vop->vop_lock); 2143 return ret; 2144 } 2145 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2146 2147 static int vop_bind(struct device *dev, struct device *master, void *data) 2148 { 2149 struct platform_device *pdev = to_platform_device(dev); 2150 const struct vop_data *vop_data; 2151 struct drm_device *drm_dev = data; 2152 struct vop *vop; 2153 struct resource *res; 2154 int ret, irq; 2155 2156 vop_data = of_device_get_match_data(dev); 2157 if (!vop_data) 2158 return -ENODEV; 2159 2160 /* Allocate vop struct and its vop_win array */ 2161 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2162 GFP_KERNEL); 2163 if (!vop) 2164 return -ENOMEM; 2165 2166 vop->dev = dev; 2167 vop->data = vop_data; 2168 vop->drm_dev = drm_dev; 2169 dev_set_drvdata(dev, vop); 2170 2171 vop_win_init(vop); 2172 2173 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2174 vop->regs = devm_ioremap_resource(dev, res); 2175 if (IS_ERR(vop->regs)) 2176 return PTR_ERR(vop->regs); 2177 vop->len = resource_size(res); 2178 2179 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2180 if (res) { 2181 if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { 2182 DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); 2183 return -EINVAL; 2184 } 2185 vop->lut_regs = devm_ioremap_resource(dev, res); 2186 if (IS_ERR(vop->lut_regs)) 2187 return PTR_ERR(vop->lut_regs); 2188 } 2189 2190 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2191 if (!vop->regsbak) 2192 return -ENOMEM; 2193 2194 irq = platform_get_irq(pdev, 0); 2195 if (irq < 0) { 2196 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2197 return irq; 2198 } 2199 vop->irq = (unsigned int)irq; 2200 2201 spin_lock_init(&vop->reg_lock); 2202 spin_lock_init(&vop->irq_lock); 2203 mutex_init(&vop->vop_lock); 2204 2205 ret = vop_create_crtc(vop); 2206 if (ret) 2207 return ret; 2208 2209 pm_runtime_enable(&pdev->dev); 2210 2211 ret = vop_initial(vop); 2212 if (ret < 0) { 2213 DRM_DEV_ERROR(&pdev->dev, 2214 "cannot initial vop dev - err %d\n", ret); 2215 goto err_disable_pm_runtime; 2216 } 2217 2218 ret = devm_request_irq(dev, vop->irq, vop_isr, 2219 IRQF_SHARED, dev_name(dev), vop); 2220 if (ret) 2221 goto err_disable_pm_runtime; 2222 2223 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2224 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 2225 if (IS_ERR(vop->rgb)) { 2226 ret = PTR_ERR(vop->rgb); 2227 goto err_disable_pm_runtime; 2228 } 2229 } 2230 2231 rockchip_drm_dma_init_device(drm_dev, dev); 2232 2233 return 0; 2234 2235 err_disable_pm_runtime: 2236 pm_runtime_disable(&pdev->dev); 2237 vop_destroy_crtc(vop); 2238 return ret; 2239 } 2240 2241 static void vop_unbind(struct device *dev, struct device *master, void *data) 2242 { 2243 struct vop *vop = dev_get_drvdata(dev); 2244 2245 if (vop->rgb) 2246 rockchip_rgb_fini(vop->rgb); 2247 2248 pm_runtime_disable(dev); 2249 vop_destroy_crtc(vop); 2250 2251 clk_unprepare(vop->aclk); 2252 clk_unprepare(vop->hclk); 2253 clk_unprepare(vop->dclk); 2254 } 2255 2256 const struct component_ops vop_component_ops = { 2257 .bind = vop_bind, 2258 .unbind = vop_unbind, 2259 }; 2260 EXPORT_SYMBOL_GPL(vop_component_ops); 2261