1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_plane_helper.h> 22 #ifdef CONFIG_DRM_ANALOGIX_DP 23 #include <drm/bridge/analogix_dp.h> 24 #endif 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/iopoll.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/component.h> 35 36 #include <linux/reset.h> 37 #include <linux/delay.h> 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_psr.h" 43 #include "rockchip_drm_vop.h" 44 45 #define VOP_WIN_SET(x, win, name, v) \ 46 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET(x, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 49 #define VOP_SCL_SET_EXT(x, win, name, v) \ 50 vop_reg_set(vop, &win->phy->scl->ext->name, \ 51 win->base, ~0, v, #name) 52 53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 54 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 55 56 #define VOP_REG_SET(vop, group, name, v) \ 57 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58 59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60 do { \ 61 int i, reg = 0, mask = 0; \ 62 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63 if (vop->data->intr->intrs[i] & type) { \ 64 reg |= (v) << i; \ 65 mask |= 1 << i; \ 66 } \ 67 } \ 68 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69 } while (0) 70 #define VOP_INTR_GET_TYPE(vop, name, type) \ 71 vop_get_intr_type(vop, &vop->data->intr->name, type) 72 73 #define VOP_WIN_GET(x, win, name) \ 74 vop_read_reg(x, win->offset, win->phy->name) 75 76 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 77 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 78 79 #define to_vop(x) container_of(x, struct vop, crtc) 80 #define to_vop_win(x) container_of(x, struct vop_win, base) 81 82 enum vop_pending { 83 VOP_PENDING_FB_UNREF, 84 }; 85 86 struct vop_win { 87 struct drm_plane base; 88 const struct vop_win_data *data; 89 struct vop *vop; 90 }; 91 92 struct vop { 93 struct drm_crtc crtc; 94 struct device *dev; 95 struct drm_device *drm_dev; 96 bool is_enabled; 97 98 struct completion dsp_hold_completion; 99 100 /* protected by dev->event_lock */ 101 struct drm_pending_vblank_event *event; 102 103 struct drm_flip_work fb_unref_work; 104 unsigned long pending; 105 106 struct completion line_flag_completion; 107 108 const struct vop_data *data; 109 110 uint32_t *regsbak; 111 void __iomem *regs; 112 113 /* physical map length of vop register */ 114 uint32_t len; 115 116 /* one time only one process allowed to config the register */ 117 spinlock_t reg_lock; 118 /* lock vop irq reg */ 119 spinlock_t irq_lock; 120 /* protects crtc enable/disable */ 121 struct mutex vop_lock; 122 123 unsigned int irq; 124 125 /* vop AHP clk */ 126 struct clk *hclk; 127 /* vop dclk */ 128 struct clk *dclk; 129 /* vop share memory frequency */ 130 struct clk *aclk; 131 132 /* vop dclk reset */ 133 struct reset_control *dclk_rst; 134 135 struct vop_win win[]; 136 }; 137 138 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 139 { 140 writel(v, vop->regs + offset); 141 vop->regsbak[offset >> 2] = v; 142 } 143 144 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 145 { 146 return readl(vop->regs + offset); 147 } 148 149 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 150 const struct vop_reg *reg) 151 { 152 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 153 } 154 155 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 156 uint32_t _offset, uint32_t _mask, uint32_t v, 157 const char *reg_name) 158 { 159 int offset, mask, shift; 160 161 if (!reg || !reg->mask) { 162 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 163 return; 164 } 165 166 offset = reg->offset + _offset; 167 mask = reg->mask & _mask; 168 shift = reg->shift; 169 170 if (reg->write_mask) { 171 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 172 } else { 173 uint32_t cached_val = vop->regsbak[offset >> 2]; 174 175 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 176 vop->regsbak[offset >> 2] = v; 177 } 178 179 if (reg->relaxed) 180 writel_relaxed(v, vop->regs + offset); 181 else 182 writel(v, vop->regs + offset); 183 } 184 185 static inline uint32_t vop_get_intr_type(struct vop *vop, 186 const struct vop_reg *reg, int type) 187 { 188 uint32_t i, ret = 0; 189 uint32_t regs = vop_read_reg(vop, 0, reg); 190 191 for (i = 0; i < vop->data->intr->nintrs; i++) { 192 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 193 ret |= vop->data->intr->intrs[i]; 194 } 195 196 return ret; 197 } 198 199 static inline void vop_cfg_done(struct vop *vop) 200 { 201 VOP_REG_SET(vop, common, cfg_done, 1); 202 } 203 204 static bool has_rb_swapped(uint32_t format) 205 { 206 switch (format) { 207 case DRM_FORMAT_XBGR8888: 208 case DRM_FORMAT_ABGR8888: 209 case DRM_FORMAT_BGR888: 210 case DRM_FORMAT_BGR565: 211 return true; 212 default: 213 return false; 214 } 215 } 216 217 static enum vop_data_format vop_convert_format(uint32_t format) 218 { 219 switch (format) { 220 case DRM_FORMAT_XRGB8888: 221 case DRM_FORMAT_ARGB8888: 222 case DRM_FORMAT_XBGR8888: 223 case DRM_FORMAT_ABGR8888: 224 return VOP_FMT_ARGB8888; 225 case DRM_FORMAT_RGB888: 226 case DRM_FORMAT_BGR888: 227 return VOP_FMT_RGB888; 228 case DRM_FORMAT_RGB565: 229 case DRM_FORMAT_BGR565: 230 return VOP_FMT_RGB565; 231 case DRM_FORMAT_NV12: 232 return VOP_FMT_YUV420SP; 233 case DRM_FORMAT_NV16: 234 return VOP_FMT_YUV422SP; 235 case DRM_FORMAT_NV24: 236 return VOP_FMT_YUV444SP; 237 default: 238 DRM_ERROR("unsupported format[%08x]\n", format); 239 return -EINVAL; 240 } 241 } 242 243 static bool is_yuv_support(uint32_t format) 244 { 245 switch (format) { 246 case DRM_FORMAT_NV12: 247 case DRM_FORMAT_NV16: 248 case DRM_FORMAT_NV24: 249 return true; 250 default: 251 return false; 252 } 253 } 254 255 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 256 uint32_t dst, bool is_horizontal, 257 int vsu_mode, int *vskiplines) 258 { 259 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 260 261 if (vskiplines) 262 *vskiplines = 0; 263 264 if (is_horizontal) { 265 if (mode == SCALE_UP) 266 val = GET_SCL_FT_BIC(src, dst); 267 else if (mode == SCALE_DOWN) 268 val = GET_SCL_FT_BILI_DN(src, dst); 269 } else { 270 if (mode == SCALE_UP) { 271 if (vsu_mode == SCALE_UP_BIL) 272 val = GET_SCL_FT_BILI_UP(src, dst); 273 else 274 val = GET_SCL_FT_BIC(src, dst); 275 } else if (mode == SCALE_DOWN) { 276 if (vskiplines) { 277 *vskiplines = scl_get_vskiplines(src, dst); 278 val = scl_get_bili_dn_vskip(src, dst, 279 *vskiplines); 280 } else { 281 val = GET_SCL_FT_BILI_DN(src, dst); 282 } 283 } 284 } 285 286 return val; 287 } 288 289 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 290 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 291 uint32_t dst_h, uint32_t pixel_format) 292 { 293 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 294 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 295 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 296 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 297 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 298 bool is_yuv = is_yuv_support(pixel_format); 299 uint16_t cbcr_src_w = src_w / hsub; 300 uint16_t cbcr_src_h = src_h / vsub; 301 uint16_t vsu_mode; 302 uint16_t lb_mode; 303 uint32_t val; 304 int vskiplines; 305 306 if (dst_w > 3840) { 307 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 308 return; 309 } 310 311 if (!win->phy->scl->ext) { 312 VOP_SCL_SET(vop, win, scale_yrgb_x, 313 scl_cal_scale2(src_w, dst_w)); 314 VOP_SCL_SET(vop, win, scale_yrgb_y, 315 scl_cal_scale2(src_h, dst_h)); 316 if (is_yuv) { 317 VOP_SCL_SET(vop, win, scale_cbcr_x, 318 scl_cal_scale2(cbcr_src_w, dst_w)); 319 VOP_SCL_SET(vop, win, scale_cbcr_y, 320 scl_cal_scale2(cbcr_src_h, dst_h)); 321 } 322 return; 323 } 324 325 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 326 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 327 328 if (is_yuv) { 329 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 330 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 331 if (cbcr_hor_scl_mode == SCALE_DOWN) 332 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 333 else 334 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 335 } else { 336 if (yrgb_hor_scl_mode == SCALE_DOWN) 337 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 338 else 339 lb_mode = scl_vop_cal_lb_mode(src_w, false); 340 } 341 342 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 343 if (lb_mode == LB_RGB_3840X2) { 344 if (yrgb_ver_scl_mode != SCALE_NONE) { 345 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 346 return; 347 } 348 if (cbcr_ver_scl_mode != SCALE_NONE) { 349 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 350 return; 351 } 352 vsu_mode = SCALE_UP_BIL; 353 } else if (lb_mode == LB_RGB_2560X4) { 354 vsu_mode = SCALE_UP_BIL; 355 } else { 356 vsu_mode = SCALE_UP_BIC; 357 } 358 359 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 360 true, 0, NULL); 361 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 362 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 363 false, vsu_mode, &vskiplines); 364 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 365 366 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 367 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 368 369 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 370 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 371 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 372 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 373 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 374 if (is_yuv) { 375 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 376 dst_w, true, 0, NULL); 377 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 378 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 379 dst_h, false, vsu_mode, &vskiplines); 380 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 381 382 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 383 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 384 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 385 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 386 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 387 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 388 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 389 } 390 } 391 392 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 393 { 394 unsigned long flags; 395 396 if (WARN_ON(!vop->is_enabled)) 397 return; 398 399 spin_lock_irqsave(&vop->irq_lock, flags); 400 401 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 402 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 403 404 spin_unlock_irqrestore(&vop->irq_lock, flags); 405 } 406 407 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 408 { 409 unsigned long flags; 410 411 if (WARN_ON(!vop->is_enabled)) 412 return; 413 414 spin_lock_irqsave(&vop->irq_lock, flags); 415 416 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 417 418 spin_unlock_irqrestore(&vop->irq_lock, flags); 419 } 420 421 /* 422 * (1) each frame starts at the start of the Vsync pulse which is signaled by 423 * the "FRAME_SYNC" interrupt. 424 * (2) the active data region of each frame ends at dsp_vact_end 425 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 426 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 427 * 428 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 429 * Interrupts 430 * LINE_FLAG -------------------------------+ 431 * FRAME_SYNC ----+ | 432 * | | 433 * v v 434 * | Vsync | Vbp | Vactive | Vfp | 435 * ^ ^ ^ ^ 436 * | | | | 437 * | | | | 438 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 439 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 440 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 441 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 442 */ 443 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 444 { 445 uint32_t line_flag_irq; 446 unsigned long flags; 447 448 spin_lock_irqsave(&vop->irq_lock, flags); 449 450 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 451 452 spin_unlock_irqrestore(&vop->irq_lock, flags); 453 454 return !!line_flag_irq; 455 } 456 457 static void vop_line_flag_irq_enable(struct vop *vop) 458 { 459 unsigned long flags; 460 461 if (WARN_ON(!vop->is_enabled)) 462 return; 463 464 spin_lock_irqsave(&vop->irq_lock, flags); 465 466 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 467 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 468 469 spin_unlock_irqrestore(&vop->irq_lock, flags); 470 } 471 472 static void vop_line_flag_irq_disable(struct vop *vop) 473 { 474 unsigned long flags; 475 476 if (WARN_ON(!vop->is_enabled)) 477 return; 478 479 spin_lock_irqsave(&vop->irq_lock, flags); 480 481 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 482 483 spin_unlock_irqrestore(&vop->irq_lock, flags); 484 } 485 486 static int vop_enable(struct drm_crtc *crtc) 487 { 488 struct vop *vop = to_vop(crtc); 489 int ret, i; 490 491 ret = pm_runtime_get_sync(vop->dev); 492 if (ret < 0) { 493 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 494 return ret; 495 } 496 497 ret = clk_enable(vop->hclk); 498 if (WARN_ON(ret < 0)) 499 goto err_put_pm_runtime; 500 501 ret = clk_enable(vop->dclk); 502 if (WARN_ON(ret < 0)) 503 goto err_disable_hclk; 504 505 ret = clk_enable(vop->aclk); 506 if (WARN_ON(ret < 0)) 507 goto err_disable_dclk; 508 509 /* 510 * Slave iommu shares power, irq and clock with vop. It was associated 511 * automatically with this master device via common driver code. 512 * Now that we have enabled the clock we attach it to the shared drm 513 * mapping. 514 */ 515 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 516 if (ret) { 517 DRM_DEV_ERROR(vop->dev, 518 "failed to attach dma mapping, %d\n", ret); 519 goto err_disable_aclk; 520 } 521 522 spin_lock(&vop->reg_lock); 523 for (i = 0; i < vop->len; i += 4) 524 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 525 526 /* 527 * We need to make sure that all windows are disabled before we 528 * enable the crtc. Otherwise we might try to scan from a destroyed 529 * buffer later. 530 */ 531 for (i = 0; i < vop->data->win_size; i++) { 532 struct vop_win *vop_win = &vop->win[i]; 533 const struct vop_win_data *win = vop_win->data; 534 535 VOP_WIN_SET(vop, win, enable, 0); 536 } 537 spin_unlock(&vop->reg_lock); 538 539 vop_cfg_done(vop); 540 541 /* 542 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 543 */ 544 vop->is_enabled = true; 545 546 spin_lock(&vop->reg_lock); 547 548 VOP_REG_SET(vop, common, standby, 1); 549 550 spin_unlock(&vop->reg_lock); 551 552 enable_irq(vop->irq); 553 554 drm_crtc_vblank_on(crtc); 555 556 return 0; 557 558 err_disable_aclk: 559 clk_disable(vop->aclk); 560 err_disable_dclk: 561 clk_disable(vop->dclk); 562 err_disable_hclk: 563 clk_disable(vop->hclk); 564 err_put_pm_runtime: 565 pm_runtime_put_sync(vop->dev); 566 return ret; 567 } 568 569 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 570 struct drm_crtc_state *old_state) 571 { 572 struct vop *vop = to_vop(crtc); 573 574 WARN_ON(vop->event); 575 576 mutex_lock(&vop->vop_lock); 577 drm_crtc_vblank_off(crtc); 578 579 /* 580 * Vop standby will take effect at end of current frame, 581 * if dsp hold valid irq happen, it means standby complete. 582 * 583 * we must wait standby complete when we want to disable aclk, 584 * if not, memory bus maybe dead. 585 */ 586 reinit_completion(&vop->dsp_hold_completion); 587 vop_dsp_hold_valid_irq_enable(vop); 588 589 spin_lock(&vop->reg_lock); 590 591 VOP_REG_SET(vop, common, standby, 1); 592 593 spin_unlock(&vop->reg_lock); 594 595 wait_for_completion(&vop->dsp_hold_completion); 596 597 vop_dsp_hold_valid_irq_disable(vop); 598 599 disable_irq(vop->irq); 600 601 vop->is_enabled = false; 602 603 /* 604 * vop standby complete, so iommu detach is safe. 605 */ 606 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 607 608 clk_disable(vop->dclk); 609 clk_disable(vop->aclk); 610 clk_disable(vop->hclk); 611 pm_runtime_put(vop->dev); 612 mutex_unlock(&vop->vop_lock); 613 614 if (crtc->state->event && !crtc->state->active) { 615 spin_lock_irq(&crtc->dev->event_lock); 616 drm_crtc_send_vblank_event(crtc, crtc->state->event); 617 spin_unlock_irq(&crtc->dev->event_lock); 618 619 crtc->state->event = NULL; 620 } 621 } 622 623 static void vop_plane_destroy(struct drm_plane *plane) 624 { 625 drm_plane_cleanup(plane); 626 } 627 628 static int vop_plane_atomic_check(struct drm_plane *plane, 629 struct drm_plane_state *state) 630 { 631 struct drm_crtc *crtc = state->crtc; 632 struct drm_crtc_state *crtc_state; 633 struct drm_framebuffer *fb = state->fb; 634 struct vop_win *vop_win = to_vop_win(plane); 635 const struct vop_win_data *win = vop_win->data; 636 int ret; 637 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 638 DRM_PLANE_HELPER_NO_SCALING; 639 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 640 DRM_PLANE_HELPER_NO_SCALING; 641 642 if (!crtc || !fb) 643 return 0; 644 645 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 646 if (WARN_ON(!crtc_state)) 647 return -EINVAL; 648 649 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 650 min_scale, max_scale, 651 true, true); 652 if (ret) 653 return ret; 654 655 if (!state->visible) 656 return 0; 657 658 ret = vop_convert_format(fb->format->format); 659 if (ret < 0) 660 return ret; 661 662 /* 663 * Src.x1 can be odd when do clip, but yuv plane start point 664 * need align with 2 pixel. 665 */ 666 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) { 667 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 668 return -EINVAL; 669 } 670 671 return 0; 672 } 673 674 static void vop_plane_atomic_disable(struct drm_plane *plane, 675 struct drm_plane_state *old_state) 676 { 677 struct vop_win *vop_win = to_vop_win(plane); 678 const struct vop_win_data *win = vop_win->data; 679 struct vop *vop = to_vop(old_state->crtc); 680 681 if (!old_state->crtc) 682 return; 683 684 spin_lock(&vop->reg_lock); 685 686 VOP_WIN_SET(vop, win, enable, 0); 687 688 spin_unlock(&vop->reg_lock); 689 } 690 691 static void vop_plane_atomic_update(struct drm_plane *plane, 692 struct drm_plane_state *old_state) 693 { 694 struct drm_plane_state *state = plane->state; 695 struct drm_crtc *crtc = state->crtc; 696 struct vop_win *vop_win = to_vop_win(plane); 697 const struct vop_win_data *win = vop_win->data; 698 struct vop *vop = to_vop(state->crtc); 699 struct drm_framebuffer *fb = state->fb; 700 unsigned int actual_w, actual_h; 701 unsigned int dsp_stx, dsp_sty; 702 uint32_t act_info, dsp_info, dsp_st; 703 struct drm_rect *src = &state->src; 704 struct drm_rect *dest = &state->dst; 705 struct drm_gem_object *obj, *uv_obj; 706 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 707 unsigned long offset; 708 dma_addr_t dma_addr; 709 uint32_t val; 710 bool rb_swap; 711 int format; 712 713 /* 714 * can't update plane when vop is disabled. 715 */ 716 if (WARN_ON(!crtc)) 717 return; 718 719 if (WARN_ON(!vop->is_enabled)) 720 return; 721 722 if (!state->visible) { 723 vop_plane_atomic_disable(plane, old_state); 724 return; 725 } 726 727 obj = rockchip_fb_get_gem_obj(fb, 0); 728 rk_obj = to_rockchip_obj(obj); 729 730 actual_w = drm_rect_width(src) >> 16; 731 actual_h = drm_rect_height(src) >> 16; 732 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 733 734 dsp_info = (drm_rect_height(dest) - 1) << 16; 735 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 736 737 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 738 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 739 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 740 741 offset = (src->x1 >> 16) * fb->format->cpp[0]; 742 offset += (src->y1 >> 16) * fb->pitches[0]; 743 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 744 745 format = vop_convert_format(fb->format->format); 746 747 spin_lock(&vop->reg_lock); 748 749 VOP_WIN_SET(vop, win, format, format); 750 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 751 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 752 if (is_yuv_support(fb->format->format)) { 753 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 754 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 755 int bpp = fb->format->cpp[1]; 756 757 uv_obj = rockchip_fb_get_gem_obj(fb, 1); 758 rk_uv_obj = to_rockchip_obj(uv_obj); 759 760 offset = (src->x1 >> 16) * bpp / hsub; 761 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 762 763 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 764 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 765 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 766 } 767 768 if (win->phy->scl) 769 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 770 drm_rect_width(dest), drm_rect_height(dest), 771 fb->format->format); 772 773 VOP_WIN_SET(vop, win, act_info, act_info); 774 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 775 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 776 777 rb_swap = has_rb_swapped(fb->format->format); 778 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 779 780 if (fb->format->has_alpha) { 781 VOP_WIN_SET(vop, win, dst_alpha_ctl, 782 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 783 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 784 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 785 SRC_BLEND_M0(ALPHA_PER_PIX) | 786 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 787 SRC_FACTOR_M0(ALPHA_ONE); 788 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 789 } else { 790 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 791 } 792 793 VOP_WIN_SET(vop, win, enable, 1); 794 spin_unlock(&vop->reg_lock); 795 } 796 797 static const struct drm_plane_helper_funcs plane_helper_funcs = { 798 .atomic_check = vop_plane_atomic_check, 799 .atomic_update = vop_plane_atomic_update, 800 .atomic_disable = vop_plane_atomic_disable, 801 }; 802 803 static const struct drm_plane_funcs vop_plane_funcs = { 804 .update_plane = drm_atomic_helper_update_plane, 805 .disable_plane = drm_atomic_helper_disable_plane, 806 .destroy = vop_plane_destroy, 807 .reset = drm_atomic_helper_plane_reset, 808 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 809 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 810 }; 811 812 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 813 { 814 struct vop *vop = to_vop(crtc); 815 unsigned long flags; 816 817 if (WARN_ON(!vop->is_enabled)) 818 return -EPERM; 819 820 spin_lock_irqsave(&vop->irq_lock, flags); 821 822 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 823 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 824 825 spin_unlock_irqrestore(&vop->irq_lock, flags); 826 827 return 0; 828 } 829 830 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 831 { 832 struct vop *vop = to_vop(crtc); 833 unsigned long flags; 834 835 if (WARN_ON(!vop->is_enabled)) 836 return; 837 838 spin_lock_irqsave(&vop->irq_lock, flags); 839 840 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 841 842 spin_unlock_irqrestore(&vop->irq_lock, flags); 843 } 844 845 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 846 const struct drm_display_mode *mode, 847 struct drm_display_mode *adjusted_mode) 848 { 849 struct vop *vop = to_vop(crtc); 850 851 adjusted_mode->clock = 852 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 853 854 return true; 855 } 856 857 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 858 struct drm_crtc_state *old_state) 859 { 860 struct vop *vop = to_vop(crtc); 861 const struct vop_data *vop_data = vop->data; 862 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 863 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 864 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 865 u16 hdisplay = adjusted_mode->hdisplay; 866 u16 htotal = adjusted_mode->htotal; 867 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 868 u16 hact_end = hact_st + hdisplay; 869 u16 vdisplay = adjusted_mode->vdisplay; 870 u16 vtotal = adjusted_mode->vtotal; 871 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 872 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 873 u16 vact_end = vact_st + vdisplay; 874 uint32_t pin_pol, val; 875 int ret; 876 877 mutex_lock(&vop->vop_lock); 878 879 WARN_ON(vop->event); 880 881 ret = vop_enable(crtc); 882 if (ret) { 883 mutex_unlock(&vop->vop_lock); 884 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 885 return; 886 } 887 888 pin_pol = BIT(DCLK_INVERT); 889 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 890 BIT(HSYNC_POSITIVE) : 0; 891 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 892 BIT(VSYNC_POSITIVE) : 0; 893 VOP_REG_SET(vop, output, pin_pol, pin_pol); 894 895 switch (s->output_type) { 896 case DRM_MODE_CONNECTOR_LVDS: 897 VOP_REG_SET(vop, output, rgb_en, 1); 898 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 899 break; 900 case DRM_MODE_CONNECTOR_eDP: 901 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 902 VOP_REG_SET(vop, output, edp_en, 1); 903 break; 904 case DRM_MODE_CONNECTOR_HDMIA: 905 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 906 VOP_REG_SET(vop, output, hdmi_en, 1); 907 break; 908 case DRM_MODE_CONNECTOR_DSI: 909 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 910 VOP_REG_SET(vop, output, mipi_en, 1); 911 break; 912 case DRM_MODE_CONNECTOR_DisplayPort: 913 pin_pol &= ~BIT(DCLK_INVERT); 914 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 915 VOP_REG_SET(vop, output, dp_en, 1); 916 break; 917 default: 918 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 919 s->output_type); 920 } 921 922 /* 923 * if vop is not support RGB10 output, need force RGB10 to RGB888. 924 */ 925 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 926 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 927 s->output_mode = ROCKCHIP_OUT_MODE_P888; 928 VOP_REG_SET(vop, common, out_mode, s->output_mode); 929 930 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 931 val = hact_st << 16; 932 val |= hact_end; 933 VOP_REG_SET(vop, modeset, hact_st_end, val); 934 VOP_REG_SET(vop, modeset, hpost_st_end, val); 935 936 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 937 val = vact_st << 16; 938 val |= vact_end; 939 VOP_REG_SET(vop, modeset, vact_st_end, val); 940 VOP_REG_SET(vop, modeset, vpost_st_end, val); 941 942 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 943 944 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 945 946 VOP_REG_SET(vop, common, standby, 0); 947 mutex_unlock(&vop->vop_lock); 948 } 949 950 static bool vop_fs_irq_is_pending(struct vop *vop) 951 { 952 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 953 } 954 955 static void vop_wait_for_irq_handler(struct vop *vop) 956 { 957 bool pending; 958 int ret; 959 960 /* 961 * Spin until frame start interrupt status bit goes low, which means 962 * that interrupt handler was invoked and cleared it. The timeout of 963 * 10 msecs is really too long, but it is just a safety measure if 964 * something goes really wrong. The wait will only happen in the very 965 * unlikely case of a vblank happening exactly at the same time and 966 * shouldn't exceed microseconds range. 967 */ 968 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 969 !pending, 0, 10 * 1000); 970 if (ret) 971 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 972 973 synchronize_irq(vop->irq); 974 } 975 976 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 977 struct drm_crtc_state *old_crtc_state) 978 { 979 struct drm_atomic_state *old_state = old_crtc_state->state; 980 struct drm_plane_state *old_plane_state, *new_plane_state; 981 struct vop *vop = to_vop(crtc); 982 struct drm_plane *plane; 983 int i; 984 985 if (WARN_ON(!vop->is_enabled)) 986 return; 987 988 spin_lock(&vop->reg_lock); 989 990 vop_cfg_done(vop); 991 992 spin_unlock(&vop->reg_lock); 993 994 /* 995 * There is a (rather unlikely) possiblity that a vblank interrupt 996 * fired before we set the cfg_done bit. To avoid spuriously 997 * signalling flip completion we need to wait for it to finish. 998 */ 999 vop_wait_for_irq_handler(vop); 1000 1001 spin_lock_irq(&crtc->dev->event_lock); 1002 if (crtc->state->event) { 1003 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1004 WARN_ON(vop->event); 1005 1006 vop->event = crtc->state->event; 1007 crtc->state->event = NULL; 1008 } 1009 spin_unlock_irq(&crtc->dev->event_lock); 1010 1011 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1012 new_plane_state, i) { 1013 if (!old_plane_state->fb) 1014 continue; 1015 1016 if (old_plane_state->fb == new_plane_state->fb) 1017 continue; 1018 1019 drm_framebuffer_get(old_plane_state->fb); 1020 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1021 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1022 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1023 } 1024 } 1025 1026 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1027 struct drm_crtc_state *old_crtc_state) 1028 { 1029 rockchip_drm_psr_flush(crtc); 1030 } 1031 1032 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1033 .mode_fixup = vop_crtc_mode_fixup, 1034 .atomic_flush = vop_crtc_atomic_flush, 1035 .atomic_begin = vop_crtc_atomic_begin, 1036 .atomic_enable = vop_crtc_atomic_enable, 1037 .atomic_disable = vop_crtc_atomic_disable, 1038 }; 1039 1040 static void vop_crtc_destroy(struct drm_crtc *crtc) 1041 { 1042 drm_crtc_cleanup(crtc); 1043 } 1044 1045 static void vop_crtc_reset(struct drm_crtc *crtc) 1046 { 1047 if (crtc->state) 1048 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1049 kfree(crtc->state); 1050 1051 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1052 if (crtc->state) 1053 crtc->state->crtc = crtc; 1054 } 1055 1056 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1057 { 1058 struct rockchip_crtc_state *rockchip_state; 1059 1060 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1061 if (!rockchip_state) 1062 return NULL; 1063 1064 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1065 return &rockchip_state->base; 1066 } 1067 1068 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1069 struct drm_crtc_state *state) 1070 { 1071 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1072 1073 __drm_atomic_helper_crtc_destroy_state(&s->base); 1074 kfree(s); 1075 } 1076 1077 #ifdef CONFIG_DRM_ANALOGIX_DP 1078 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1079 { 1080 struct drm_connector *connector; 1081 struct drm_connector_list_iter conn_iter; 1082 1083 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1084 drm_for_each_connector_iter(connector, &conn_iter) { 1085 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1086 drm_connector_list_iter_end(&conn_iter); 1087 return connector; 1088 } 1089 } 1090 drm_connector_list_iter_end(&conn_iter); 1091 1092 return NULL; 1093 } 1094 1095 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1096 const char *source_name, size_t *values_cnt) 1097 { 1098 struct vop *vop = to_vop(crtc); 1099 struct drm_connector *connector; 1100 int ret; 1101 1102 connector = vop_get_edp_connector(vop); 1103 if (!connector) 1104 return -EINVAL; 1105 1106 *values_cnt = 3; 1107 1108 if (source_name && strcmp(source_name, "auto") == 0) 1109 ret = analogix_dp_start_crc(connector); 1110 else if (!source_name) 1111 ret = analogix_dp_stop_crc(connector); 1112 else 1113 ret = -EINVAL; 1114 1115 return ret; 1116 } 1117 #else 1118 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1119 const char *source_name, size_t *values_cnt) 1120 { 1121 return -ENODEV; 1122 } 1123 #endif 1124 1125 static const struct drm_crtc_funcs vop_crtc_funcs = { 1126 .set_config = drm_atomic_helper_set_config, 1127 .page_flip = drm_atomic_helper_page_flip, 1128 .destroy = vop_crtc_destroy, 1129 .reset = vop_crtc_reset, 1130 .atomic_duplicate_state = vop_crtc_duplicate_state, 1131 .atomic_destroy_state = vop_crtc_destroy_state, 1132 .enable_vblank = vop_crtc_enable_vblank, 1133 .disable_vblank = vop_crtc_disable_vblank, 1134 .set_crc_source = vop_crtc_set_crc_source, 1135 }; 1136 1137 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1138 { 1139 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1140 struct drm_framebuffer *fb = val; 1141 1142 drm_crtc_vblank_put(&vop->crtc); 1143 drm_framebuffer_put(fb); 1144 } 1145 1146 static void vop_handle_vblank(struct vop *vop) 1147 { 1148 struct drm_device *drm = vop->drm_dev; 1149 struct drm_crtc *crtc = &vop->crtc; 1150 1151 spin_lock(&drm->event_lock); 1152 if (vop->event) { 1153 drm_crtc_send_vblank_event(crtc, vop->event); 1154 drm_crtc_vblank_put(crtc); 1155 vop->event = NULL; 1156 } 1157 spin_unlock(&drm->event_lock); 1158 1159 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1160 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1161 } 1162 1163 static irqreturn_t vop_isr(int irq, void *data) 1164 { 1165 struct vop *vop = data; 1166 struct drm_crtc *crtc = &vop->crtc; 1167 uint32_t active_irqs; 1168 int ret = IRQ_NONE; 1169 1170 /* 1171 * interrupt register has interrupt status, enable and clear bits, we 1172 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1173 */ 1174 spin_lock(&vop->irq_lock); 1175 1176 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1177 /* Clear all active interrupt sources */ 1178 if (active_irqs) 1179 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1180 1181 spin_unlock(&vop->irq_lock); 1182 1183 /* This is expected for vop iommu irqs, since the irq is shared */ 1184 if (!active_irqs) 1185 return IRQ_NONE; 1186 1187 if (active_irqs & DSP_HOLD_VALID_INTR) { 1188 complete(&vop->dsp_hold_completion); 1189 active_irqs &= ~DSP_HOLD_VALID_INTR; 1190 ret = IRQ_HANDLED; 1191 } 1192 1193 if (active_irqs & LINE_FLAG_INTR) { 1194 complete(&vop->line_flag_completion); 1195 active_irqs &= ~LINE_FLAG_INTR; 1196 ret = IRQ_HANDLED; 1197 } 1198 1199 if (active_irqs & FS_INTR) { 1200 drm_crtc_handle_vblank(crtc); 1201 vop_handle_vblank(vop); 1202 active_irqs &= ~FS_INTR; 1203 ret = IRQ_HANDLED; 1204 } 1205 1206 /* Unhandled irqs are spurious. */ 1207 if (active_irqs) 1208 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1209 active_irqs); 1210 1211 return ret; 1212 } 1213 1214 static int vop_create_crtc(struct vop *vop) 1215 { 1216 const struct vop_data *vop_data = vop->data; 1217 struct device *dev = vop->dev; 1218 struct drm_device *drm_dev = vop->drm_dev; 1219 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1220 struct drm_crtc *crtc = &vop->crtc; 1221 struct device_node *port; 1222 int ret; 1223 int i; 1224 1225 /* 1226 * Create drm_plane for primary and cursor planes first, since we need 1227 * to pass them to drm_crtc_init_with_planes, which sets the 1228 * "possible_crtcs" to the newly initialized crtc. 1229 */ 1230 for (i = 0; i < vop_data->win_size; i++) { 1231 struct vop_win *vop_win = &vop->win[i]; 1232 const struct vop_win_data *win_data = vop_win->data; 1233 1234 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1235 win_data->type != DRM_PLANE_TYPE_CURSOR) 1236 continue; 1237 1238 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1239 0, &vop_plane_funcs, 1240 win_data->phy->data_formats, 1241 win_data->phy->nformats, 1242 NULL, win_data->type, NULL); 1243 if (ret) { 1244 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1245 ret); 1246 goto err_cleanup_planes; 1247 } 1248 1249 plane = &vop_win->base; 1250 drm_plane_helper_add(plane, &plane_helper_funcs); 1251 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1252 primary = plane; 1253 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1254 cursor = plane; 1255 } 1256 1257 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1258 &vop_crtc_funcs, NULL); 1259 if (ret) 1260 goto err_cleanup_planes; 1261 1262 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1263 1264 /* 1265 * Create drm_planes for overlay windows with possible_crtcs restricted 1266 * to the newly created crtc. 1267 */ 1268 for (i = 0; i < vop_data->win_size; i++) { 1269 struct vop_win *vop_win = &vop->win[i]; 1270 const struct vop_win_data *win_data = vop_win->data; 1271 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1272 1273 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1274 continue; 1275 1276 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1277 possible_crtcs, 1278 &vop_plane_funcs, 1279 win_data->phy->data_formats, 1280 win_data->phy->nformats, 1281 NULL, win_data->type, NULL); 1282 if (ret) { 1283 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1284 ret); 1285 goto err_cleanup_crtc; 1286 } 1287 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1288 } 1289 1290 port = of_get_child_by_name(dev->of_node, "port"); 1291 if (!port) { 1292 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1293 dev->of_node); 1294 ret = -ENOENT; 1295 goto err_cleanup_crtc; 1296 } 1297 1298 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1299 vop_fb_unref_worker); 1300 1301 init_completion(&vop->dsp_hold_completion); 1302 init_completion(&vop->line_flag_completion); 1303 crtc->port = port; 1304 1305 return 0; 1306 1307 err_cleanup_crtc: 1308 drm_crtc_cleanup(crtc); 1309 err_cleanup_planes: 1310 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1311 head) 1312 drm_plane_cleanup(plane); 1313 return ret; 1314 } 1315 1316 static void vop_destroy_crtc(struct vop *vop) 1317 { 1318 struct drm_crtc *crtc = &vop->crtc; 1319 struct drm_device *drm_dev = vop->drm_dev; 1320 struct drm_plane *plane, *tmp; 1321 1322 of_node_put(crtc->port); 1323 1324 /* 1325 * We need to cleanup the planes now. Why? 1326 * 1327 * The planes are "&vop->win[i].base". That means the memory is 1328 * all part of the big "struct vop" chunk of memory. That memory 1329 * was devm allocated and associated with this component. We need to 1330 * free it ourselves before vop_unbind() finishes. 1331 */ 1332 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1333 head) 1334 vop_plane_destroy(plane); 1335 1336 /* 1337 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1338 * references the CRTC. 1339 */ 1340 drm_crtc_cleanup(crtc); 1341 drm_flip_work_cleanup(&vop->fb_unref_work); 1342 } 1343 1344 static int vop_initial(struct vop *vop) 1345 { 1346 const struct vop_data *vop_data = vop->data; 1347 struct reset_control *ahb_rst; 1348 int i, ret; 1349 1350 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1351 if (IS_ERR(vop->hclk)) { 1352 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1353 return PTR_ERR(vop->hclk); 1354 } 1355 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1356 if (IS_ERR(vop->aclk)) { 1357 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1358 return PTR_ERR(vop->aclk); 1359 } 1360 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1361 if (IS_ERR(vop->dclk)) { 1362 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1363 return PTR_ERR(vop->dclk); 1364 } 1365 1366 ret = pm_runtime_get_sync(vop->dev); 1367 if (ret < 0) { 1368 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1369 return ret; 1370 } 1371 1372 ret = clk_prepare(vop->dclk); 1373 if (ret < 0) { 1374 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1375 goto err_put_pm_runtime; 1376 } 1377 1378 /* Enable both the hclk and aclk to setup the vop */ 1379 ret = clk_prepare_enable(vop->hclk); 1380 if (ret < 0) { 1381 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1382 goto err_unprepare_dclk; 1383 } 1384 1385 ret = clk_prepare_enable(vop->aclk); 1386 if (ret < 0) { 1387 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1388 goto err_disable_hclk; 1389 } 1390 1391 /* 1392 * do hclk_reset, reset all vop registers. 1393 */ 1394 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1395 if (IS_ERR(ahb_rst)) { 1396 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1397 ret = PTR_ERR(ahb_rst); 1398 goto err_disable_aclk; 1399 } 1400 reset_control_assert(ahb_rst); 1401 usleep_range(10, 20); 1402 reset_control_deassert(ahb_rst); 1403 1404 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1405 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1406 1407 for (i = 0; i < vop->len; i += sizeof(u32)) 1408 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1409 1410 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1411 VOP_REG_SET(vop, common, dsp_blank, 0); 1412 1413 for (i = 0; i < vop_data->win_size; i++) { 1414 const struct vop_win_data *win = &vop_data->win[i]; 1415 int channel = i * 2 + 1; 1416 1417 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1418 VOP_WIN_SET(vop, win, enable, 0); 1419 VOP_WIN_SET(vop, win, gate, 1); 1420 } 1421 1422 vop_cfg_done(vop); 1423 1424 /* 1425 * do dclk_reset, let all config take affect. 1426 */ 1427 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1428 if (IS_ERR(vop->dclk_rst)) { 1429 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1430 ret = PTR_ERR(vop->dclk_rst); 1431 goto err_disable_aclk; 1432 } 1433 reset_control_assert(vop->dclk_rst); 1434 usleep_range(10, 20); 1435 reset_control_deassert(vop->dclk_rst); 1436 1437 clk_disable(vop->hclk); 1438 clk_disable(vop->aclk); 1439 1440 vop->is_enabled = false; 1441 1442 pm_runtime_put_sync(vop->dev); 1443 1444 return 0; 1445 1446 err_disable_aclk: 1447 clk_disable_unprepare(vop->aclk); 1448 err_disable_hclk: 1449 clk_disable_unprepare(vop->hclk); 1450 err_unprepare_dclk: 1451 clk_unprepare(vop->dclk); 1452 err_put_pm_runtime: 1453 pm_runtime_put_sync(vop->dev); 1454 return ret; 1455 } 1456 1457 /* 1458 * Initialize the vop->win array elements. 1459 */ 1460 static void vop_win_init(struct vop *vop) 1461 { 1462 const struct vop_data *vop_data = vop->data; 1463 unsigned int i; 1464 1465 for (i = 0; i < vop_data->win_size; i++) { 1466 struct vop_win *vop_win = &vop->win[i]; 1467 const struct vop_win_data *win_data = &vop_data->win[i]; 1468 1469 vop_win->data = win_data; 1470 vop_win->vop = vop; 1471 } 1472 } 1473 1474 /** 1475 * rockchip_drm_wait_vact_end 1476 * @crtc: CRTC to enable line flag 1477 * @mstimeout: millisecond for timeout 1478 * 1479 * Wait for vact_end line flag irq or timeout. 1480 * 1481 * Returns: 1482 * Zero on success, negative errno on failure. 1483 */ 1484 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1485 { 1486 struct vop *vop = to_vop(crtc); 1487 unsigned long jiffies_left; 1488 int ret = 0; 1489 1490 if (!crtc || !vop->is_enabled) 1491 return -ENODEV; 1492 1493 mutex_lock(&vop->vop_lock); 1494 if (mstimeout <= 0) { 1495 ret = -EINVAL; 1496 goto out; 1497 } 1498 1499 if (vop_line_flag_irq_is_enabled(vop)) { 1500 ret = -EBUSY; 1501 goto out; 1502 } 1503 1504 reinit_completion(&vop->line_flag_completion); 1505 vop_line_flag_irq_enable(vop); 1506 1507 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1508 msecs_to_jiffies(mstimeout)); 1509 vop_line_flag_irq_disable(vop); 1510 1511 if (jiffies_left == 0) { 1512 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1513 ret = -ETIMEDOUT; 1514 goto out; 1515 } 1516 1517 out: 1518 mutex_unlock(&vop->vop_lock); 1519 return ret; 1520 } 1521 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1522 1523 static int vop_bind(struct device *dev, struct device *master, void *data) 1524 { 1525 struct platform_device *pdev = to_platform_device(dev); 1526 const struct vop_data *vop_data; 1527 struct drm_device *drm_dev = data; 1528 struct vop *vop; 1529 struct resource *res; 1530 size_t alloc_size; 1531 int ret, irq; 1532 1533 vop_data = of_device_get_match_data(dev); 1534 if (!vop_data) 1535 return -ENODEV; 1536 1537 /* Allocate vop struct and its vop_win array */ 1538 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1539 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1540 if (!vop) 1541 return -ENOMEM; 1542 1543 vop->dev = dev; 1544 vop->data = vop_data; 1545 vop->drm_dev = drm_dev; 1546 dev_set_drvdata(dev, vop); 1547 1548 vop_win_init(vop); 1549 1550 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1551 vop->len = resource_size(res); 1552 vop->regs = devm_ioremap_resource(dev, res); 1553 if (IS_ERR(vop->regs)) 1554 return PTR_ERR(vop->regs); 1555 1556 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1557 if (!vop->regsbak) 1558 return -ENOMEM; 1559 1560 irq = platform_get_irq(pdev, 0); 1561 if (irq < 0) { 1562 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1563 return irq; 1564 } 1565 vop->irq = (unsigned int)irq; 1566 1567 spin_lock_init(&vop->reg_lock); 1568 spin_lock_init(&vop->irq_lock); 1569 mutex_init(&vop->vop_lock); 1570 1571 ret = vop_create_crtc(vop); 1572 if (ret) 1573 return ret; 1574 1575 pm_runtime_enable(&pdev->dev); 1576 1577 ret = vop_initial(vop); 1578 if (ret < 0) { 1579 DRM_DEV_ERROR(&pdev->dev, 1580 "cannot initial vop dev - err %d\n", ret); 1581 goto err_disable_pm_runtime; 1582 } 1583 1584 ret = devm_request_irq(dev, vop->irq, vop_isr, 1585 IRQF_SHARED, dev_name(dev), vop); 1586 if (ret) 1587 goto err_disable_pm_runtime; 1588 1589 /* IRQ is initially disabled; it gets enabled in power_on */ 1590 disable_irq(vop->irq); 1591 1592 return 0; 1593 1594 err_disable_pm_runtime: 1595 pm_runtime_disable(&pdev->dev); 1596 vop_destroy_crtc(vop); 1597 return ret; 1598 } 1599 1600 static void vop_unbind(struct device *dev, struct device *master, void *data) 1601 { 1602 struct vop *vop = dev_get_drvdata(dev); 1603 1604 pm_runtime_disable(dev); 1605 vop_destroy_crtc(vop); 1606 1607 clk_unprepare(vop->aclk); 1608 clk_unprepare(vop->hclk); 1609 clk_unprepare(vop->dclk); 1610 } 1611 1612 const struct component_ops vop_component_ops = { 1613 .bind = vop_bind, 1614 .unbind = vop_unbind, 1615 }; 1616 EXPORT_SYMBOL_GPL(vop_component_ops); 1617