1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author:Mark Yao <mark.yao@rock-chips.com> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <drm/drm.h> 16 #include <drm/drmP.h> 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_flip_work.h> 21 #include <drm/drm_plane_helper.h> 22 #ifdef CONFIG_DRM_ANALOGIX_DP 23 #include <drm/bridge/analogix_dp.h> 24 #endif 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/iopoll.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/component.h> 35 36 #include <linux/reset.h> 37 #include <linux/delay.h> 38 39 #include "rockchip_drm_drv.h" 40 #include "rockchip_drm_gem.h" 41 #include "rockchip_drm_fb.h" 42 #include "rockchip_drm_psr.h" 43 #include "rockchip_drm_vop.h" 44 45 #define VOP_WIN_SET(x, win, name, v) \ 46 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET(x, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 49 #define VOP_SCL_SET_EXT(x, win, name, v) \ 50 vop_reg_set(vop, &win->phy->scl->ext->name, \ 51 win->base, ~0, v, #name) 52 53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 54 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 55 56 #define VOP_REG_SET(vop, group, name, v) \ 57 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 58 59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 60 do { \ 61 int i, reg = 0, mask = 0; \ 62 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 63 if (vop->data->intr->intrs[i] & type) { \ 64 reg |= (v) << i; \ 65 mask |= 1 << i; \ 66 } \ 67 } \ 68 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 69 } while (0) 70 #define VOP_INTR_GET_TYPE(vop, name, type) \ 71 vop_get_intr_type(vop, &vop->data->intr->name, type) 72 73 #define VOP_WIN_GET(x, win, name) \ 74 vop_read_reg(x, win->offset, win->phy->name) 75 76 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 77 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 78 79 #define VOP_WIN_TO_INDEX(vop_win) \ 80 ((vop_win) - (vop_win)->vop->win) 81 82 #define to_vop(x) container_of(x, struct vop, crtc) 83 #define to_vop_win(x) container_of(x, struct vop_win, base) 84 85 enum vop_pending { 86 VOP_PENDING_FB_UNREF, 87 }; 88 89 struct vop_win { 90 struct drm_plane base; 91 const struct vop_win_data *data; 92 struct vop *vop; 93 }; 94 95 struct vop { 96 struct drm_crtc crtc; 97 struct device *dev; 98 struct drm_device *drm_dev; 99 bool is_enabled; 100 101 struct completion dsp_hold_completion; 102 103 /* protected by dev->event_lock */ 104 struct drm_pending_vblank_event *event; 105 106 struct drm_flip_work fb_unref_work; 107 unsigned long pending; 108 109 struct completion line_flag_completion; 110 111 const struct vop_data *data; 112 113 uint32_t *regsbak; 114 void __iomem *regs; 115 116 /* physical map length of vop register */ 117 uint32_t len; 118 119 /* one time only one process allowed to config the register */ 120 spinlock_t reg_lock; 121 /* lock vop irq reg */ 122 spinlock_t irq_lock; 123 /* protects crtc enable/disable */ 124 struct mutex vop_lock; 125 126 unsigned int irq; 127 128 /* vop AHP clk */ 129 struct clk *hclk; 130 /* vop dclk */ 131 struct clk *dclk; 132 /* vop share memory frequency */ 133 struct clk *aclk; 134 135 /* vop dclk reset */ 136 struct reset_control *dclk_rst; 137 138 struct vop_win win[]; 139 }; 140 141 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 142 { 143 writel(v, vop->regs + offset); 144 vop->regsbak[offset >> 2] = v; 145 } 146 147 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 148 { 149 return readl(vop->regs + offset); 150 } 151 152 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 153 const struct vop_reg *reg) 154 { 155 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 156 } 157 158 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 159 uint32_t _offset, uint32_t _mask, uint32_t v, 160 const char *reg_name) 161 { 162 int offset, mask, shift; 163 164 if (!reg || !reg->mask) { 165 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 166 return; 167 } 168 169 offset = reg->offset + _offset; 170 mask = reg->mask & _mask; 171 shift = reg->shift; 172 173 if (reg->write_mask) { 174 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 175 } else { 176 uint32_t cached_val = vop->regsbak[offset >> 2]; 177 178 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 179 vop->regsbak[offset >> 2] = v; 180 } 181 182 if (reg->relaxed) 183 writel_relaxed(v, vop->regs + offset); 184 else 185 writel(v, vop->regs + offset); 186 } 187 188 static inline uint32_t vop_get_intr_type(struct vop *vop, 189 const struct vop_reg *reg, int type) 190 { 191 uint32_t i, ret = 0; 192 uint32_t regs = vop_read_reg(vop, 0, reg); 193 194 for (i = 0; i < vop->data->intr->nintrs; i++) { 195 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 196 ret |= vop->data->intr->intrs[i]; 197 } 198 199 return ret; 200 } 201 202 static inline void vop_cfg_done(struct vop *vop) 203 { 204 VOP_REG_SET(vop, common, cfg_done, 1); 205 } 206 207 static bool has_rb_swapped(uint32_t format) 208 { 209 switch (format) { 210 case DRM_FORMAT_XBGR8888: 211 case DRM_FORMAT_ABGR8888: 212 case DRM_FORMAT_BGR888: 213 case DRM_FORMAT_BGR565: 214 return true; 215 default: 216 return false; 217 } 218 } 219 220 static enum vop_data_format vop_convert_format(uint32_t format) 221 { 222 switch (format) { 223 case DRM_FORMAT_XRGB8888: 224 case DRM_FORMAT_ARGB8888: 225 case DRM_FORMAT_XBGR8888: 226 case DRM_FORMAT_ABGR8888: 227 return VOP_FMT_ARGB8888; 228 case DRM_FORMAT_RGB888: 229 case DRM_FORMAT_BGR888: 230 return VOP_FMT_RGB888; 231 case DRM_FORMAT_RGB565: 232 case DRM_FORMAT_BGR565: 233 return VOP_FMT_RGB565; 234 case DRM_FORMAT_NV12: 235 return VOP_FMT_YUV420SP; 236 case DRM_FORMAT_NV16: 237 return VOP_FMT_YUV422SP; 238 case DRM_FORMAT_NV24: 239 return VOP_FMT_YUV444SP; 240 default: 241 DRM_ERROR("unsupported format[%08x]\n", format); 242 return -EINVAL; 243 } 244 } 245 246 static bool is_yuv_support(uint32_t format) 247 { 248 switch (format) { 249 case DRM_FORMAT_NV12: 250 case DRM_FORMAT_NV16: 251 case DRM_FORMAT_NV24: 252 return true; 253 default: 254 return false; 255 } 256 } 257 258 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 259 uint32_t dst, bool is_horizontal, 260 int vsu_mode, int *vskiplines) 261 { 262 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 263 264 if (vskiplines) 265 *vskiplines = 0; 266 267 if (is_horizontal) { 268 if (mode == SCALE_UP) 269 val = GET_SCL_FT_BIC(src, dst); 270 else if (mode == SCALE_DOWN) 271 val = GET_SCL_FT_BILI_DN(src, dst); 272 } else { 273 if (mode == SCALE_UP) { 274 if (vsu_mode == SCALE_UP_BIL) 275 val = GET_SCL_FT_BILI_UP(src, dst); 276 else 277 val = GET_SCL_FT_BIC(src, dst); 278 } else if (mode == SCALE_DOWN) { 279 if (vskiplines) { 280 *vskiplines = scl_get_vskiplines(src, dst); 281 val = scl_get_bili_dn_vskip(src, dst, 282 *vskiplines); 283 } else { 284 val = GET_SCL_FT_BILI_DN(src, dst); 285 } 286 } 287 } 288 289 return val; 290 } 291 292 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 293 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 294 uint32_t dst_h, uint32_t pixel_format) 295 { 296 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 297 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 298 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 299 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 300 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 301 bool is_yuv = is_yuv_support(pixel_format); 302 uint16_t cbcr_src_w = src_w / hsub; 303 uint16_t cbcr_src_h = src_h / vsub; 304 uint16_t vsu_mode; 305 uint16_t lb_mode; 306 uint32_t val; 307 int vskiplines; 308 309 if (dst_w > 3840) { 310 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 311 return; 312 } 313 314 if (!win->phy->scl->ext) { 315 VOP_SCL_SET(vop, win, scale_yrgb_x, 316 scl_cal_scale2(src_w, dst_w)); 317 VOP_SCL_SET(vop, win, scale_yrgb_y, 318 scl_cal_scale2(src_h, dst_h)); 319 if (is_yuv) { 320 VOP_SCL_SET(vop, win, scale_cbcr_x, 321 scl_cal_scale2(cbcr_src_w, dst_w)); 322 VOP_SCL_SET(vop, win, scale_cbcr_y, 323 scl_cal_scale2(cbcr_src_h, dst_h)); 324 } 325 return; 326 } 327 328 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 329 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 330 331 if (is_yuv) { 332 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 333 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 334 if (cbcr_hor_scl_mode == SCALE_DOWN) 335 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 336 else 337 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 338 } else { 339 if (yrgb_hor_scl_mode == SCALE_DOWN) 340 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 341 else 342 lb_mode = scl_vop_cal_lb_mode(src_w, false); 343 } 344 345 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 346 if (lb_mode == LB_RGB_3840X2) { 347 if (yrgb_ver_scl_mode != SCALE_NONE) { 348 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 349 return; 350 } 351 if (cbcr_ver_scl_mode != SCALE_NONE) { 352 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 353 return; 354 } 355 vsu_mode = SCALE_UP_BIL; 356 } else if (lb_mode == LB_RGB_2560X4) { 357 vsu_mode = SCALE_UP_BIL; 358 } else { 359 vsu_mode = SCALE_UP_BIC; 360 } 361 362 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 363 true, 0, NULL); 364 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 365 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 366 false, vsu_mode, &vskiplines); 367 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 368 369 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 370 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 371 372 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 373 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 374 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 375 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 376 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 377 if (is_yuv) { 378 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 379 dst_w, true, 0, NULL); 380 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 381 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 382 dst_h, false, vsu_mode, &vskiplines); 383 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 384 385 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 386 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 387 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 388 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 389 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 390 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 391 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 392 } 393 } 394 395 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 396 { 397 unsigned long flags; 398 399 if (WARN_ON(!vop->is_enabled)) 400 return; 401 402 spin_lock_irqsave(&vop->irq_lock, flags); 403 404 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 405 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 406 407 spin_unlock_irqrestore(&vop->irq_lock, flags); 408 } 409 410 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 411 { 412 unsigned long flags; 413 414 if (WARN_ON(!vop->is_enabled)) 415 return; 416 417 spin_lock_irqsave(&vop->irq_lock, flags); 418 419 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 420 421 spin_unlock_irqrestore(&vop->irq_lock, flags); 422 } 423 424 /* 425 * (1) each frame starts at the start of the Vsync pulse which is signaled by 426 * the "FRAME_SYNC" interrupt. 427 * (2) the active data region of each frame ends at dsp_vact_end 428 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 429 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 430 * 431 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 432 * Interrupts 433 * LINE_FLAG -------------------------------+ 434 * FRAME_SYNC ----+ | 435 * | | 436 * v v 437 * | Vsync | Vbp | Vactive | Vfp | 438 * ^ ^ ^ ^ 439 * | | | | 440 * | | | | 441 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 442 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 443 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 444 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 445 */ 446 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 447 { 448 uint32_t line_flag_irq; 449 unsigned long flags; 450 451 spin_lock_irqsave(&vop->irq_lock, flags); 452 453 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 454 455 spin_unlock_irqrestore(&vop->irq_lock, flags); 456 457 return !!line_flag_irq; 458 } 459 460 static void vop_line_flag_irq_enable(struct vop *vop) 461 { 462 unsigned long flags; 463 464 if (WARN_ON(!vop->is_enabled)) 465 return; 466 467 spin_lock_irqsave(&vop->irq_lock, flags); 468 469 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 470 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 471 472 spin_unlock_irqrestore(&vop->irq_lock, flags); 473 } 474 475 static void vop_line_flag_irq_disable(struct vop *vop) 476 { 477 unsigned long flags; 478 479 if (WARN_ON(!vop->is_enabled)) 480 return; 481 482 spin_lock_irqsave(&vop->irq_lock, flags); 483 484 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 485 486 spin_unlock_irqrestore(&vop->irq_lock, flags); 487 } 488 489 static int vop_enable(struct drm_crtc *crtc) 490 { 491 struct vop *vop = to_vop(crtc); 492 int ret, i; 493 494 ret = pm_runtime_get_sync(vop->dev); 495 if (ret < 0) { 496 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 497 return ret; 498 } 499 500 ret = clk_enable(vop->hclk); 501 if (WARN_ON(ret < 0)) 502 goto err_put_pm_runtime; 503 504 ret = clk_enable(vop->dclk); 505 if (WARN_ON(ret < 0)) 506 goto err_disable_hclk; 507 508 ret = clk_enable(vop->aclk); 509 if (WARN_ON(ret < 0)) 510 goto err_disable_dclk; 511 512 /* 513 * Slave iommu shares power, irq and clock with vop. It was associated 514 * automatically with this master device via common driver code. 515 * Now that we have enabled the clock we attach it to the shared drm 516 * mapping. 517 */ 518 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 519 if (ret) { 520 DRM_DEV_ERROR(vop->dev, 521 "failed to attach dma mapping, %d\n", ret); 522 goto err_disable_aclk; 523 } 524 525 spin_lock(&vop->reg_lock); 526 for (i = 0; i < vop->len; i += 4) 527 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 528 529 /* 530 * We need to make sure that all windows are disabled before we 531 * enable the crtc. Otherwise we might try to scan from a destroyed 532 * buffer later. 533 */ 534 for (i = 0; i < vop->data->win_size; i++) { 535 struct vop_win *vop_win = &vop->win[i]; 536 const struct vop_win_data *win = vop_win->data; 537 538 VOP_WIN_SET(vop, win, enable, 0); 539 } 540 spin_unlock(&vop->reg_lock); 541 542 vop_cfg_done(vop); 543 544 /* 545 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 546 */ 547 vop->is_enabled = true; 548 549 spin_lock(&vop->reg_lock); 550 551 VOP_REG_SET(vop, common, standby, 1); 552 553 spin_unlock(&vop->reg_lock); 554 555 enable_irq(vop->irq); 556 557 drm_crtc_vblank_on(crtc); 558 559 return 0; 560 561 err_disable_aclk: 562 clk_disable(vop->aclk); 563 err_disable_dclk: 564 clk_disable(vop->dclk); 565 err_disable_hclk: 566 clk_disable(vop->hclk); 567 err_put_pm_runtime: 568 pm_runtime_put_sync(vop->dev); 569 return ret; 570 } 571 572 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 573 struct drm_crtc_state *old_state) 574 { 575 struct vop *vop = to_vop(crtc); 576 577 WARN_ON(vop->event); 578 579 mutex_lock(&vop->vop_lock); 580 drm_crtc_vblank_off(crtc); 581 582 /* 583 * Vop standby will take effect at end of current frame, 584 * if dsp hold valid irq happen, it means standby complete. 585 * 586 * we must wait standby complete when we want to disable aclk, 587 * if not, memory bus maybe dead. 588 */ 589 reinit_completion(&vop->dsp_hold_completion); 590 vop_dsp_hold_valid_irq_enable(vop); 591 592 spin_lock(&vop->reg_lock); 593 594 VOP_REG_SET(vop, common, standby, 1); 595 596 spin_unlock(&vop->reg_lock); 597 598 wait_for_completion(&vop->dsp_hold_completion); 599 600 vop_dsp_hold_valid_irq_disable(vop); 601 602 disable_irq(vop->irq); 603 604 vop->is_enabled = false; 605 606 /* 607 * vop standby complete, so iommu detach is safe. 608 */ 609 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 610 611 clk_disable(vop->dclk); 612 clk_disable(vop->aclk); 613 clk_disable(vop->hclk); 614 pm_runtime_put(vop->dev); 615 mutex_unlock(&vop->vop_lock); 616 617 if (crtc->state->event && !crtc->state->active) { 618 spin_lock_irq(&crtc->dev->event_lock); 619 drm_crtc_send_vblank_event(crtc, crtc->state->event); 620 spin_unlock_irq(&crtc->dev->event_lock); 621 622 crtc->state->event = NULL; 623 } 624 } 625 626 static void vop_plane_destroy(struct drm_plane *plane) 627 { 628 drm_plane_cleanup(plane); 629 } 630 631 static int vop_plane_atomic_check(struct drm_plane *plane, 632 struct drm_plane_state *state) 633 { 634 struct drm_crtc *crtc = state->crtc; 635 struct drm_crtc_state *crtc_state; 636 struct drm_framebuffer *fb = state->fb; 637 struct vop_win *vop_win = to_vop_win(plane); 638 const struct vop_win_data *win = vop_win->data; 639 int ret; 640 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 641 DRM_PLANE_HELPER_NO_SCALING; 642 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 643 DRM_PLANE_HELPER_NO_SCALING; 644 645 if (!crtc || !fb) 646 return 0; 647 648 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 649 if (WARN_ON(!crtc_state)) 650 return -EINVAL; 651 652 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 653 min_scale, max_scale, 654 true, true); 655 if (ret) 656 return ret; 657 658 if (!state->visible) 659 return 0; 660 661 ret = vop_convert_format(fb->format->format); 662 if (ret < 0) 663 return ret; 664 665 /* 666 * Src.x1 can be odd when do clip, but yuv plane start point 667 * need align with 2 pixel. 668 */ 669 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) { 670 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 671 return -EINVAL; 672 } 673 674 return 0; 675 } 676 677 static void vop_plane_atomic_disable(struct drm_plane *plane, 678 struct drm_plane_state *old_state) 679 { 680 struct vop_win *vop_win = to_vop_win(plane); 681 const struct vop_win_data *win = vop_win->data; 682 struct vop *vop = to_vop(old_state->crtc); 683 684 if (!old_state->crtc) 685 return; 686 687 spin_lock(&vop->reg_lock); 688 689 VOP_WIN_SET(vop, win, enable, 0); 690 691 spin_unlock(&vop->reg_lock); 692 } 693 694 static void vop_plane_atomic_update(struct drm_plane *plane, 695 struct drm_plane_state *old_state) 696 { 697 struct drm_plane_state *state = plane->state; 698 struct drm_crtc *crtc = state->crtc; 699 struct vop_win *vop_win = to_vop_win(plane); 700 const struct vop_win_data *win = vop_win->data; 701 struct vop *vop = to_vop(state->crtc); 702 struct drm_framebuffer *fb = state->fb; 703 unsigned int actual_w, actual_h; 704 unsigned int dsp_stx, dsp_sty; 705 uint32_t act_info, dsp_info, dsp_st; 706 struct drm_rect *src = &state->src; 707 struct drm_rect *dest = &state->dst; 708 struct drm_gem_object *obj, *uv_obj; 709 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 710 unsigned long offset; 711 dma_addr_t dma_addr; 712 uint32_t val; 713 bool rb_swap; 714 int win_index = VOP_WIN_TO_INDEX(vop_win); 715 int format; 716 717 /* 718 * can't update plane when vop is disabled. 719 */ 720 if (WARN_ON(!crtc)) 721 return; 722 723 if (WARN_ON(!vop->is_enabled)) 724 return; 725 726 if (!state->visible) { 727 vop_plane_atomic_disable(plane, old_state); 728 return; 729 } 730 731 obj = rockchip_fb_get_gem_obj(fb, 0); 732 rk_obj = to_rockchip_obj(obj); 733 734 actual_w = drm_rect_width(src) >> 16; 735 actual_h = drm_rect_height(src) >> 16; 736 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 737 738 dsp_info = (drm_rect_height(dest) - 1) << 16; 739 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 740 741 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 742 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 743 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 744 745 offset = (src->x1 >> 16) * fb->format->cpp[0]; 746 offset += (src->y1 >> 16) * fb->pitches[0]; 747 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 748 749 format = vop_convert_format(fb->format->format); 750 751 spin_lock(&vop->reg_lock); 752 753 VOP_WIN_SET(vop, win, format, format); 754 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 755 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 756 if (is_yuv_support(fb->format->format)) { 757 int hsub = drm_format_horz_chroma_subsampling(fb->format->format); 758 int vsub = drm_format_vert_chroma_subsampling(fb->format->format); 759 int bpp = fb->format->cpp[1]; 760 761 uv_obj = rockchip_fb_get_gem_obj(fb, 1); 762 rk_uv_obj = to_rockchip_obj(uv_obj); 763 764 offset = (src->x1 >> 16) * bpp / hsub; 765 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 766 767 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 768 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 769 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 770 } 771 772 if (win->phy->scl) 773 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 774 drm_rect_width(dest), drm_rect_height(dest), 775 fb->format->format); 776 777 VOP_WIN_SET(vop, win, act_info, act_info); 778 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 779 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 780 781 rb_swap = has_rb_swapped(fb->format->format); 782 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 783 784 /* 785 * Blending win0 with the background color doesn't seem to work 786 * correctly. We only get the background color, no matter the contents 787 * of the win0 framebuffer. However, blending pre-multiplied color 788 * with the default opaque black default background color is a no-op, 789 * so we can just disable blending to get the correct result. 790 */ 791 if (fb->format->has_alpha && win_index > 0) { 792 VOP_WIN_SET(vop, win, dst_alpha_ctl, 793 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 794 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 795 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 796 SRC_BLEND_M0(ALPHA_PER_PIX) | 797 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 798 SRC_FACTOR_M0(ALPHA_ONE); 799 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 800 } else { 801 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 802 } 803 804 VOP_WIN_SET(vop, win, enable, 1); 805 spin_unlock(&vop->reg_lock); 806 } 807 808 static const struct drm_plane_helper_funcs plane_helper_funcs = { 809 .atomic_check = vop_plane_atomic_check, 810 .atomic_update = vop_plane_atomic_update, 811 .atomic_disable = vop_plane_atomic_disable, 812 }; 813 814 static const struct drm_plane_funcs vop_plane_funcs = { 815 .update_plane = drm_atomic_helper_update_plane, 816 .disable_plane = drm_atomic_helper_disable_plane, 817 .destroy = vop_plane_destroy, 818 .reset = drm_atomic_helper_plane_reset, 819 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 820 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 821 }; 822 823 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 824 { 825 struct vop *vop = to_vop(crtc); 826 unsigned long flags; 827 828 if (WARN_ON(!vop->is_enabled)) 829 return -EPERM; 830 831 spin_lock_irqsave(&vop->irq_lock, flags); 832 833 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 834 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 835 836 spin_unlock_irqrestore(&vop->irq_lock, flags); 837 838 return 0; 839 } 840 841 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 842 { 843 struct vop *vop = to_vop(crtc); 844 unsigned long flags; 845 846 if (WARN_ON(!vop->is_enabled)) 847 return; 848 849 spin_lock_irqsave(&vop->irq_lock, flags); 850 851 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 852 853 spin_unlock_irqrestore(&vop->irq_lock, flags); 854 } 855 856 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 857 const struct drm_display_mode *mode, 858 struct drm_display_mode *adjusted_mode) 859 { 860 struct vop *vop = to_vop(crtc); 861 862 adjusted_mode->clock = 863 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000; 864 865 return true; 866 } 867 868 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 869 struct drm_crtc_state *old_state) 870 { 871 struct vop *vop = to_vop(crtc); 872 const struct vop_data *vop_data = vop->data; 873 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 874 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 875 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 876 u16 hdisplay = adjusted_mode->hdisplay; 877 u16 htotal = adjusted_mode->htotal; 878 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 879 u16 hact_end = hact_st + hdisplay; 880 u16 vdisplay = adjusted_mode->vdisplay; 881 u16 vtotal = adjusted_mode->vtotal; 882 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 883 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 884 u16 vact_end = vact_st + vdisplay; 885 uint32_t pin_pol, val; 886 int ret; 887 888 mutex_lock(&vop->vop_lock); 889 890 WARN_ON(vop->event); 891 892 ret = vop_enable(crtc); 893 if (ret) { 894 mutex_unlock(&vop->vop_lock); 895 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 896 return; 897 } 898 899 pin_pol = BIT(DCLK_INVERT); 900 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 901 BIT(HSYNC_POSITIVE) : 0; 902 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 903 BIT(VSYNC_POSITIVE) : 0; 904 VOP_REG_SET(vop, output, pin_pol, pin_pol); 905 906 switch (s->output_type) { 907 case DRM_MODE_CONNECTOR_LVDS: 908 VOP_REG_SET(vop, output, rgb_en, 1); 909 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 910 break; 911 case DRM_MODE_CONNECTOR_eDP: 912 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 913 VOP_REG_SET(vop, output, edp_en, 1); 914 break; 915 case DRM_MODE_CONNECTOR_HDMIA: 916 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 917 VOP_REG_SET(vop, output, hdmi_en, 1); 918 break; 919 case DRM_MODE_CONNECTOR_DSI: 920 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 921 VOP_REG_SET(vop, output, mipi_en, 1); 922 break; 923 case DRM_MODE_CONNECTOR_DisplayPort: 924 pin_pol &= ~BIT(DCLK_INVERT); 925 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 926 VOP_REG_SET(vop, output, dp_en, 1); 927 break; 928 default: 929 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 930 s->output_type); 931 } 932 933 /* 934 * if vop is not support RGB10 output, need force RGB10 to RGB888. 935 */ 936 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 937 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 938 s->output_mode = ROCKCHIP_OUT_MODE_P888; 939 940 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && s->output_bpc == 8) 941 VOP_REG_SET(vop, common, pre_dither_down, 1); 942 else 943 VOP_REG_SET(vop, common, pre_dither_down, 0); 944 945 VOP_REG_SET(vop, common, out_mode, s->output_mode); 946 947 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 948 val = hact_st << 16; 949 val |= hact_end; 950 VOP_REG_SET(vop, modeset, hact_st_end, val); 951 VOP_REG_SET(vop, modeset, hpost_st_end, val); 952 953 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 954 val = vact_st << 16; 955 val |= vact_end; 956 VOP_REG_SET(vop, modeset, vact_st_end, val); 957 VOP_REG_SET(vop, modeset, vpost_st_end, val); 958 959 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 960 961 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 962 963 VOP_REG_SET(vop, common, standby, 0); 964 mutex_unlock(&vop->vop_lock); 965 } 966 967 static bool vop_fs_irq_is_pending(struct vop *vop) 968 { 969 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 970 } 971 972 static void vop_wait_for_irq_handler(struct vop *vop) 973 { 974 bool pending; 975 int ret; 976 977 /* 978 * Spin until frame start interrupt status bit goes low, which means 979 * that interrupt handler was invoked and cleared it. The timeout of 980 * 10 msecs is really too long, but it is just a safety measure if 981 * something goes really wrong. The wait will only happen in the very 982 * unlikely case of a vblank happening exactly at the same time and 983 * shouldn't exceed microseconds range. 984 */ 985 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 986 !pending, 0, 10 * 1000); 987 if (ret) 988 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 989 990 synchronize_irq(vop->irq); 991 } 992 993 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 994 struct drm_crtc_state *old_crtc_state) 995 { 996 struct drm_atomic_state *old_state = old_crtc_state->state; 997 struct drm_plane_state *old_plane_state, *new_plane_state; 998 struct vop *vop = to_vop(crtc); 999 struct drm_plane *plane; 1000 int i; 1001 1002 if (WARN_ON(!vop->is_enabled)) 1003 return; 1004 1005 spin_lock(&vop->reg_lock); 1006 1007 vop_cfg_done(vop); 1008 1009 spin_unlock(&vop->reg_lock); 1010 1011 /* 1012 * There is a (rather unlikely) possiblity that a vblank interrupt 1013 * fired before we set the cfg_done bit. To avoid spuriously 1014 * signalling flip completion we need to wait for it to finish. 1015 */ 1016 vop_wait_for_irq_handler(vop); 1017 1018 spin_lock_irq(&crtc->dev->event_lock); 1019 if (crtc->state->event) { 1020 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1021 WARN_ON(vop->event); 1022 1023 vop->event = crtc->state->event; 1024 crtc->state->event = NULL; 1025 } 1026 spin_unlock_irq(&crtc->dev->event_lock); 1027 1028 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1029 new_plane_state, i) { 1030 if (!old_plane_state->fb) 1031 continue; 1032 1033 if (old_plane_state->fb == new_plane_state->fb) 1034 continue; 1035 1036 drm_framebuffer_get(old_plane_state->fb); 1037 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1038 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1039 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1040 } 1041 } 1042 1043 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1044 .mode_fixup = vop_crtc_mode_fixup, 1045 .atomic_flush = vop_crtc_atomic_flush, 1046 .atomic_enable = vop_crtc_atomic_enable, 1047 .atomic_disable = vop_crtc_atomic_disable, 1048 }; 1049 1050 static void vop_crtc_destroy(struct drm_crtc *crtc) 1051 { 1052 drm_crtc_cleanup(crtc); 1053 } 1054 1055 static void vop_crtc_reset(struct drm_crtc *crtc) 1056 { 1057 if (crtc->state) 1058 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1059 kfree(crtc->state); 1060 1061 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL); 1062 if (crtc->state) 1063 crtc->state->crtc = crtc; 1064 } 1065 1066 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1067 { 1068 struct rockchip_crtc_state *rockchip_state; 1069 1070 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1071 if (!rockchip_state) 1072 return NULL; 1073 1074 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1075 return &rockchip_state->base; 1076 } 1077 1078 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1079 struct drm_crtc_state *state) 1080 { 1081 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1082 1083 __drm_atomic_helper_crtc_destroy_state(&s->base); 1084 kfree(s); 1085 } 1086 1087 #ifdef CONFIG_DRM_ANALOGIX_DP 1088 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1089 { 1090 struct drm_connector *connector; 1091 struct drm_connector_list_iter conn_iter; 1092 1093 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1094 drm_for_each_connector_iter(connector, &conn_iter) { 1095 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1096 drm_connector_list_iter_end(&conn_iter); 1097 return connector; 1098 } 1099 } 1100 drm_connector_list_iter_end(&conn_iter); 1101 1102 return NULL; 1103 } 1104 1105 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1106 const char *source_name, size_t *values_cnt) 1107 { 1108 struct vop *vop = to_vop(crtc); 1109 struct drm_connector *connector; 1110 int ret; 1111 1112 connector = vop_get_edp_connector(vop); 1113 if (!connector) 1114 return -EINVAL; 1115 1116 *values_cnt = 3; 1117 1118 if (source_name && strcmp(source_name, "auto") == 0) 1119 ret = analogix_dp_start_crc(connector); 1120 else if (!source_name) 1121 ret = analogix_dp_stop_crc(connector); 1122 else 1123 ret = -EINVAL; 1124 1125 return ret; 1126 } 1127 #else 1128 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1129 const char *source_name, size_t *values_cnt) 1130 { 1131 return -ENODEV; 1132 } 1133 #endif 1134 1135 static const struct drm_crtc_funcs vop_crtc_funcs = { 1136 .set_config = drm_atomic_helper_set_config, 1137 .page_flip = drm_atomic_helper_page_flip, 1138 .destroy = vop_crtc_destroy, 1139 .reset = vop_crtc_reset, 1140 .atomic_duplicate_state = vop_crtc_duplicate_state, 1141 .atomic_destroy_state = vop_crtc_destroy_state, 1142 .enable_vblank = vop_crtc_enable_vblank, 1143 .disable_vblank = vop_crtc_disable_vblank, 1144 .set_crc_source = vop_crtc_set_crc_source, 1145 }; 1146 1147 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1148 { 1149 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1150 struct drm_framebuffer *fb = val; 1151 1152 drm_crtc_vblank_put(&vop->crtc); 1153 drm_framebuffer_put(fb); 1154 } 1155 1156 static void vop_handle_vblank(struct vop *vop) 1157 { 1158 struct drm_device *drm = vop->drm_dev; 1159 struct drm_crtc *crtc = &vop->crtc; 1160 1161 spin_lock(&drm->event_lock); 1162 if (vop->event) { 1163 drm_crtc_send_vblank_event(crtc, vop->event); 1164 drm_crtc_vblank_put(crtc); 1165 vop->event = NULL; 1166 } 1167 spin_unlock(&drm->event_lock); 1168 1169 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1170 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1171 } 1172 1173 static irqreturn_t vop_isr(int irq, void *data) 1174 { 1175 struct vop *vop = data; 1176 struct drm_crtc *crtc = &vop->crtc; 1177 uint32_t active_irqs; 1178 int ret = IRQ_NONE; 1179 1180 /* 1181 * interrupt register has interrupt status, enable and clear bits, we 1182 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1183 */ 1184 spin_lock(&vop->irq_lock); 1185 1186 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1187 /* Clear all active interrupt sources */ 1188 if (active_irqs) 1189 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1190 1191 spin_unlock(&vop->irq_lock); 1192 1193 /* This is expected for vop iommu irqs, since the irq is shared */ 1194 if (!active_irqs) 1195 return IRQ_NONE; 1196 1197 if (active_irqs & DSP_HOLD_VALID_INTR) { 1198 complete(&vop->dsp_hold_completion); 1199 active_irqs &= ~DSP_HOLD_VALID_INTR; 1200 ret = IRQ_HANDLED; 1201 } 1202 1203 if (active_irqs & LINE_FLAG_INTR) { 1204 complete(&vop->line_flag_completion); 1205 active_irqs &= ~LINE_FLAG_INTR; 1206 ret = IRQ_HANDLED; 1207 } 1208 1209 if (active_irqs & FS_INTR) { 1210 drm_crtc_handle_vblank(crtc); 1211 vop_handle_vblank(vop); 1212 active_irqs &= ~FS_INTR; 1213 ret = IRQ_HANDLED; 1214 } 1215 1216 /* Unhandled irqs are spurious. */ 1217 if (active_irqs) 1218 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1219 active_irqs); 1220 1221 return ret; 1222 } 1223 1224 static int vop_create_crtc(struct vop *vop) 1225 { 1226 const struct vop_data *vop_data = vop->data; 1227 struct device *dev = vop->dev; 1228 struct drm_device *drm_dev = vop->drm_dev; 1229 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1230 struct drm_crtc *crtc = &vop->crtc; 1231 struct device_node *port; 1232 int ret; 1233 int i; 1234 1235 /* 1236 * Create drm_plane for primary and cursor planes first, since we need 1237 * to pass them to drm_crtc_init_with_planes, which sets the 1238 * "possible_crtcs" to the newly initialized crtc. 1239 */ 1240 for (i = 0; i < vop_data->win_size; i++) { 1241 struct vop_win *vop_win = &vop->win[i]; 1242 const struct vop_win_data *win_data = vop_win->data; 1243 1244 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1245 win_data->type != DRM_PLANE_TYPE_CURSOR) 1246 continue; 1247 1248 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1249 0, &vop_plane_funcs, 1250 win_data->phy->data_formats, 1251 win_data->phy->nformats, 1252 NULL, win_data->type, NULL); 1253 if (ret) { 1254 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1255 ret); 1256 goto err_cleanup_planes; 1257 } 1258 1259 plane = &vop_win->base; 1260 drm_plane_helper_add(plane, &plane_helper_funcs); 1261 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1262 primary = plane; 1263 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1264 cursor = plane; 1265 } 1266 1267 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1268 &vop_crtc_funcs, NULL); 1269 if (ret) 1270 goto err_cleanup_planes; 1271 1272 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1273 1274 /* 1275 * Create drm_planes for overlay windows with possible_crtcs restricted 1276 * to the newly created crtc. 1277 */ 1278 for (i = 0; i < vop_data->win_size; i++) { 1279 struct vop_win *vop_win = &vop->win[i]; 1280 const struct vop_win_data *win_data = vop_win->data; 1281 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc); 1282 1283 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1284 continue; 1285 1286 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1287 possible_crtcs, 1288 &vop_plane_funcs, 1289 win_data->phy->data_formats, 1290 win_data->phy->nformats, 1291 NULL, win_data->type, NULL); 1292 if (ret) { 1293 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1294 ret); 1295 goto err_cleanup_crtc; 1296 } 1297 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1298 } 1299 1300 port = of_get_child_by_name(dev->of_node, "port"); 1301 if (!port) { 1302 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1303 dev->of_node); 1304 ret = -ENOENT; 1305 goto err_cleanup_crtc; 1306 } 1307 1308 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1309 vop_fb_unref_worker); 1310 1311 init_completion(&vop->dsp_hold_completion); 1312 init_completion(&vop->line_flag_completion); 1313 crtc->port = port; 1314 1315 return 0; 1316 1317 err_cleanup_crtc: 1318 drm_crtc_cleanup(crtc); 1319 err_cleanup_planes: 1320 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1321 head) 1322 drm_plane_cleanup(plane); 1323 return ret; 1324 } 1325 1326 static void vop_destroy_crtc(struct vop *vop) 1327 { 1328 struct drm_crtc *crtc = &vop->crtc; 1329 struct drm_device *drm_dev = vop->drm_dev; 1330 struct drm_plane *plane, *tmp; 1331 1332 of_node_put(crtc->port); 1333 1334 /* 1335 * We need to cleanup the planes now. Why? 1336 * 1337 * The planes are "&vop->win[i].base". That means the memory is 1338 * all part of the big "struct vop" chunk of memory. That memory 1339 * was devm allocated and associated with this component. We need to 1340 * free it ourselves before vop_unbind() finishes. 1341 */ 1342 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1343 head) 1344 vop_plane_destroy(plane); 1345 1346 /* 1347 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1348 * references the CRTC. 1349 */ 1350 drm_crtc_cleanup(crtc); 1351 drm_flip_work_cleanup(&vop->fb_unref_work); 1352 } 1353 1354 static int vop_initial(struct vop *vop) 1355 { 1356 const struct vop_data *vop_data = vop->data; 1357 struct reset_control *ahb_rst; 1358 int i, ret; 1359 1360 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1361 if (IS_ERR(vop->hclk)) { 1362 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1363 return PTR_ERR(vop->hclk); 1364 } 1365 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1366 if (IS_ERR(vop->aclk)) { 1367 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1368 return PTR_ERR(vop->aclk); 1369 } 1370 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1371 if (IS_ERR(vop->dclk)) { 1372 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1373 return PTR_ERR(vop->dclk); 1374 } 1375 1376 ret = pm_runtime_get_sync(vop->dev); 1377 if (ret < 0) { 1378 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1379 return ret; 1380 } 1381 1382 ret = clk_prepare(vop->dclk); 1383 if (ret < 0) { 1384 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1385 goto err_put_pm_runtime; 1386 } 1387 1388 /* Enable both the hclk and aclk to setup the vop */ 1389 ret = clk_prepare_enable(vop->hclk); 1390 if (ret < 0) { 1391 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1392 goto err_unprepare_dclk; 1393 } 1394 1395 ret = clk_prepare_enable(vop->aclk); 1396 if (ret < 0) { 1397 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1398 goto err_disable_hclk; 1399 } 1400 1401 /* 1402 * do hclk_reset, reset all vop registers. 1403 */ 1404 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1405 if (IS_ERR(ahb_rst)) { 1406 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1407 ret = PTR_ERR(ahb_rst); 1408 goto err_disable_aclk; 1409 } 1410 reset_control_assert(ahb_rst); 1411 usleep_range(10, 20); 1412 reset_control_deassert(ahb_rst); 1413 1414 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1415 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1416 1417 for (i = 0; i < vop->len; i += sizeof(u32)) 1418 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1419 1420 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1421 VOP_REG_SET(vop, common, dsp_blank, 0); 1422 1423 for (i = 0; i < vop_data->win_size; i++) { 1424 const struct vop_win_data *win = &vop_data->win[i]; 1425 int channel = i * 2 + 1; 1426 1427 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1428 VOP_WIN_SET(vop, win, enable, 0); 1429 VOP_WIN_SET(vop, win, gate, 1); 1430 } 1431 1432 vop_cfg_done(vop); 1433 1434 /* 1435 * do dclk_reset, let all config take affect. 1436 */ 1437 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1438 if (IS_ERR(vop->dclk_rst)) { 1439 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1440 ret = PTR_ERR(vop->dclk_rst); 1441 goto err_disable_aclk; 1442 } 1443 reset_control_assert(vop->dclk_rst); 1444 usleep_range(10, 20); 1445 reset_control_deassert(vop->dclk_rst); 1446 1447 clk_disable(vop->hclk); 1448 clk_disable(vop->aclk); 1449 1450 vop->is_enabled = false; 1451 1452 pm_runtime_put_sync(vop->dev); 1453 1454 return 0; 1455 1456 err_disable_aclk: 1457 clk_disable_unprepare(vop->aclk); 1458 err_disable_hclk: 1459 clk_disable_unprepare(vop->hclk); 1460 err_unprepare_dclk: 1461 clk_unprepare(vop->dclk); 1462 err_put_pm_runtime: 1463 pm_runtime_put_sync(vop->dev); 1464 return ret; 1465 } 1466 1467 /* 1468 * Initialize the vop->win array elements. 1469 */ 1470 static void vop_win_init(struct vop *vop) 1471 { 1472 const struct vop_data *vop_data = vop->data; 1473 unsigned int i; 1474 1475 for (i = 0; i < vop_data->win_size; i++) { 1476 struct vop_win *vop_win = &vop->win[i]; 1477 const struct vop_win_data *win_data = &vop_data->win[i]; 1478 1479 vop_win->data = win_data; 1480 vop_win->vop = vop; 1481 } 1482 } 1483 1484 /** 1485 * rockchip_drm_wait_vact_end 1486 * @crtc: CRTC to enable line flag 1487 * @mstimeout: millisecond for timeout 1488 * 1489 * Wait for vact_end line flag irq or timeout. 1490 * 1491 * Returns: 1492 * Zero on success, negative errno on failure. 1493 */ 1494 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1495 { 1496 struct vop *vop = to_vop(crtc); 1497 unsigned long jiffies_left; 1498 int ret = 0; 1499 1500 if (!crtc || !vop->is_enabled) 1501 return -ENODEV; 1502 1503 mutex_lock(&vop->vop_lock); 1504 if (mstimeout <= 0) { 1505 ret = -EINVAL; 1506 goto out; 1507 } 1508 1509 if (vop_line_flag_irq_is_enabled(vop)) { 1510 ret = -EBUSY; 1511 goto out; 1512 } 1513 1514 reinit_completion(&vop->line_flag_completion); 1515 vop_line_flag_irq_enable(vop); 1516 1517 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1518 msecs_to_jiffies(mstimeout)); 1519 vop_line_flag_irq_disable(vop); 1520 1521 if (jiffies_left == 0) { 1522 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1523 ret = -ETIMEDOUT; 1524 goto out; 1525 } 1526 1527 out: 1528 mutex_unlock(&vop->vop_lock); 1529 return ret; 1530 } 1531 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1532 1533 static int vop_bind(struct device *dev, struct device *master, void *data) 1534 { 1535 struct platform_device *pdev = to_platform_device(dev); 1536 const struct vop_data *vop_data; 1537 struct drm_device *drm_dev = data; 1538 struct vop *vop; 1539 struct resource *res; 1540 size_t alloc_size; 1541 int ret, irq; 1542 1543 vop_data = of_device_get_match_data(dev); 1544 if (!vop_data) 1545 return -ENODEV; 1546 1547 /* Allocate vop struct and its vop_win array */ 1548 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size; 1549 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL); 1550 if (!vop) 1551 return -ENOMEM; 1552 1553 vop->dev = dev; 1554 vop->data = vop_data; 1555 vop->drm_dev = drm_dev; 1556 dev_set_drvdata(dev, vop); 1557 1558 vop_win_init(vop); 1559 1560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1561 vop->len = resource_size(res); 1562 vop->regs = devm_ioremap_resource(dev, res); 1563 if (IS_ERR(vop->regs)) 1564 return PTR_ERR(vop->regs); 1565 1566 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1567 if (!vop->regsbak) 1568 return -ENOMEM; 1569 1570 irq = platform_get_irq(pdev, 0); 1571 if (irq < 0) { 1572 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1573 return irq; 1574 } 1575 vop->irq = (unsigned int)irq; 1576 1577 spin_lock_init(&vop->reg_lock); 1578 spin_lock_init(&vop->irq_lock); 1579 mutex_init(&vop->vop_lock); 1580 1581 ret = vop_create_crtc(vop); 1582 if (ret) 1583 return ret; 1584 1585 pm_runtime_enable(&pdev->dev); 1586 1587 ret = vop_initial(vop); 1588 if (ret < 0) { 1589 DRM_DEV_ERROR(&pdev->dev, 1590 "cannot initial vop dev - err %d\n", ret); 1591 goto err_disable_pm_runtime; 1592 } 1593 1594 ret = devm_request_irq(dev, vop->irq, vop_isr, 1595 IRQF_SHARED, dev_name(dev), vop); 1596 if (ret) 1597 goto err_disable_pm_runtime; 1598 1599 /* IRQ is initially disabled; it gets enabled in power_on */ 1600 disable_irq(vop->irq); 1601 1602 return 0; 1603 1604 err_disable_pm_runtime: 1605 pm_runtime_disable(&pdev->dev); 1606 vop_destroy_crtc(vop); 1607 return ret; 1608 } 1609 1610 static void vop_unbind(struct device *dev, struct device *master, void *data) 1611 { 1612 struct vop *vop = dev_get_drvdata(dev); 1613 1614 pm_runtime_disable(dev); 1615 vop_destroy_crtc(vop); 1616 1617 clk_unprepare(vop->aclk); 1618 clk_unprepare(vop->hclk); 1619 clk_unprepare(vop->dclk); 1620 } 1621 1622 const struct component_ops vop_component_ops = { 1623 .bind = vop_bind, 1624 .unbind = vop_unbind, 1625 }; 1626 EXPORT_SYMBOL_GPL(vop_component_ops); 1627