1 /*
2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3  * Author:Mark Yao <mark.yao@rock-chips.com>
4  *
5  * This software is licensed under the terms of the GNU General Public
6  * License version 2, as published by the Free Software Foundation, and
7  * may be copied, distributed, and modified under those terms.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #include <drm/drm.h>
16 #include <drm/drmP.h>
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
22 #ifdef CONFIG_DRM_ANALOGIX_DP
23 #include <drm/bridge/analogix_dp.h>
24 #endif
25 
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/iopoll.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/component.h>
35 
36 #include <linux/reset.h>
37 #include <linux/delay.h>
38 
39 #include "rockchip_drm_drv.h"
40 #include "rockchip_drm_gem.h"
41 #include "rockchip_drm_fb.h"
42 #include "rockchip_drm_psr.h"
43 #include "rockchip_drm_vop.h"
44 
45 #define VOP_WIN_SET(x, win, name, v) \
46 		vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
47 #define VOP_SCL_SET(x, win, name, v) \
48 		vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
49 #define VOP_SCL_SET_EXT(x, win, name, v) \
50 		vop_reg_set(vop, &win->phy->scl->ext->name, \
51 			    win->base, ~0, v, #name)
52 
53 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
54 		vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
55 
56 #define VOP_REG_SET(vop, group, name, v) \
57 		    vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
58 
59 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
60 	do { \
61 		int i, reg = 0, mask = 0; \
62 		for (i = 0; i < vop->data->intr->nintrs; i++) { \
63 			if (vop->data->intr->intrs[i] & type) { \
64 				reg |= (v) << i; \
65 				mask |= 1 << i; \
66 			} \
67 		} \
68 		VOP_INTR_SET_MASK(vop, name, mask, reg); \
69 	} while (0)
70 #define VOP_INTR_GET_TYPE(vop, name, type) \
71 		vop_get_intr_type(vop, &vop->data->intr->name, type)
72 
73 #define VOP_WIN_GET(x, win, name) \
74 		vop_read_reg(x, win->offset, win->phy->name)
75 
76 #define VOP_WIN_GET_YRGBADDR(vop, win) \
77 		vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
78 
79 #define to_vop(x) container_of(x, struct vop, crtc)
80 #define to_vop_win(x) container_of(x, struct vop_win, base)
81 
82 enum vop_pending {
83 	VOP_PENDING_FB_UNREF,
84 };
85 
86 struct vop_win {
87 	struct drm_plane base;
88 	const struct vop_win_data *data;
89 	struct vop *vop;
90 };
91 
92 struct vop {
93 	struct drm_crtc crtc;
94 	struct device *dev;
95 	struct drm_device *drm_dev;
96 	bool is_enabled;
97 
98 	/* mutex vsync_ work */
99 	struct mutex vsync_mutex;
100 	bool vsync_work_pending;
101 	struct completion dsp_hold_completion;
102 
103 	/* protected by dev->event_lock */
104 	struct drm_pending_vblank_event *event;
105 
106 	struct drm_flip_work fb_unref_work;
107 	unsigned long pending;
108 
109 	struct completion line_flag_completion;
110 
111 	const struct vop_data *data;
112 
113 	uint32_t *regsbak;
114 	void __iomem *regs;
115 
116 	/* physical map length of vop register */
117 	uint32_t len;
118 
119 	/* one time only one process allowed to config the register */
120 	spinlock_t reg_lock;
121 	/* lock vop irq reg */
122 	spinlock_t irq_lock;
123 
124 	unsigned int irq;
125 
126 	/* vop AHP clk */
127 	struct clk *hclk;
128 	/* vop dclk */
129 	struct clk *dclk;
130 	/* vop share memory frequency */
131 	struct clk *aclk;
132 
133 	/* vop dclk reset */
134 	struct reset_control *dclk_rst;
135 
136 	struct vop_win win[];
137 };
138 
139 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
140 {
141 	writel(v, vop->regs + offset);
142 	vop->regsbak[offset >> 2] = v;
143 }
144 
145 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
146 {
147 	return readl(vop->regs + offset);
148 }
149 
150 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
151 				    const struct vop_reg *reg)
152 {
153 	return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
154 }
155 
156 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
157 			uint32_t _offset, uint32_t _mask, uint32_t v,
158 			const char *reg_name)
159 {
160 	int offset, mask, shift;
161 
162 	if (!reg || !reg->mask) {
163 		dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
164 		return;
165 	}
166 
167 	offset = reg->offset + _offset;
168 	mask = reg->mask & _mask;
169 	shift = reg->shift;
170 
171 	if (reg->write_mask) {
172 		v = ((v << shift) & 0xffff) | (mask << (shift + 16));
173 	} else {
174 		uint32_t cached_val = vop->regsbak[offset >> 2];
175 
176 		v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
177 		vop->regsbak[offset >> 2] = v;
178 	}
179 
180 	if (reg->relaxed)
181 		writel_relaxed(v, vop->regs + offset);
182 	else
183 		writel(v, vop->regs + offset);
184 }
185 
186 static inline uint32_t vop_get_intr_type(struct vop *vop,
187 					 const struct vop_reg *reg, int type)
188 {
189 	uint32_t i, ret = 0;
190 	uint32_t regs = vop_read_reg(vop, 0, reg);
191 
192 	for (i = 0; i < vop->data->intr->nintrs; i++) {
193 		if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
194 			ret |= vop->data->intr->intrs[i];
195 	}
196 
197 	return ret;
198 }
199 
200 static inline void vop_cfg_done(struct vop *vop)
201 {
202 	VOP_REG_SET(vop, common, cfg_done, 1);
203 }
204 
205 static bool has_rb_swapped(uint32_t format)
206 {
207 	switch (format) {
208 	case DRM_FORMAT_XBGR8888:
209 	case DRM_FORMAT_ABGR8888:
210 	case DRM_FORMAT_BGR888:
211 	case DRM_FORMAT_BGR565:
212 		return true;
213 	default:
214 		return false;
215 	}
216 }
217 
218 static enum vop_data_format vop_convert_format(uint32_t format)
219 {
220 	switch (format) {
221 	case DRM_FORMAT_XRGB8888:
222 	case DRM_FORMAT_ARGB8888:
223 	case DRM_FORMAT_XBGR8888:
224 	case DRM_FORMAT_ABGR8888:
225 		return VOP_FMT_ARGB8888;
226 	case DRM_FORMAT_RGB888:
227 	case DRM_FORMAT_BGR888:
228 		return VOP_FMT_RGB888;
229 	case DRM_FORMAT_RGB565:
230 	case DRM_FORMAT_BGR565:
231 		return VOP_FMT_RGB565;
232 	case DRM_FORMAT_NV12:
233 		return VOP_FMT_YUV420SP;
234 	case DRM_FORMAT_NV16:
235 		return VOP_FMT_YUV422SP;
236 	case DRM_FORMAT_NV24:
237 		return VOP_FMT_YUV444SP;
238 	default:
239 		DRM_ERROR("unsupported format[%08x]\n", format);
240 		return -EINVAL;
241 	}
242 }
243 
244 static bool is_yuv_support(uint32_t format)
245 {
246 	switch (format) {
247 	case DRM_FORMAT_NV12:
248 	case DRM_FORMAT_NV16:
249 	case DRM_FORMAT_NV24:
250 		return true;
251 	default:
252 		return false;
253 	}
254 }
255 
256 static bool is_alpha_support(uint32_t format)
257 {
258 	switch (format) {
259 	case DRM_FORMAT_ARGB8888:
260 	case DRM_FORMAT_ABGR8888:
261 		return true;
262 	default:
263 		return false;
264 	}
265 }
266 
267 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
268 				  uint32_t dst, bool is_horizontal,
269 				  int vsu_mode, int *vskiplines)
270 {
271 	uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
272 
273 	if (is_horizontal) {
274 		if (mode == SCALE_UP)
275 			val = GET_SCL_FT_BIC(src, dst);
276 		else if (mode == SCALE_DOWN)
277 			val = GET_SCL_FT_BILI_DN(src, dst);
278 	} else {
279 		if (mode == SCALE_UP) {
280 			if (vsu_mode == SCALE_UP_BIL)
281 				val = GET_SCL_FT_BILI_UP(src, dst);
282 			else
283 				val = GET_SCL_FT_BIC(src, dst);
284 		} else if (mode == SCALE_DOWN) {
285 			if (vskiplines) {
286 				*vskiplines = scl_get_vskiplines(src, dst);
287 				val = scl_get_bili_dn_vskip(src, dst,
288 							    *vskiplines);
289 			} else {
290 				val = GET_SCL_FT_BILI_DN(src, dst);
291 			}
292 		}
293 	}
294 
295 	return val;
296 }
297 
298 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
299 			     uint32_t src_w, uint32_t src_h, uint32_t dst_w,
300 			     uint32_t dst_h, uint32_t pixel_format)
301 {
302 	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
303 	uint16_t cbcr_hor_scl_mode = SCALE_NONE;
304 	uint16_t cbcr_ver_scl_mode = SCALE_NONE;
305 	int hsub = drm_format_horz_chroma_subsampling(pixel_format);
306 	int vsub = drm_format_vert_chroma_subsampling(pixel_format);
307 	bool is_yuv = is_yuv_support(pixel_format);
308 	uint16_t cbcr_src_w = src_w / hsub;
309 	uint16_t cbcr_src_h = src_h / vsub;
310 	uint16_t vsu_mode;
311 	uint16_t lb_mode;
312 	uint32_t val;
313 	int vskiplines = 0;
314 
315 	if (dst_w > 3840) {
316 		DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
317 		return;
318 	}
319 
320 	if (!win->phy->scl->ext) {
321 		VOP_SCL_SET(vop, win, scale_yrgb_x,
322 			    scl_cal_scale2(src_w, dst_w));
323 		VOP_SCL_SET(vop, win, scale_yrgb_y,
324 			    scl_cal_scale2(src_h, dst_h));
325 		if (is_yuv) {
326 			VOP_SCL_SET(vop, win, scale_cbcr_x,
327 				    scl_cal_scale2(cbcr_src_w, dst_w));
328 			VOP_SCL_SET(vop, win, scale_cbcr_y,
329 				    scl_cal_scale2(cbcr_src_h, dst_h));
330 		}
331 		return;
332 	}
333 
334 	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
335 	yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
336 
337 	if (is_yuv) {
338 		cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
339 		cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
340 		if (cbcr_hor_scl_mode == SCALE_DOWN)
341 			lb_mode = scl_vop_cal_lb_mode(dst_w, true);
342 		else
343 			lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
344 	} else {
345 		if (yrgb_hor_scl_mode == SCALE_DOWN)
346 			lb_mode = scl_vop_cal_lb_mode(dst_w, false);
347 		else
348 			lb_mode = scl_vop_cal_lb_mode(src_w, false);
349 	}
350 
351 	VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
352 	if (lb_mode == LB_RGB_3840X2) {
353 		if (yrgb_ver_scl_mode != SCALE_NONE) {
354 			DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
355 			return;
356 		}
357 		if (cbcr_ver_scl_mode != SCALE_NONE) {
358 			DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
359 			return;
360 		}
361 		vsu_mode = SCALE_UP_BIL;
362 	} else if (lb_mode == LB_RGB_2560X4) {
363 		vsu_mode = SCALE_UP_BIL;
364 	} else {
365 		vsu_mode = SCALE_UP_BIC;
366 	}
367 
368 	val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
369 				true, 0, NULL);
370 	VOP_SCL_SET(vop, win, scale_yrgb_x, val);
371 	val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
372 				false, vsu_mode, &vskiplines);
373 	VOP_SCL_SET(vop, win, scale_yrgb_y, val);
374 
375 	VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
376 	VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
377 
378 	VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
379 	VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
380 	VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
381 	VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
382 	VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
383 	if (is_yuv) {
384 		val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
385 					dst_w, true, 0, NULL);
386 		VOP_SCL_SET(vop, win, scale_cbcr_x, val);
387 		val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
388 					dst_h, false, vsu_mode, &vskiplines);
389 		VOP_SCL_SET(vop, win, scale_cbcr_y, val);
390 
391 		VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
392 		VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
393 		VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
394 		VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
395 		VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
396 		VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
397 		VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
398 	}
399 }
400 
401 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
402 {
403 	unsigned long flags;
404 
405 	if (WARN_ON(!vop->is_enabled))
406 		return;
407 
408 	spin_lock_irqsave(&vop->irq_lock, flags);
409 
410 	VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
411 	VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
412 
413 	spin_unlock_irqrestore(&vop->irq_lock, flags);
414 }
415 
416 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
417 {
418 	unsigned long flags;
419 
420 	if (WARN_ON(!vop->is_enabled))
421 		return;
422 
423 	spin_lock_irqsave(&vop->irq_lock, flags);
424 
425 	VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
426 
427 	spin_unlock_irqrestore(&vop->irq_lock, flags);
428 }
429 
430 /*
431  * (1) each frame starts at the start of the Vsync pulse which is signaled by
432  *     the "FRAME_SYNC" interrupt.
433  * (2) the active data region of each frame ends at dsp_vact_end
434  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
435  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
436  *
437  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
438  * Interrupts
439  * LINE_FLAG -------------------------------+
440  * FRAME_SYNC ----+                         |
441  *                |                         |
442  *                v                         v
443  *                | Vsync | Vbp |  Vactive  | Vfp |
444  *                        ^     ^           ^     ^
445  *                        |     |           |     |
446  *                        |     |           |     |
447  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
448  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
449  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
450  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
451  */
452 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
453 {
454 	uint32_t line_flag_irq;
455 	unsigned long flags;
456 
457 	spin_lock_irqsave(&vop->irq_lock, flags);
458 
459 	line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
460 
461 	spin_unlock_irqrestore(&vop->irq_lock, flags);
462 
463 	return !!line_flag_irq;
464 }
465 
466 static void vop_line_flag_irq_enable(struct vop *vop)
467 {
468 	unsigned long flags;
469 
470 	if (WARN_ON(!vop->is_enabled))
471 		return;
472 
473 	spin_lock_irqsave(&vop->irq_lock, flags);
474 
475 	VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
476 	VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
477 
478 	spin_unlock_irqrestore(&vop->irq_lock, flags);
479 }
480 
481 static void vop_line_flag_irq_disable(struct vop *vop)
482 {
483 	unsigned long flags;
484 
485 	if (WARN_ON(!vop->is_enabled))
486 		return;
487 
488 	spin_lock_irqsave(&vop->irq_lock, flags);
489 
490 	VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
491 
492 	spin_unlock_irqrestore(&vop->irq_lock, flags);
493 }
494 
495 static int vop_enable(struct drm_crtc *crtc)
496 {
497 	struct vop *vop = to_vop(crtc);
498 	int ret, i;
499 
500 	ret = pm_runtime_get_sync(vop->dev);
501 	if (ret < 0) {
502 		dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
503 		return ret;
504 	}
505 
506 	ret = clk_enable(vop->hclk);
507 	if (WARN_ON(ret < 0))
508 		goto err_put_pm_runtime;
509 
510 	ret = clk_enable(vop->dclk);
511 	if (WARN_ON(ret < 0))
512 		goto err_disable_hclk;
513 
514 	ret = clk_enable(vop->aclk);
515 	if (WARN_ON(ret < 0))
516 		goto err_disable_dclk;
517 
518 	/*
519 	 * Slave iommu shares power, irq and clock with vop.  It was associated
520 	 * automatically with this master device via common driver code.
521 	 * Now that we have enabled the clock we attach it to the shared drm
522 	 * mapping.
523 	 */
524 	ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
525 	if (ret) {
526 		dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
527 		goto err_disable_aclk;
528 	}
529 
530 	memcpy(vop->regs, vop->regsbak, vop->len);
531 	/*
532 	 * We need to make sure that all windows are disabled before we
533 	 * enable the crtc. Otherwise we might try to scan from a destroyed
534 	 * buffer later.
535 	 */
536 	for (i = 0; i < vop->data->win_size; i++) {
537 		struct vop_win *vop_win = &vop->win[i];
538 		const struct vop_win_data *win = vop_win->data;
539 
540 		spin_lock(&vop->reg_lock);
541 		VOP_WIN_SET(vop, win, enable, 0);
542 		spin_unlock(&vop->reg_lock);
543 	}
544 
545 	vop_cfg_done(vop);
546 
547 	/*
548 	 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
549 	 */
550 	vop->is_enabled = true;
551 
552 	spin_lock(&vop->reg_lock);
553 
554 	VOP_REG_SET(vop, common, standby, 1);
555 
556 	spin_unlock(&vop->reg_lock);
557 
558 	enable_irq(vop->irq);
559 
560 	drm_crtc_vblank_on(crtc);
561 
562 	return 0;
563 
564 err_disable_aclk:
565 	clk_disable(vop->aclk);
566 err_disable_dclk:
567 	clk_disable(vop->dclk);
568 err_disable_hclk:
569 	clk_disable(vop->hclk);
570 err_put_pm_runtime:
571 	pm_runtime_put_sync(vop->dev);
572 	return ret;
573 }
574 
575 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
576 				    struct drm_crtc_state *old_state)
577 {
578 	struct vop *vop = to_vop(crtc);
579 
580 	WARN_ON(vop->event);
581 
582 	rockchip_drm_psr_deactivate(&vop->crtc);
583 
584 	drm_crtc_vblank_off(crtc);
585 
586 	/*
587 	 * Vop standby will take effect at end of current frame,
588 	 * if dsp hold valid irq happen, it means standby complete.
589 	 *
590 	 * we must wait standby complete when we want to disable aclk,
591 	 * if not, memory bus maybe dead.
592 	 */
593 	reinit_completion(&vop->dsp_hold_completion);
594 	vop_dsp_hold_valid_irq_enable(vop);
595 
596 	spin_lock(&vop->reg_lock);
597 
598 	VOP_REG_SET(vop, common, standby, 1);
599 
600 	spin_unlock(&vop->reg_lock);
601 
602 	wait_for_completion(&vop->dsp_hold_completion);
603 
604 	vop_dsp_hold_valid_irq_disable(vop);
605 
606 	disable_irq(vop->irq);
607 
608 	vop->is_enabled = false;
609 
610 	/*
611 	 * vop standby complete, so iommu detach is safe.
612 	 */
613 	rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
614 
615 	clk_disable(vop->dclk);
616 	clk_disable(vop->aclk);
617 	clk_disable(vop->hclk);
618 	pm_runtime_put(vop->dev);
619 
620 	if (crtc->state->event && !crtc->state->active) {
621 		spin_lock_irq(&crtc->dev->event_lock);
622 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
623 		spin_unlock_irq(&crtc->dev->event_lock);
624 
625 		crtc->state->event = NULL;
626 	}
627 }
628 
629 static void vop_plane_destroy(struct drm_plane *plane)
630 {
631 	drm_plane_cleanup(plane);
632 }
633 
634 static int vop_plane_atomic_check(struct drm_plane *plane,
635 			   struct drm_plane_state *state)
636 {
637 	struct drm_crtc *crtc = state->crtc;
638 	struct drm_crtc_state *crtc_state;
639 	struct drm_framebuffer *fb = state->fb;
640 	struct vop_win *vop_win = to_vop_win(plane);
641 	const struct vop_win_data *win = vop_win->data;
642 	int ret;
643 	struct drm_rect clip;
644 	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
645 					DRM_PLANE_HELPER_NO_SCALING;
646 	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
647 					DRM_PLANE_HELPER_NO_SCALING;
648 
649 	if (!crtc || !fb)
650 		return 0;
651 
652 	crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
653 	if (WARN_ON(!crtc_state))
654 		return -EINVAL;
655 
656 	clip.x1 = 0;
657 	clip.y1 = 0;
658 	clip.x2 = crtc_state->adjusted_mode.hdisplay;
659 	clip.y2 = crtc_state->adjusted_mode.vdisplay;
660 
661 	ret = drm_plane_helper_check_state(state, &clip,
662 					   min_scale, max_scale,
663 					   true, true);
664 	if (ret)
665 		return ret;
666 
667 	if (!state->visible)
668 		return 0;
669 
670 	ret = vop_convert_format(fb->format->format);
671 	if (ret < 0)
672 		return ret;
673 
674 	/*
675 	 * Src.x1 can be odd when do clip, but yuv plane start point
676 	 * need align with 2 pixel.
677 	 */
678 	if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) {
679 		DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
680 		return -EINVAL;
681 	}
682 
683 	return 0;
684 }
685 
686 static void vop_plane_atomic_disable(struct drm_plane *plane,
687 				     struct drm_plane_state *old_state)
688 {
689 	struct vop_win *vop_win = to_vop_win(plane);
690 	const struct vop_win_data *win = vop_win->data;
691 	struct vop *vop = to_vop(old_state->crtc);
692 
693 	if (!old_state->crtc)
694 		return;
695 
696 	spin_lock(&vop->reg_lock);
697 
698 	VOP_WIN_SET(vop, win, enable, 0);
699 
700 	spin_unlock(&vop->reg_lock);
701 }
702 
703 static void vop_plane_atomic_update(struct drm_plane *plane,
704 		struct drm_plane_state *old_state)
705 {
706 	struct drm_plane_state *state = plane->state;
707 	struct drm_crtc *crtc = state->crtc;
708 	struct vop_win *vop_win = to_vop_win(plane);
709 	const struct vop_win_data *win = vop_win->data;
710 	struct vop *vop = to_vop(state->crtc);
711 	struct drm_framebuffer *fb = state->fb;
712 	unsigned int actual_w, actual_h;
713 	unsigned int dsp_stx, dsp_sty;
714 	uint32_t act_info, dsp_info, dsp_st;
715 	struct drm_rect *src = &state->src;
716 	struct drm_rect *dest = &state->dst;
717 	struct drm_gem_object *obj, *uv_obj;
718 	struct rockchip_gem_object *rk_obj, *rk_uv_obj;
719 	unsigned long offset;
720 	dma_addr_t dma_addr;
721 	uint32_t val;
722 	bool rb_swap;
723 	int format;
724 
725 	/*
726 	 * can't update plane when vop is disabled.
727 	 */
728 	if (WARN_ON(!crtc))
729 		return;
730 
731 	if (WARN_ON(!vop->is_enabled))
732 		return;
733 
734 	if (!state->visible) {
735 		vop_plane_atomic_disable(plane, old_state);
736 		return;
737 	}
738 
739 	obj = rockchip_fb_get_gem_obj(fb, 0);
740 	rk_obj = to_rockchip_obj(obj);
741 
742 	actual_w = drm_rect_width(src) >> 16;
743 	actual_h = drm_rect_height(src) >> 16;
744 	act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
745 
746 	dsp_info = (drm_rect_height(dest) - 1) << 16;
747 	dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
748 
749 	dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
750 	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
751 	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
752 
753 	offset = (src->x1 >> 16) * fb->format->cpp[0];
754 	offset += (src->y1 >> 16) * fb->pitches[0];
755 	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
756 
757 	format = vop_convert_format(fb->format->format);
758 
759 	spin_lock(&vop->reg_lock);
760 
761 	VOP_WIN_SET(vop, win, format, format);
762 	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
763 	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
764 	if (is_yuv_support(fb->format->format)) {
765 		int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
766 		int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
767 		int bpp = fb->format->cpp[1];
768 
769 		uv_obj = rockchip_fb_get_gem_obj(fb, 1);
770 		rk_uv_obj = to_rockchip_obj(uv_obj);
771 
772 		offset = (src->x1 >> 16) * bpp / hsub;
773 		offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
774 
775 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
776 		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
777 		VOP_WIN_SET(vop, win, uv_mst, dma_addr);
778 	}
779 
780 	if (win->phy->scl)
781 		scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
782 				    drm_rect_width(dest), drm_rect_height(dest),
783 				    fb->format->format);
784 
785 	VOP_WIN_SET(vop, win, act_info, act_info);
786 	VOP_WIN_SET(vop, win, dsp_info, dsp_info);
787 	VOP_WIN_SET(vop, win, dsp_st, dsp_st);
788 
789 	rb_swap = has_rb_swapped(fb->format->format);
790 	VOP_WIN_SET(vop, win, rb_swap, rb_swap);
791 
792 	if (is_alpha_support(fb->format->format)) {
793 		VOP_WIN_SET(vop, win, dst_alpha_ctl,
794 			    DST_FACTOR_M0(ALPHA_SRC_INVERSE));
795 		val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
796 			SRC_ALPHA_M0(ALPHA_STRAIGHT) |
797 			SRC_BLEND_M0(ALPHA_PER_PIX) |
798 			SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
799 			SRC_FACTOR_M0(ALPHA_ONE);
800 		VOP_WIN_SET(vop, win, src_alpha_ctl, val);
801 	} else {
802 		VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
803 	}
804 
805 	VOP_WIN_SET(vop, win, enable, 1);
806 	spin_unlock(&vop->reg_lock);
807 }
808 
809 static const struct drm_plane_helper_funcs plane_helper_funcs = {
810 	.atomic_check = vop_plane_atomic_check,
811 	.atomic_update = vop_plane_atomic_update,
812 	.atomic_disable = vop_plane_atomic_disable,
813 };
814 
815 static const struct drm_plane_funcs vop_plane_funcs = {
816 	.update_plane	= drm_atomic_helper_update_plane,
817 	.disable_plane	= drm_atomic_helper_disable_plane,
818 	.destroy = vop_plane_destroy,
819 	.reset = drm_atomic_helper_plane_reset,
820 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
821 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
822 };
823 
824 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
825 {
826 	struct vop *vop = to_vop(crtc);
827 	unsigned long flags;
828 
829 	if (WARN_ON(!vop->is_enabled))
830 		return -EPERM;
831 
832 	spin_lock_irqsave(&vop->irq_lock, flags);
833 
834 	VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
835 	VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
836 
837 	spin_unlock_irqrestore(&vop->irq_lock, flags);
838 
839 	return 0;
840 }
841 
842 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
843 {
844 	struct vop *vop = to_vop(crtc);
845 	unsigned long flags;
846 
847 	if (WARN_ON(!vop->is_enabled))
848 		return;
849 
850 	spin_lock_irqsave(&vop->irq_lock, flags);
851 
852 	VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
853 
854 	spin_unlock_irqrestore(&vop->irq_lock, flags);
855 }
856 
857 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
858 				const struct drm_display_mode *mode,
859 				struct drm_display_mode *adjusted_mode)
860 {
861 	struct vop *vop = to_vop(crtc);
862 
863 	adjusted_mode->clock =
864 		clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
865 
866 	return true;
867 }
868 
869 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
870 				   struct drm_crtc_state *old_state)
871 {
872 	struct vop *vop = to_vop(crtc);
873 	const struct vop_data *vop_data = vop->data;
874 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
875 	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
876 	u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
877 	u16 hdisplay = adjusted_mode->hdisplay;
878 	u16 htotal = adjusted_mode->htotal;
879 	u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
880 	u16 hact_end = hact_st + hdisplay;
881 	u16 vdisplay = adjusted_mode->vdisplay;
882 	u16 vtotal = adjusted_mode->vtotal;
883 	u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
884 	u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
885 	u16 vact_end = vact_st + vdisplay;
886 	uint32_t pin_pol, val;
887 	int ret;
888 
889 	WARN_ON(vop->event);
890 
891 	ret = vop_enable(crtc);
892 	if (ret) {
893 		DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
894 		return;
895 	}
896 
897 	pin_pol = BIT(DCLK_INVERT);
898 	pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
899 		   BIT(HSYNC_POSITIVE) : 0;
900 	pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
901 		   BIT(VSYNC_POSITIVE) : 0;
902 	VOP_REG_SET(vop, output, pin_pol, pin_pol);
903 
904 	switch (s->output_type) {
905 	case DRM_MODE_CONNECTOR_LVDS:
906 		VOP_REG_SET(vop, output, rgb_en, 1);
907 		VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
908 		break;
909 	case DRM_MODE_CONNECTOR_eDP:
910 		VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
911 		VOP_REG_SET(vop, output, edp_en, 1);
912 		break;
913 	case DRM_MODE_CONNECTOR_HDMIA:
914 		VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
915 		VOP_REG_SET(vop, output, hdmi_en, 1);
916 		break;
917 	case DRM_MODE_CONNECTOR_DSI:
918 		VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
919 		VOP_REG_SET(vop, output, mipi_en, 1);
920 		break;
921 	case DRM_MODE_CONNECTOR_DisplayPort:
922 		pin_pol &= ~BIT(DCLK_INVERT);
923 		VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
924 		VOP_REG_SET(vop, output, dp_en, 1);
925 		break;
926 	default:
927 		DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
928 			      s->output_type);
929 	}
930 
931 	/*
932 	 * if vop is not support RGB10 output, need force RGB10 to RGB888.
933 	 */
934 	if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
935 	    !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
936 		s->output_mode = ROCKCHIP_OUT_MODE_P888;
937 	VOP_REG_SET(vop, common, out_mode, s->output_mode);
938 
939 	VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
940 	val = hact_st << 16;
941 	val |= hact_end;
942 	VOP_REG_SET(vop, modeset, hact_st_end, val);
943 	VOP_REG_SET(vop, modeset, hpost_st_end, val);
944 
945 	VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
946 	val = vact_st << 16;
947 	val |= vact_end;
948 	VOP_REG_SET(vop, modeset, vact_st_end, val);
949 	VOP_REG_SET(vop, modeset, vpost_st_end, val);
950 
951 	VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
952 
953 	clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
954 
955 	VOP_REG_SET(vop, common, standby, 0);
956 
957 	rockchip_drm_psr_activate(&vop->crtc);
958 }
959 
960 static bool vop_fs_irq_is_pending(struct vop *vop)
961 {
962 	return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
963 }
964 
965 static void vop_wait_for_irq_handler(struct vop *vop)
966 {
967 	bool pending;
968 	int ret;
969 
970 	/*
971 	 * Spin until frame start interrupt status bit goes low, which means
972 	 * that interrupt handler was invoked and cleared it. The timeout of
973 	 * 10 msecs is really too long, but it is just a safety measure if
974 	 * something goes really wrong. The wait will only happen in the very
975 	 * unlikely case of a vblank happening exactly at the same time and
976 	 * shouldn't exceed microseconds range.
977 	 */
978 	ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
979 					!pending, 0, 10 * 1000);
980 	if (ret)
981 		DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
982 
983 	synchronize_irq(vop->irq);
984 }
985 
986 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
987 				  struct drm_crtc_state *old_crtc_state)
988 {
989 	struct drm_atomic_state *old_state = old_crtc_state->state;
990 	struct drm_plane_state *old_plane_state, *new_plane_state;
991 	struct vop *vop = to_vop(crtc);
992 	struct drm_plane *plane;
993 	int i;
994 
995 	if (WARN_ON(!vop->is_enabled))
996 		return;
997 
998 	spin_lock(&vop->reg_lock);
999 
1000 	vop_cfg_done(vop);
1001 
1002 	spin_unlock(&vop->reg_lock);
1003 
1004 	/*
1005 	 * There is a (rather unlikely) possiblity that a vblank interrupt
1006 	 * fired before we set the cfg_done bit. To avoid spuriously
1007 	 * signalling flip completion we need to wait for it to finish.
1008 	 */
1009 	vop_wait_for_irq_handler(vop);
1010 
1011 	spin_lock_irq(&crtc->dev->event_lock);
1012 	if (crtc->state->event) {
1013 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1014 		WARN_ON(vop->event);
1015 
1016 		vop->event = crtc->state->event;
1017 		crtc->state->event = NULL;
1018 	}
1019 	spin_unlock_irq(&crtc->dev->event_lock);
1020 
1021 	for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1022 				       new_plane_state, i) {
1023 		if (!old_plane_state->fb)
1024 			continue;
1025 
1026 		if (old_plane_state->fb == new_plane_state->fb)
1027 			continue;
1028 
1029 		drm_framebuffer_get(old_plane_state->fb);
1030 		drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1031 		set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1032 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1033 	}
1034 }
1035 
1036 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1037 				  struct drm_crtc_state *old_crtc_state)
1038 {
1039 	rockchip_drm_psr_flush(crtc);
1040 }
1041 
1042 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1043 	.mode_fixup = vop_crtc_mode_fixup,
1044 	.atomic_flush = vop_crtc_atomic_flush,
1045 	.atomic_begin = vop_crtc_atomic_begin,
1046 	.atomic_enable = vop_crtc_atomic_enable,
1047 	.atomic_disable = vop_crtc_atomic_disable,
1048 };
1049 
1050 static void vop_crtc_destroy(struct drm_crtc *crtc)
1051 {
1052 	drm_crtc_cleanup(crtc);
1053 }
1054 
1055 static void vop_crtc_reset(struct drm_crtc *crtc)
1056 {
1057 	if (crtc->state)
1058 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
1059 	kfree(crtc->state);
1060 
1061 	crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1062 	if (crtc->state)
1063 		crtc->state->crtc = crtc;
1064 }
1065 
1066 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1067 {
1068 	struct rockchip_crtc_state *rockchip_state;
1069 
1070 	rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1071 	if (!rockchip_state)
1072 		return NULL;
1073 
1074 	__drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1075 	return &rockchip_state->base;
1076 }
1077 
1078 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1079 				   struct drm_crtc_state *state)
1080 {
1081 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1082 
1083 	__drm_atomic_helper_crtc_destroy_state(&s->base);
1084 	kfree(s);
1085 }
1086 
1087 #ifdef CONFIG_DRM_ANALOGIX_DP
1088 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1089 {
1090 	struct drm_connector *connector;
1091 	struct drm_connector_list_iter conn_iter;
1092 
1093 	drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1094 	drm_for_each_connector_iter(connector, &conn_iter) {
1095 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1096 			drm_connector_list_iter_end(&conn_iter);
1097 			return connector;
1098 		}
1099 	}
1100 	drm_connector_list_iter_end(&conn_iter);
1101 
1102 	return NULL;
1103 }
1104 
1105 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1106 				   const char *source_name, size_t *values_cnt)
1107 {
1108 	struct vop *vop = to_vop(crtc);
1109 	struct drm_connector *connector;
1110 	int ret;
1111 
1112 	connector = vop_get_edp_connector(vop);
1113 	if (!connector)
1114 		return -EINVAL;
1115 
1116 	*values_cnt = 3;
1117 
1118 	if (source_name && strcmp(source_name, "auto") == 0)
1119 		ret = analogix_dp_start_crc(connector);
1120 	else if (!source_name)
1121 		ret = analogix_dp_stop_crc(connector);
1122 	else
1123 		ret = -EINVAL;
1124 
1125 	return ret;
1126 }
1127 #else
1128 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1129 				   const char *source_name, size_t *values_cnt)
1130 {
1131 	return -ENODEV;
1132 }
1133 #endif
1134 
1135 static const struct drm_crtc_funcs vop_crtc_funcs = {
1136 	.set_config = drm_atomic_helper_set_config,
1137 	.page_flip = drm_atomic_helper_page_flip,
1138 	.destroy = vop_crtc_destroy,
1139 	.reset = vop_crtc_reset,
1140 	.atomic_duplicate_state = vop_crtc_duplicate_state,
1141 	.atomic_destroy_state = vop_crtc_destroy_state,
1142 	.enable_vblank = vop_crtc_enable_vblank,
1143 	.disable_vblank = vop_crtc_disable_vblank,
1144 	.set_crc_source = vop_crtc_set_crc_source,
1145 };
1146 
1147 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1148 {
1149 	struct vop *vop = container_of(work, struct vop, fb_unref_work);
1150 	struct drm_framebuffer *fb = val;
1151 
1152 	drm_crtc_vblank_put(&vop->crtc);
1153 	drm_framebuffer_put(fb);
1154 }
1155 
1156 static void vop_handle_vblank(struct vop *vop)
1157 {
1158 	struct drm_device *drm = vop->drm_dev;
1159 	struct drm_crtc *crtc = &vop->crtc;
1160 	unsigned long flags;
1161 
1162 	spin_lock_irqsave(&drm->event_lock, flags);
1163 	if (vop->event) {
1164 		drm_crtc_send_vblank_event(crtc, vop->event);
1165 		drm_crtc_vblank_put(crtc);
1166 		vop->event = NULL;
1167 	}
1168 	spin_unlock_irqrestore(&drm->event_lock, flags);
1169 
1170 	if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1171 		drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1172 }
1173 
1174 static irqreturn_t vop_isr(int irq, void *data)
1175 {
1176 	struct vop *vop = data;
1177 	struct drm_crtc *crtc = &vop->crtc;
1178 	uint32_t active_irqs;
1179 	unsigned long flags;
1180 	int ret = IRQ_NONE;
1181 
1182 	/*
1183 	 * interrupt register has interrupt status, enable and clear bits, we
1184 	 * must hold irq_lock to avoid a race with enable/disable_vblank().
1185 	*/
1186 	spin_lock_irqsave(&vop->irq_lock, flags);
1187 
1188 	active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1189 	/* Clear all active interrupt sources */
1190 	if (active_irqs)
1191 		VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1192 
1193 	spin_unlock_irqrestore(&vop->irq_lock, flags);
1194 
1195 	/* This is expected for vop iommu irqs, since the irq is shared */
1196 	if (!active_irqs)
1197 		return IRQ_NONE;
1198 
1199 	if (active_irqs & DSP_HOLD_VALID_INTR) {
1200 		complete(&vop->dsp_hold_completion);
1201 		active_irqs &= ~DSP_HOLD_VALID_INTR;
1202 		ret = IRQ_HANDLED;
1203 	}
1204 
1205 	if (active_irqs & LINE_FLAG_INTR) {
1206 		complete(&vop->line_flag_completion);
1207 		active_irqs &= ~LINE_FLAG_INTR;
1208 		ret = IRQ_HANDLED;
1209 	}
1210 
1211 	if (active_irqs & FS_INTR) {
1212 		drm_crtc_handle_vblank(crtc);
1213 		vop_handle_vblank(vop);
1214 		active_irqs &= ~FS_INTR;
1215 		ret = IRQ_HANDLED;
1216 	}
1217 
1218 	/* Unhandled irqs are spurious. */
1219 	if (active_irqs)
1220 		DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1221 			      active_irqs);
1222 
1223 	return ret;
1224 }
1225 
1226 static int vop_create_crtc(struct vop *vop)
1227 {
1228 	const struct vop_data *vop_data = vop->data;
1229 	struct device *dev = vop->dev;
1230 	struct drm_device *drm_dev = vop->drm_dev;
1231 	struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1232 	struct drm_crtc *crtc = &vop->crtc;
1233 	struct device_node *port;
1234 	int ret;
1235 	int i;
1236 
1237 	/*
1238 	 * Create drm_plane for primary and cursor planes first, since we need
1239 	 * to pass them to drm_crtc_init_with_planes, which sets the
1240 	 * "possible_crtcs" to the newly initialized crtc.
1241 	 */
1242 	for (i = 0; i < vop_data->win_size; i++) {
1243 		struct vop_win *vop_win = &vop->win[i];
1244 		const struct vop_win_data *win_data = vop_win->data;
1245 
1246 		if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1247 		    win_data->type != DRM_PLANE_TYPE_CURSOR)
1248 			continue;
1249 
1250 		ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1251 					       0, &vop_plane_funcs,
1252 					       win_data->phy->data_formats,
1253 					       win_data->phy->nformats,
1254 					       NULL, win_data->type, NULL);
1255 		if (ret) {
1256 			DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1257 				      ret);
1258 			goto err_cleanup_planes;
1259 		}
1260 
1261 		plane = &vop_win->base;
1262 		drm_plane_helper_add(plane, &plane_helper_funcs);
1263 		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1264 			primary = plane;
1265 		else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1266 			cursor = plane;
1267 	}
1268 
1269 	ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1270 					&vop_crtc_funcs, NULL);
1271 	if (ret)
1272 		goto err_cleanup_planes;
1273 
1274 	drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1275 
1276 	/*
1277 	 * Create drm_planes for overlay windows with possible_crtcs restricted
1278 	 * to the newly created crtc.
1279 	 */
1280 	for (i = 0; i < vop_data->win_size; i++) {
1281 		struct vop_win *vop_win = &vop->win[i];
1282 		const struct vop_win_data *win_data = vop_win->data;
1283 		unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1284 
1285 		if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1286 			continue;
1287 
1288 		ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1289 					       possible_crtcs,
1290 					       &vop_plane_funcs,
1291 					       win_data->phy->data_formats,
1292 					       win_data->phy->nformats,
1293 					       NULL, win_data->type, NULL);
1294 		if (ret) {
1295 			DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1296 				      ret);
1297 			goto err_cleanup_crtc;
1298 		}
1299 		drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1300 	}
1301 
1302 	port = of_get_child_by_name(dev->of_node, "port");
1303 	if (!port) {
1304 		DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1305 			      dev->of_node);
1306 		ret = -ENOENT;
1307 		goto err_cleanup_crtc;
1308 	}
1309 
1310 	drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1311 			   vop_fb_unref_worker);
1312 
1313 	init_completion(&vop->dsp_hold_completion);
1314 	init_completion(&vop->line_flag_completion);
1315 	crtc->port = port;
1316 
1317 	return 0;
1318 
1319 err_cleanup_crtc:
1320 	drm_crtc_cleanup(crtc);
1321 err_cleanup_planes:
1322 	list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1323 				 head)
1324 		drm_plane_cleanup(plane);
1325 	return ret;
1326 }
1327 
1328 static void vop_destroy_crtc(struct vop *vop)
1329 {
1330 	struct drm_crtc *crtc = &vop->crtc;
1331 	struct drm_device *drm_dev = vop->drm_dev;
1332 	struct drm_plane *plane, *tmp;
1333 
1334 	of_node_put(crtc->port);
1335 
1336 	/*
1337 	 * We need to cleanup the planes now.  Why?
1338 	 *
1339 	 * The planes are "&vop->win[i].base".  That means the memory is
1340 	 * all part of the big "struct vop" chunk of memory.  That memory
1341 	 * was devm allocated and associated with this component.  We need to
1342 	 * free it ourselves before vop_unbind() finishes.
1343 	 */
1344 	list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1345 				 head)
1346 		vop_plane_destroy(plane);
1347 
1348 	/*
1349 	 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1350 	 * references the CRTC.
1351 	 */
1352 	drm_crtc_cleanup(crtc);
1353 	drm_flip_work_cleanup(&vop->fb_unref_work);
1354 }
1355 
1356 static int vop_initial(struct vop *vop)
1357 {
1358 	const struct vop_data *vop_data = vop->data;
1359 	struct reset_control *ahb_rst;
1360 	int i, ret;
1361 
1362 	vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1363 	if (IS_ERR(vop->hclk)) {
1364 		dev_err(vop->dev, "failed to get hclk source\n");
1365 		return PTR_ERR(vop->hclk);
1366 	}
1367 	vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1368 	if (IS_ERR(vop->aclk)) {
1369 		dev_err(vop->dev, "failed to get aclk source\n");
1370 		return PTR_ERR(vop->aclk);
1371 	}
1372 	vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1373 	if (IS_ERR(vop->dclk)) {
1374 		dev_err(vop->dev, "failed to get dclk source\n");
1375 		return PTR_ERR(vop->dclk);
1376 	}
1377 
1378 	ret = pm_runtime_get_sync(vop->dev);
1379 	if (ret < 0) {
1380 		dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
1381 		return ret;
1382 	}
1383 
1384 	ret = clk_prepare(vop->dclk);
1385 	if (ret < 0) {
1386 		dev_err(vop->dev, "failed to prepare dclk\n");
1387 		goto err_put_pm_runtime;
1388 	}
1389 
1390 	/* Enable both the hclk and aclk to setup the vop */
1391 	ret = clk_prepare_enable(vop->hclk);
1392 	if (ret < 0) {
1393 		dev_err(vop->dev, "failed to prepare/enable hclk\n");
1394 		goto err_unprepare_dclk;
1395 	}
1396 
1397 	ret = clk_prepare_enable(vop->aclk);
1398 	if (ret < 0) {
1399 		dev_err(vop->dev, "failed to prepare/enable aclk\n");
1400 		goto err_disable_hclk;
1401 	}
1402 
1403 	/*
1404 	 * do hclk_reset, reset all vop registers.
1405 	 */
1406 	ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1407 	if (IS_ERR(ahb_rst)) {
1408 		dev_err(vop->dev, "failed to get ahb reset\n");
1409 		ret = PTR_ERR(ahb_rst);
1410 		goto err_disable_aclk;
1411 	}
1412 	reset_control_assert(ahb_rst);
1413 	usleep_range(10, 20);
1414 	reset_control_deassert(ahb_rst);
1415 
1416 	memcpy(vop->regsbak, vop->regs, vop->len);
1417 
1418 	VOP_REG_SET(vop, misc, global_regdone_en, 1);
1419 	VOP_REG_SET(vop, common, dsp_blank, 0);
1420 
1421 	for (i = 0; i < vop_data->win_size; i++) {
1422 		const struct vop_win_data *win = &vop_data->win[i];
1423 		int channel = i * 2 + 1;
1424 
1425 		VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1426 		VOP_WIN_SET(vop, win, enable, 0);
1427 		VOP_WIN_SET(vop, win, gate, 1);
1428 	}
1429 
1430 	vop_cfg_done(vop);
1431 
1432 	/*
1433 	 * do dclk_reset, let all config take affect.
1434 	 */
1435 	vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1436 	if (IS_ERR(vop->dclk_rst)) {
1437 		dev_err(vop->dev, "failed to get dclk reset\n");
1438 		ret = PTR_ERR(vop->dclk_rst);
1439 		goto err_disable_aclk;
1440 	}
1441 	reset_control_assert(vop->dclk_rst);
1442 	usleep_range(10, 20);
1443 	reset_control_deassert(vop->dclk_rst);
1444 
1445 	clk_disable(vop->hclk);
1446 	clk_disable(vop->aclk);
1447 
1448 	vop->is_enabled = false;
1449 
1450 	pm_runtime_put_sync(vop->dev);
1451 
1452 	return 0;
1453 
1454 err_disable_aclk:
1455 	clk_disable_unprepare(vop->aclk);
1456 err_disable_hclk:
1457 	clk_disable_unprepare(vop->hclk);
1458 err_unprepare_dclk:
1459 	clk_unprepare(vop->dclk);
1460 err_put_pm_runtime:
1461 	pm_runtime_put_sync(vop->dev);
1462 	return ret;
1463 }
1464 
1465 /*
1466  * Initialize the vop->win array elements.
1467  */
1468 static void vop_win_init(struct vop *vop)
1469 {
1470 	const struct vop_data *vop_data = vop->data;
1471 	unsigned int i;
1472 
1473 	for (i = 0; i < vop_data->win_size; i++) {
1474 		struct vop_win *vop_win = &vop->win[i];
1475 		const struct vop_win_data *win_data = &vop_data->win[i];
1476 
1477 		vop_win->data = win_data;
1478 		vop_win->vop = vop;
1479 	}
1480 }
1481 
1482 /**
1483  * rockchip_drm_wait_vact_end
1484  * @crtc: CRTC to enable line flag
1485  * @mstimeout: millisecond for timeout
1486  *
1487  * Wait for vact_end line flag irq or timeout.
1488  *
1489  * Returns:
1490  * Zero on success, negative errno on failure.
1491  */
1492 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1493 {
1494 	struct vop *vop = to_vop(crtc);
1495 	unsigned long jiffies_left;
1496 
1497 	if (!crtc || !vop->is_enabled)
1498 		return -ENODEV;
1499 
1500 	if (mstimeout <= 0)
1501 		return -EINVAL;
1502 
1503 	if (vop_line_flag_irq_is_enabled(vop))
1504 		return -EBUSY;
1505 
1506 	reinit_completion(&vop->line_flag_completion);
1507 	vop_line_flag_irq_enable(vop);
1508 
1509 	jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1510 						   msecs_to_jiffies(mstimeout));
1511 	vop_line_flag_irq_disable(vop);
1512 
1513 	if (jiffies_left == 0) {
1514 		dev_err(vop->dev, "Timeout waiting for IRQ\n");
1515 		return -ETIMEDOUT;
1516 	}
1517 
1518 	return 0;
1519 }
1520 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1521 
1522 static int vop_bind(struct device *dev, struct device *master, void *data)
1523 {
1524 	struct platform_device *pdev = to_platform_device(dev);
1525 	const struct vop_data *vop_data;
1526 	struct drm_device *drm_dev = data;
1527 	struct vop *vop;
1528 	struct resource *res;
1529 	size_t alloc_size;
1530 	int ret, irq;
1531 
1532 	vop_data = of_device_get_match_data(dev);
1533 	if (!vop_data)
1534 		return -ENODEV;
1535 
1536 	/* Allocate vop struct and its vop_win array */
1537 	alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1538 	vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1539 	if (!vop)
1540 		return -ENOMEM;
1541 
1542 	vop->dev = dev;
1543 	vop->data = vop_data;
1544 	vop->drm_dev = drm_dev;
1545 	dev_set_drvdata(dev, vop);
1546 
1547 	vop_win_init(vop);
1548 
1549 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1550 	vop->len = resource_size(res);
1551 	vop->regs = devm_ioremap_resource(dev, res);
1552 	if (IS_ERR(vop->regs))
1553 		return PTR_ERR(vop->regs);
1554 
1555 	vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1556 	if (!vop->regsbak)
1557 		return -ENOMEM;
1558 
1559 	irq = platform_get_irq(pdev, 0);
1560 	if (irq < 0) {
1561 		dev_err(dev, "cannot find irq for vop\n");
1562 		return irq;
1563 	}
1564 	vop->irq = (unsigned int)irq;
1565 
1566 	spin_lock_init(&vop->reg_lock);
1567 	spin_lock_init(&vop->irq_lock);
1568 
1569 	mutex_init(&vop->vsync_mutex);
1570 
1571 	ret = devm_request_irq(dev, vop->irq, vop_isr,
1572 			       IRQF_SHARED, dev_name(dev), vop);
1573 	if (ret)
1574 		return ret;
1575 
1576 	/* IRQ is initially disabled; it gets enabled in power_on */
1577 	disable_irq(vop->irq);
1578 
1579 	ret = vop_create_crtc(vop);
1580 	if (ret)
1581 		goto err_enable_irq;
1582 
1583 	pm_runtime_enable(&pdev->dev);
1584 
1585 	ret = vop_initial(vop);
1586 	if (ret < 0) {
1587 		dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1588 		goto err_disable_pm_runtime;
1589 	}
1590 
1591 	return 0;
1592 
1593 err_disable_pm_runtime:
1594 	pm_runtime_disable(&pdev->dev);
1595 	vop_destroy_crtc(vop);
1596 err_enable_irq:
1597 	enable_irq(vop->irq); /* To balance out the disable_irq above */
1598 	return ret;
1599 }
1600 
1601 static void vop_unbind(struct device *dev, struct device *master, void *data)
1602 {
1603 	struct vop *vop = dev_get_drvdata(dev);
1604 
1605 	pm_runtime_disable(dev);
1606 	vop_destroy_crtc(vop);
1607 
1608 	clk_unprepare(vop->aclk);
1609 	clk_unprepare(vop->hclk);
1610 	clk_unprepare(vop->dclk);
1611 }
1612 
1613 const struct component_ops vop_component_ops = {
1614 	.bind = vop_bind,
1615 	.unbind = vop_unbind,
1616 };
1617 EXPORT_SYMBOL_GPL(vop_component_ops);
1618