1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_uapi.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_flip_work.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_gem_atomic_helper.h> 27 #include <drm/drm_gem_framebuffer_helper.h> 28 #include <drm/drm_plane_helper.h> 29 #include <drm/drm_probe_helper.h> 30 #include <drm/drm_self_refresh_helper.h> 31 #include <drm/drm_vblank.h> 32 33 #ifdef CONFIG_DRM_ANALOGIX_DP 34 #include <drm/bridge/analogix_dp.h> 35 #endif 36 37 #include "rockchip_drm_drv.h" 38 #include "rockchip_drm_gem.h" 39 #include "rockchip_drm_fb.h" 40 #include "rockchip_drm_vop.h" 41 #include "rockchip_rgb.h" 42 43 #define VOP_WIN_SET(vop, win, name, v) \ 44 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 45 #define VOP_SCL_SET(vop, win, name, v) \ 46 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 47 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 48 vop_reg_set(vop, &win->phy->scl->ext->name, \ 49 win->base, ~0, v, #name) 50 51 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 52 do { \ 53 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 54 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 55 } while (0) 56 57 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 58 do { \ 59 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 60 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 61 } while (0) 62 63 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 64 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 65 66 #define VOP_REG_SET(vop, group, name, v) \ 67 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 68 69 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 70 do { \ 71 int i, reg = 0, mask = 0; \ 72 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 73 if (vop->data->intr->intrs[i] & type) { \ 74 reg |= (v) << i; \ 75 mask |= 1 << i; \ 76 } \ 77 } \ 78 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 79 } while (0) 80 #define VOP_INTR_GET_TYPE(vop, name, type) \ 81 vop_get_intr_type(vop, &vop->data->intr->name, type) 82 83 #define VOP_WIN_GET(vop, win, name) \ 84 vop_read_reg(vop, win->base, &win->phy->name) 85 86 #define VOP_WIN_HAS_REG(win, name) \ 87 (!!(win->phy->name.mask)) 88 89 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 91 92 #define VOP_WIN_TO_INDEX(vop_win) \ 93 ((vop_win) - (vop_win)->vop->win) 94 95 #define VOP_AFBC_SET(vop, name, v) \ 96 do { \ 97 if ((vop)->data->afbc) \ 98 vop_reg_set((vop), &(vop)->data->afbc->name, \ 99 0, ~0, v, #name); \ 100 } while (0) 101 102 #define to_vop(x) container_of(x, struct vop, crtc) 103 #define to_vop_win(x) container_of(x, struct vop_win, base) 104 105 #define AFBC_FMT_RGB565 0x0 106 #define AFBC_FMT_U8U8U8U8 0x5 107 #define AFBC_FMT_U8U8U8 0x4 108 109 #define AFBC_TILE_16x16 BIT(4) 110 111 /* 112 * The coefficients of the following matrix are all fixed points. 113 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 114 * They are all represented in two's complement. 115 */ 116 static const uint32_t bt601_yuv2rgb[] = { 117 0x4A8, 0x0, 0x662, 118 0x4A8, 0x1E6F, 0x1CBF, 119 0x4A8, 0x812, 0x0, 120 0x321168, 0x0877CF, 0x2EB127 121 }; 122 123 enum vop_pending { 124 VOP_PENDING_FB_UNREF, 125 }; 126 127 struct vop_win { 128 struct drm_plane base; 129 const struct vop_win_data *data; 130 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 131 struct vop *vop; 132 }; 133 134 struct rockchip_rgb; 135 struct vop { 136 struct drm_crtc crtc; 137 struct device *dev; 138 struct drm_device *drm_dev; 139 bool is_enabled; 140 141 struct completion dsp_hold_completion; 142 unsigned int win_enabled; 143 144 /* protected by dev->event_lock */ 145 struct drm_pending_vblank_event *event; 146 147 struct drm_flip_work fb_unref_work; 148 unsigned long pending; 149 150 struct completion line_flag_completion; 151 152 const struct vop_data *data; 153 154 uint32_t *regsbak; 155 void __iomem *regs; 156 void __iomem *lut_regs; 157 158 /* physical map length of vop register */ 159 uint32_t len; 160 161 /* one time only one process allowed to config the register */ 162 spinlock_t reg_lock; 163 /* lock vop irq reg */ 164 spinlock_t irq_lock; 165 /* protects crtc enable/disable */ 166 struct mutex vop_lock; 167 168 unsigned int irq; 169 170 /* vop AHP clk */ 171 struct clk *hclk; 172 /* vop dclk */ 173 struct clk *dclk; 174 /* vop share memory frequency */ 175 struct clk *aclk; 176 177 /* vop dclk reset */ 178 struct reset_control *dclk_rst; 179 180 /* optional internal rgb encoder */ 181 struct rockchip_rgb *rgb; 182 183 struct vop_win win[]; 184 }; 185 186 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 187 { 188 writel(v, vop->regs + offset); 189 vop->regsbak[offset >> 2] = v; 190 } 191 192 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 193 { 194 return readl(vop->regs + offset); 195 } 196 197 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 198 const struct vop_reg *reg) 199 { 200 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 201 } 202 203 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 204 uint32_t _offset, uint32_t _mask, uint32_t v, 205 const char *reg_name) 206 { 207 int offset, mask, shift; 208 209 if (!reg || !reg->mask) { 210 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 211 return; 212 } 213 214 offset = reg->offset + _offset; 215 mask = reg->mask & _mask; 216 shift = reg->shift; 217 218 if (reg->write_mask) { 219 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 220 } else { 221 uint32_t cached_val = vop->regsbak[offset >> 2]; 222 223 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 224 vop->regsbak[offset >> 2] = v; 225 } 226 227 if (reg->relaxed) 228 writel_relaxed(v, vop->regs + offset); 229 else 230 writel(v, vop->regs + offset); 231 } 232 233 static inline uint32_t vop_get_intr_type(struct vop *vop, 234 const struct vop_reg *reg, int type) 235 { 236 uint32_t i, ret = 0; 237 uint32_t regs = vop_read_reg(vop, 0, reg); 238 239 for (i = 0; i < vop->data->intr->nintrs; i++) { 240 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 241 ret |= vop->data->intr->intrs[i]; 242 } 243 244 return ret; 245 } 246 247 static inline void vop_cfg_done(struct vop *vop) 248 { 249 VOP_REG_SET(vop, common, cfg_done, 1); 250 } 251 252 static bool has_rb_swapped(uint32_t format) 253 { 254 switch (format) { 255 case DRM_FORMAT_XBGR8888: 256 case DRM_FORMAT_ABGR8888: 257 case DRM_FORMAT_BGR888: 258 case DRM_FORMAT_BGR565: 259 return true; 260 default: 261 return false; 262 } 263 } 264 265 static enum vop_data_format vop_convert_format(uint32_t format) 266 { 267 switch (format) { 268 case DRM_FORMAT_XRGB8888: 269 case DRM_FORMAT_ARGB8888: 270 case DRM_FORMAT_XBGR8888: 271 case DRM_FORMAT_ABGR8888: 272 return VOP_FMT_ARGB8888; 273 case DRM_FORMAT_RGB888: 274 case DRM_FORMAT_BGR888: 275 return VOP_FMT_RGB888; 276 case DRM_FORMAT_RGB565: 277 case DRM_FORMAT_BGR565: 278 return VOP_FMT_RGB565; 279 case DRM_FORMAT_NV12: 280 return VOP_FMT_YUV420SP; 281 case DRM_FORMAT_NV16: 282 return VOP_FMT_YUV422SP; 283 case DRM_FORMAT_NV24: 284 return VOP_FMT_YUV444SP; 285 default: 286 DRM_ERROR("unsupported format[%08x]\n", format); 287 return -EINVAL; 288 } 289 } 290 291 static int vop_convert_afbc_format(uint32_t format) 292 { 293 switch (format) { 294 case DRM_FORMAT_XRGB8888: 295 case DRM_FORMAT_ARGB8888: 296 case DRM_FORMAT_XBGR8888: 297 case DRM_FORMAT_ABGR8888: 298 return AFBC_FMT_U8U8U8U8; 299 case DRM_FORMAT_RGB888: 300 case DRM_FORMAT_BGR888: 301 return AFBC_FMT_U8U8U8; 302 case DRM_FORMAT_RGB565: 303 case DRM_FORMAT_BGR565: 304 return AFBC_FMT_RGB565; 305 /* either of the below should not be reachable */ 306 default: 307 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format); 308 return -EINVAL; 309 } 310 311 return -EINVAL; 312 } 313 314 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 315 uint32_t dst, bool is_horizontal, 316 int vsu_mode, int *vskiplines) 317 { 318 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 319 320 if (vskiplines) 321 *vskiplines = 0; 322 323 if (is_horizontal) { 324 if (mode == SCALE_UP) 325 val = GET_SCL_FT_BIC(src, dst); 326 else if (mode == SCALE_DOWN) 327 val = GET_SCL_FT_BILI_DN(src, dst); 328 } else { 329 if (mode == SCALE_UP) { 330 if (vsu_mode == SCALE_UP_BIL) 331 val = GET_SCL_FT_BILI_UP(src, dst); 332 else 333 val = GET_SCL_FT_BIC(src, dst); 334 } else if (mode == SCALE_DOWN) { 335 if (vskiplines) { 336 *vskiplines = scl_get_vskiplines(src, dst); 337 val = scl_get_bili_dn_vskip(src, dst, 338 *vskiplines); 339 } else { 340 val = GET_SCL_FT_BILI_DN(src, dst); 341 } 342 } 343 } 344 345 return val; 346 } 347 348 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 349 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 350 uint32_t dst_h, const struct drm_format_info *info) 351 { 352 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 353 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 354 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 355 bool is_yuv = false; 356 uint16_t cbcr_src_w = src_w / info->hsub; 357 uint16_t cbcr_src_h = src_h / info->vsub; 358 uint16_t vsu_mode; 359 uint16_t lb_mode; 360 uint32_t val; 361 int vskiplines; 362 363 if (info->is_yuv) 364 is_yuv = true; 365 366 if (dst_w > 3840) { 367 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 368 return; 369 } 370 371 if (!win->phy->scl->ext) { 372 VOP_SCL_SET(vop, win, scale_yrgb_x, 373 scl_cal_scale2(src_w, dst_w)); 374 VOP_SCL_SET(vop, win, scale_yrgb_y, 375 scl_cal_scale2(src_h, dst_h)); 376 if (is_yuv) { 377 VOP_SCL_SET(vop, win, scale_cbcr_x, 378 scl_cal_scale2(cbcr_src_w, dst_w)); 379 VOP_SCL_SET(vop, win, scale_cbcr_y, 380 scl_cal_scale2(cbcr_src_h, dst_h)); 381 } 382 return; 383 } 384 385 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 386 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 387 388 if (is_yuv) { 389 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 390 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 391 if (cbcr_hor_scl_mode == SCALE_DOWN) 392 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 393 else 394 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 395 } else { 396 if (yrgb_hor_scl_mode == SCALE_DOWN) 397 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 398 else 399 lb_mode = scl_vop_cal_lb_mode(src_w, false); 400 } 401 402 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 403 if (lb_mode == LB_RGB_3840X2) { 404 if (yrgb_ver_scl_mode != SCALE_NONE) { 405 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 406 return; 407 } 408 if (cbcr_ver_scl_mode != SCALE_NONE) { 409 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 410 return; 411 } 412 vsu_mode = SCALE_UP_BIL; 413 } else if (lb_mode == LB_RGB_2560X4) { 414 vsu_mode = SCALE_UP_BIL; 415 } else { 416 vsu_mode = SCALE_UP_BIC; 417 } 418 419 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 420 true, 0, NULL); 421 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 422 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 423 false, vsu_mode, &vskiplines); 424 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 425 426 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 427 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 428 429 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 430 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 431 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 432 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 433 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 434 if (is_yuv) { 435 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 436 dst_w, true, 0, NULL); 437 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 438 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 439 dst_h, false, vsu_mode, &vskiplines); 440 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 441 442 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 443 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 444 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 445 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 446 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 447 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 448 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 449 } 450 } 451 452 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 453 { 454 unsigned long flags; 455 456 if (WARN_ON(!vop->is_enabled)) 457 return; 458 459 spin_lock_irqsave(&vop->irq_lock, flags); 460 461 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 462 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 463 464 spin_unlock_irqrestore(&vop->irq_lock, flags); 465 } 466 467 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 468 { 469 unsigned long flags; 470 471 if (WARN_ON(!vop->is_enabled)) 472 return; 473 474 spin_lock_irqsave(&vop->irq_lock, flags); 475 476 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 477 478 spin_unlock_irqrestore(&vop->irq_lock, flags); 479 } 480 481 /* 482 * (1) each frame starts at the start of the Vsync pulse which is signaled by 483 * the "FRAME_SYNC" interrupt. 484 * (2) the active data region of each frame ends at dsp_vact_end 485 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 486 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 487 * 488 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 489 * Interrupts 490 * LINE_FLAG -------------------------------+ 491 * FRAME_SYNC ----+ | 492 * | | 493 * v v 494 * | Vsync | Vbp | Vactive | Vfp | 495 * ^ ^ ^ ^ 496 * | | | | 497 * | | | | 498 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 499 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 500 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 501 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 502 */ 503 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 504 { 505 uint32_t line_flag_irq; 506 unsigned long flags; 507 508 spin_lock_irqsave(&vop->irq_lock, flags); 509 510 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 511 512 spin_unlock_irqrestore(&vop->irq_lock, flags); 513 514 return !!line_flag_irq; 515 } 516 517 static void vop_line_flag_irq_enable(struct vop *vop) 518 { 519 unsigned long flags; 520 521 if (WARN_ON(!vop->is_enabled)) 522 return; 523 524 spin_lock_irqsave(&vop->irq_lock, flags); 525 526 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 527 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 528 529 spin_unlock_irqrestore(&vop->irq_lock, flags); 530 } 531 532 static void vop_line_flag_irq_disable(struct vop *vop) 533 { 534 unsigned long flags; 535 536 if (WARN_ON(!vop->is_enabled)) 537 return; 538 539 spin_lock_irqsave(&vop->irq_lock, flags); 540 541 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 542 543 spin_unlock_irqrestore(&vop->irq_lock, flags); 544 } 545 546 static int vop_core_clks_enable(struct vop *vop) 547 { 548 int ret; 549 550 ret = clk_enable(vop->hclk); 551 if (ret < 0) 552 return ret; 553 554 ret = clk_enable(vop->aclk); 555 if (ret < 0) 556 goto err_disable_hclk; 557 558 return 0; 559 560 err_disable_hclk: 561 clk_disable(vop->hclk); 562 return ret; 563 } 564 565 static void vop_core_clks_disable(struct vop *vop) 566 { 567 clk_disable(vop->aclk); 568 clk_disable(vop->hclk); 569 } 570 571 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win) 572 { 573 const struct vop_win_data *win = vop_win->data; 574 575 if (win->phy->scl && win->phy->scl->ext) { 576 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 577 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 578 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 579 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 580 } 581 582 VOP_WIN_SET(vop, win, enable, 0); 583 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win)); 584 } 585 586 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) 587 { 588 struct vop *vop = to_vop(crtc); 589 int ret, i; 590 591 ret = pm_runtime_get_sync(vop->dev); 592 if (ret < 0) { 593 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 594 return ret; 595 } 596 597 ret = vop_core_clks_enable(vop); 598 if (WARN_ON(ret < 0)) 599 goto err_put_pm_runtime; 600 601 ret = clk_enable(vop->dclk); 602 if (WARN_ON(ret < 0)) 603 goto err_disable_core; 604 605 /* 606 * Slave iommu shares power, irq and clock with vop. It was associated 607 * automatically with this master device via common driver code. 608 * Now that we have enabled the clock we attach it to the shared drm 609 * mapping. 610 */ 611 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 612 if (ret) { 613 DRM_DEV_ERROR(vop->dev, 614 "failed to attach dma mapping, %d\n", ret); 615 goto err_disable_dclk; 616 } 617 618 spin_lock(&vop->reg_lock); 619 for (i = 0; i < vop->len; i += 4) 620 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 621 622 /* 623 * We need to make sure that all windows are disabled before we 624 * enable the crtc. Otherwise we might try to scan from a destroyed 625 * buffer later. 626 * 627 * In the case of enable-after-PSR, we don't need to worry about this 628 * case since the buffer is guaranteed to be valid and disabling the 629 * window will result in screen glitches on PSR exit. 630 */ 631 if (!old_state || !old_state->self_refresh_active) { 632 for (i = 0; i < vop->data->win_size; i++) { 633 struct vop_win *vop_win = &vop->win[i]; 634 635 vop_win_disable(vop, vop_win); 636 } 637 } 638 639 if (vop->data->afbc) { 640 struct rockchip_crtc_state *s; 641 /* 642 * Disable AFBC and forget there was a vop window with AFBC 643 */ 644 VOP_AFBC_SET(vop, enable, 0); 645 s = to_rockchip_crtc_state(crtc->state); 646 s->enable_afbc = false; 647 } 648 649 vop_cfg_done(vop); 650 651 spin_unlock(&vop->reg_lock); 652 653 /* 654 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 655 */ 656 vop->is_enabled = true; 657 658 spin_lock(&vop->reg_lock); 659 660 VOP_REG_SET(vop, common, standby, 1); 661 662 spin_unlock(&vop->reg_lock); 663 664 drm_crtc_vblank_on(crtc); 665 666 return 0; 667 668 err_disable_dclk: 669 clk_disable(vop->dclk); 670 err_disable_core: 671 vop_core_clks_disable(vop); 672 err_put_pm_runtime: 673 pm_runtime_put_sync(vop->dev); 674 return ret; 675 } 676 677 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled) 678 { 679 struct vop *vop = to_vop(crtc); 680 int i; 681 682 spin_lock(&vop->reg_lock); 683 684 for (i = 0; i < vop->data->win_size; i++) { 685 struct vop_win *vop_win = &vop->win[i]; 686 const struct vop_win_data *win = vop_win->data; 687 688 VOP_WIN_SET(vop, win, enable, 689 enabled && (vop->win_enabled & BIT(i))); 690 } 691 vop_cfg_done(vop); 692 693 spin_unlock(&vop->reg_lock); 694 } 695 696 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 697 struct drm_atomic_state *state) 698 { 699 struct vop *vop = to_vop(crtc); 700 701 WARN_ON(vop->event); 702 703 if (crtc->state->self_refresh_active) 704 rockchip_drm_set_win_enabled(crtc, false); 705 706 mutex_lock(&vop->vop_lock); 707 708 drm_crtc_vblank_off(crtc); 709 710 if (crtc->state->self_refresh_active) 711 goto out; 712 713 /* 714 * Vop standby will take effect at end of current frame, 715 * if dsp hold valid irq happen, it means standby complete. 716 * 717 * we must wait standby complete when we want to disable aclk, 718 * if not, memory bus maybe dead. 719 */ 720 reinit_completion(&vop->dsp_hold_completion); 721 vop_dsp_hold_valid_irq_enable(vop); 722 723 spin_lock(&vop->reg_lock); 724 725 VOP_REG_SET(vop, common, standby, 1); 726 727 spin_unlock(&vop->reg_lock); 728 729 if (!wait_for_completion_timeout(&vop->dsp_hold_completion, 730 msecs_to_jiffies(200))) 731 WARN(1, "%s: timed out waiting for DSP hold", crtc->name); 732 733 vop_dsp_hold_valid_irq_disable(vop); 734 735 vop->is_enabled = false; 736 737 /* 738 * vop standby complete, so iommu detach is safe. 739 */ 740 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 741 742 clk_disable(vop->dclk); 743 vop_core_clks_disable(vop); 744 pm_runtime_put(vop->dev); 745 746 out: 747 mutex_unlock(&vop->vop_lock); 748 749 if (crtc->state->event && !crtc->state->active) { 750 spin_lock_irq(&crtc->dev->event_lock); 751 drm_crtc_send_vblank_event(crtc, crtc->state->event); 752 spin_unlock_irq(&crtc->dev->event_lock); 753 754 crtc->state->event = NULL; 755 } 756 } 757 758 static void vop_plane_destroy(struct drm_plane *plane) 759 { 760 drm_plane_cleanup(plane); 761 } 762 763 static inline bool rockchip_afbc(u64 modifier) 764 { 765 return modifier == ROCKCHIP_AFBC_MOD; 766 } 767 768 static bool rockchip_mod_supported(struct drm_plane *plane, 769 u32 format, u64 modifier) 770 { 771 if (modifier == DRM_FORMAT_MOD_LINEAR) 772 return true; 773 774 if (!rockchip_afbc(modifier)) { 775 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier); 776 777 return false; 778 } 779 780 return vop_convert_afbc_format(format) >= 0; 781 } 782 783 static int vop_plane_atomic_check(struct drm_plane *plane, 784 struct drm_atomic_state *state) 785 { 786 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 787 plane); 788 struct drm_crtc *crtc = new_plane_state->crtc; 789 struct drm_crtc_state *crtc_state; 790 struct drm_framebuffer *fb = new_plane_state->fb; 791 struct vop_win *vop_win = to_vop_win(plane); 792 const struct vop_win_data *win = vop_win->data; 793 int ret; 794 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 795 DRM_PLANE_HELPER_NO_SCALING; 796 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 797 DRM_PLANE_HELPER_NO_SCALING; 798 799 if (!crtc || WARN_ON(!fb)) 800 return 0; 801 802 crtc_state = drm_atomic_get_existing_crtc_state(state, 803 crtc); 804 if (WARN_ON(!crtc_state)) 805 return -EINVAL; 806 807 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 808 min_scale, max_scale, 809 true, true); 810 if (ret) 811 return ret; 812 813 if (!new_plane_state->visible) 814 return 0; 815 816 ret = vop_convert_format(fb->format->format); 817 if (ret < 0) 818 return ret; 819 820 /* 821 * Src.x1 can be odd when do clip, but yuv plane start point 822 * need align with 2 pixel. 823 */ 824 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) { 825 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 826 return -EINVAL; 827 } 828 829 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) { 830 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 831 return -EINVAL; 832 } 833 834 if (rockchip_afbc(fb->modifier)) { 835 struct vop *vop = to_vop(crtc); 836 837 if (!vop->data->afbc) { 838 DRM_ERROR("vop does not support AFBC\n"); 839 return -EINVAL; 840 } 841 842 ret = vop_convert_afbc_format(fb->format->format); 843 if (ret < 0) 844 return ret; 845 846 if (new_plane_state->src.x1 || new_plane_state->src.y1) { 847 DRM_ERROR("AFBC does not support offset display, xpos=%d, ypos=%d, offset=%d\n", 848 new_plane_state->src.x1, 849 new_plane_state->src.y1, fb->offsets[0]); 850 return -EINVAL; 851 } 852 853 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) { 854 DRM_ERROR("No rotation support in AFBC, rotation=%d\n", 855 new_plane_state->rotation); 856 return -EINVAL; 857 } 858 } 859 860 return 0; 861 } 862 863 static void vop_plane_atomic_disable(struct drm_plane *plane, 864 struct drm_atomic_state *state) 865 { 866 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 867 plane); 868 struct vop_win *vop_win = to_vop_win(plane); 869 struct vop *vop = to_vop(old_state->crtc); 870 871 if (!old_state->crtc) 872 return; 873 874 spin_lock(&vop->reg_lock); 875 876 vop_win_disable(vop, vop_win); 877 878 spin_unlock(&vop->reg_lock); 879 } 880 881 static void vop_plane_atomic_update(struct drm_plane *plane, 882 struct drm_atomic_state *state) 883 { 884 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 885 plane); 886 struct drm_crtc *crtc = new_state->crtc; 887 struct vop_win *vop_win = to_vop_win(plane); 888 const struct vop_win_data *win = vop_win->data; 889 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 890 struct vop *vop = to_vop(new_state->crtc); 891 struct drm_framebuffer *fb = new_state->fb; 892 unsigned int actual_w, actual_h; 893 unsigned int dsp_stx, dsp_sty; 894 uint32_t act_info, dsp_info, dsp_st; 895 struct drm_rect *src = &new_state->src; 896 struct drm_rect *dest = &new_state->dst; 897 struct drm_gem_object *obj, *uv_obj; 898 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 899 unsigned long offset; 900 dma_addr_t dma_addr; 901 uint32_t val; 902 bool rb_swap; 903 int win_index = VOP_WIN_TO_INDEX(vop_win); 904 int format; 905 int is_yuv = fb->format->is_yuv; 906 int i; 907 908 /* 909 * can't update plane when vop is disabled. 910 */ 911 if (WARN_ON(!crtc)) 912 return; 913 914 if (WARN_ON(!vop->is_enabled)) 915 return; 916 917 if (!new_state->visible) { 918 vop_plane_atomic_disable(plane, state); 919 return; 920 } 921 922 obj = fb->obj[0]; 923 rk_obj = to_rockchip_obj(obj); 924 925 actual_w = drm_rect_width(src) >> 16; 926 actual_h = drm_rect_height(src) >> 16; 927 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 928 929 dsp_info = (drm_rect_height(dest) - 1) << 16; 930 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 931 932 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 933 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 934 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 935 936 offset = (src->x1 >> 16) * fb->format->cpp[0]; 937 offset += (src->y1 >> 16) * fb->pitches[0]; 938 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 939 940 /* 941 * For y-mirroring we need to move address 942 * to the beginning of the last line. 943 */ 944 if (new_state->rotation & DRM_MODE_REFLECT_Y) 945 dma_addr += (actual_h - 1) * fb->pitches[0]; 946 947 format = vop_convert_format(fb->format->format); 948 949 spin_lock(&vop->reg_lock); 950 951 if (rockchip_afbc(fb->modifier)) { 952 int afbc_format = vop_convert_afbc_format(fb->format->format); 953 954 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16); 955 VOP_AFBC_SET(vop, hreg_block_split, 0); 956 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win)); 957 VOP_AFBC_SET(vop, hdr_ptr, dma_addr); 958 VOP_AFBC_SET(vop, pic_size, act_info); 959 } 960 961 VOP_WIN_SET(vop, win, format, format); 962 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 963 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 964 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 965 VOP_WIN_SET(vop, win, y_mir_en, 966 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 967 VOP_WIN_SET(vop, win, x_mir_en, 968 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 969 970 if (is_yuv) { 971 int hsub = fb->format->hsub; 972 int vsub = fb->format->vsub; 973 int bpp = fb->format->cpp[1]; 974 975 uv_obj = fb->obj[1]; 976 rk_uv_obj = to_rockchip_obj(uv_obj); 977 978 offset = (src->x1 >> 16) * bpp / hsub; 979 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 980 981 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 982 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 983 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 984 985 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 986 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 987 win_yuv2yuv, 988 y2r_coefficients[i], 989 bt601_yuv2rgb[i]); 990 } 991 } 992 993 if (win->phy->scl) 994 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 995 drm_rect_width(dest), drm_rect_height(dest), 996 fb->format); 997 998 VOP_WIN_SET(vop, win, act_info, act_info); 999 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 1000 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 1001 1002 rb_swap = has_rb_swapped(fb->format->format); 1003 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 1004 1005 /* 1006 * Blending win0 with the background color doesn't seem to work 1007 * correctly. We only get the background color, no matter the contents 1008 * of the win0 framebuffer. However, blending pre-multiplied color 1009 * with the default opaque black default background color is a no-op, 1010 * so we can just disable blending to get the correct result. 1011 */ 1012 if (fb->format->has_alpha && win_index > 0) { 1013 VOP_WIN_SET(vop, win, dst_alpha_ctl, 1014 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 1015 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 1016 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 1017 SRC_BLEND_M0(ALPHA_PER_PIX) | 1018 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 1019 SRC_FACTOR_M0(ALPHA_ONE); 1020 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 1021 1022 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL); 1023 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX); 1024 VOP_WIN_SET(vop, win, alpha_en, 1); 1025 } else { 1026 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 1027 VOP_WIN_SET(vop, win, alpha_en, 0); 1028 } 1029 1030 VOP_WIN_SET(vop, win, enable, 1); 1031 vop->win_enabled |= BIT(win_index); 1032 spin_unlock(&vop->reg_lock); 1033 } 1034 1035 static int vop_plane_atomic_async_check(struct drm_plane *plane, 1036 struct drm_atomic_state *state) 1037 { 1038 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1039 plane); 1040 struct vop_win *vop_win = to_vop_win(plane); 1041 const struct vop_win_data *win = vop_win->data; 1042 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 1043 DRM_PLANE_HELPER_NO_SCALING; 1044 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 1045 DRM_PLANE_HELPER_NO_SCALING; 1046 struct drm_crtc_state *crtc_state; 1047 1048 if (plane != new_plane_state->crtc->cursor) 1049 return -EINVAL; 1050 1051 if (!plane->state) 1052 return -EINVAL; 1053 1054 if (!plane->state->fb) 1055 return -EINVAL; 1056 1057 if (state) 1058 crtc_state = drm_atomic_get_existing_crtc_state(state, 1059 new_plane_state->crtc); 1060 else /* Special case for asynchronous cursor updates. */ 1061 crtc_state = plane->crtc->state; 1062 1063 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 1064 min_scale, max_scale, 1065 true, true); 1066 } 1067 1068 static void vop_plane_atomic_async_update(struct drm_plane *plane, 1069 struct drm_atomic_state *state) 1070 { 1071 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1072 plane); 1073 struct vop *vop = to_vop(plane->state->crtc); 1074 struct drm_framebuffer *old_fb = plane->state->fb; 1075 1076 plane->state->crtc_x = new_state->crtc_x; 1077 plane->state->crtc_y = new_state->crtc_y; 1078 plane->state->crtc_h = new_state->crtc_h; 1079 plane->state->crtc_w = new_state->crtc_w; 1080 plane->state->src_x = new_state->src_x; 1081 plane->state->src_y = new_state->src_y; 1082 plane->state->src_h = new_state->src_h; 1083 plane->state->src_w = new_state->src_w; 1084 swap(plane->state->fb, new_state->fb); 1085 1086 if (vop->is_enabled) { 1087 vop_plane_atomic_update(plane, state); 1088 spin_lock(&vop->reg_lock); 1089 vop_cfg_done(vop); 1090 spin_unlock(&vop->reg_lock); 1091 1092 /* 1093 * A scanout can still be occurring, so we can't drop the 1094 * reference to the old framebuffer. To solve this we get a 1095 * reference to old_fb and set a worker to release it later. 1096 * FIXME: if we perform 500 async_update calls before the 1097 * vblank, then we can have 500 different framebuffers waiting 1098 * to be released. 1099 */ 1100 if (old_fb && plane->state->fb != old_fb) { 1101 drm_framebuffer_get(old_fb); 1102 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 1103 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 1104 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1105 } 1106 } 1107 } 1108 1109 static const struct drm_plane_helper_funcs plane_helper_funcs = { 1110 .atomic_check = vop_plane_atomic_check, 1111 .atomic_update = vop_plane_atomic_update, 1112 .atomic_disable = vop_plane_atomic_disable, 1113 .atomic_async_check = vop_plane_atomic_async_check, 1114 .atomic_async_update = vop_plane_atomic_async_update, 1115 }; 1116 1117 static const struct drm_plane_funcs vop_plane_funcs = { 1118 .update_plane = drm_atomic_helper_update_plane, 1119 .disable_plane = drm_atomic_helper_disable_plane, 1120 .destroy = vop_plane_destroy, 1121 .reset = drm_atomic_helper_plane_reset, 1122 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1123 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1124 .format_mod_supported = rockchip_mod_supported, 1125 }; 1126 1127 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 1128 { 1129 struct vop *vop = to_vop(crtc); 1130 unsigned long flags; 1131 1132 if (WARN_ON(!vop->is_enabled)) 1133 return -EPERM; 1134 1135 spin_lock_irqsave(&vop->irq_lock, flags); 1136 1137 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 1138 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 1139 1140 spin_unlock_irqrestore(&vop->irq_lock, flags); 1141 1142 return 0; 1143 } 1144 1145 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 1146 { 1147 struct vop *vop = to_vop(crtc); 1148 unsigned long flags; 1149 1150 if (WARN_ON(!vop->is_enabled)) 1151 return; 1152 1153 spin_lock_irqsave(&vop->irq_lock, flags); 1154 1155 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 1156 1157 spin_unlock_irqrestore(&vop->irq_lock, flags); 1158 } 1159 1160 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1161 const struct drm_display_mode *mode, 1162 struct drm_display_mode *adjusted_mode) 1163 { 1164 struct vop *vop = to_vop(crtc); 1165 unsigned long rate; 1166 1167 /* 1168 * Clock craziness. 1169 * 1170 * Key points: 1171 * 1172 * - DRM works in in kHz. 1173 * - Clock framework works in Hz. 1174 * - Rockchip's clock driver picks the clock rate that is the 1175 * same _OR LOWER_ than the one requested. 1176 * 1177 * Action plan: 1178 * 1179 * 1. When DRM gives us a mode, we should add 999 Hz to it. That way 1180 * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to 1181 * make 60000 kHz then the clock framework will actually give us 1182 * the right clock. 1183 * 1184 * NOTE: if the PLL (maybe through a divider) could actually make 1185 * a clock rate 999 Hz higher instead of the one we want then this 1186 * could be a problem. Unfortunately there's not much we can do 1187 * since it's baked into DRM to use kHz. It shouldn't matter in 1188 * practice since Rockchip PLLs are controlled by tables and 1189 * even if there is a divider in the middle I wouldn't expect PLL 1190 * rates in the table that are just a few kHz different. 1191 * 1192 * 2. Get the clock framework to round the rate for us to tell us 1193 * what it will actually make. 1194 * 1195 * 3. Store the rounded up rate so that we don't need to worry about 1196 * this in the actual clk_set_rate(). 1197 */ 1198 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); 1199 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); 1200 1201 return true; 1202 } 1203 1204 static bool vop_dsp_lut_is_enabled(struct vop *vop) 1205 { 1206 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); 1207 } 1208 1209 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) 1210 { 1211 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 1212 unsigned int i; 1213 1214 for (i = 0; i < crtc->gamma_size; i++) { 1215 u32 word; 1216 1217 word = (drm_color_lut_extract(lut[i].red, 10) << 20) | 1218 (drm_color_lut_extract(lut[i].green, 10) << 10) | 1219 drm_color_lut_extract(lut[i].blue, 10); 1220 writel(word, vop->lut_regs + i * 4); 1221 } 1222 } 1223 1224 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, 1225 struct drm_crtc_state *old_state) 1226 { 1227 struct drm_crtc_state *state = crtc->state; 1228 unsigned int idle; 1229 int ret; 1230 1231 if (!vop->lut_regs) 1232 return; 1233 /* 1234 * To disable gamma (gamma_lut is null) or to write 1235 * an update to the LUT, clear dsp_lut_en. 1236 */ 1237 spin_lock(&vop->reg_lock); 1238 VOP_REG_SET(vop, common, dsp_lut_en, 0); 1239 vop_cfg_done(vop); 1240 spin_unlock(&vop->reg_lock); 1241 1242 /* 1243 * In order to write the LUT to the internal memory, 1244 * we need to first make sure the dsp_lut_en bit is cleared. 1245 */ 1246 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, 1247 idle, !idle, 5, 30 * 1000); 1248 if (ret) { 1249 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); 1250 return; 1251 } 1252 1253 if (!state->gamma_lut) 1254 return; 1255 1256 spin_lock(&vop->reg_lock); 1257 vop_crtc_write_gamma_lut(vop, crtc); 1258 VOP_REG_SET(vop, common, dsp_lut_en, 1); 1259 vop_cfg_done(vop); 1260 spin_unlock(&vop->reg_lock); 1261 } 1262 1263 static void vop_crtc_atomic_begin(struct drm_crtc *crtc, 1264 struct drm_atomic_state *state) 1265 { 1266 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1267 crtc); 1268 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1269 crtc); 1270 struct vop *vop = to_vop(crtc); 1271 1272 /* 1273 * Only update GAMMA if the 'active' flag is not changed, 1274 * otherwise it's updated by .atomic_enable. 1275 */ 1276 if (crtc_state->color_mgmt_changed && 1277 !crtc_state->active_changed) 1278 vop_crtc_gamma_set(vop, crtc, old_crtc_state); 1279 } 1280 1281 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1282 struct drm_atomic_state *state) 1283 { 1284 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 1285 crtc); 1286 struct vop *vop = to_vop(crtc); 1287 const struct vop_data *vop_data = vop->data; 1288 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1289 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1290 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1291 u16 hdisplay = adjusted_mode->hdisplay; 1292 u16 htotal = adjusted_mode->htotal; 1293 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1294 u16 hact_end = hact_st + hdisplay; 1295 u16 vdisplay = adjusted_mode->vdisplay; 1296 u16 vtotal = adjusted_mode->vtotal; 1297 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1298 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1299 u16 vact_end = vact_st + vdisplay; 1300 uint32_t pin_pol, val; 1301 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1302 int ret; 1303 1304 if (old_state && old_state->self_refresh_active) { 1305 drm_crtc_vblank_on(crtc); 1306 rockchip_drm_set_win_enabled(crtc, true); 1307 return; 1308 } 1309 1310 /* 1311 * If we have a GAMMA LUT in the state, then let's make sure 1312 * it's updated. We might be coming out of suspend, 1313 * which means the LUT internal memory needs to be re-written. 1314 */ 1315 if (crtc->state->gamma_lut) 1316 vop_crtc_gamma_set(vop, crtc, old_state); 1317 1318 mutex_lock(&vop->vop_lock); 1319 1320 WARN_ON(vop->event); 1321 1322 ret = vop_enable(crtc, old_state); 1323 if (ret) { 1324 mutex_unlock(&vop->vop_lock); 1325 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1326 return; 1327 } 1328 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1329 BIT(HSYNC_POSITIVE) : 0; 1330 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1331 BIT(VSYNC_POSITIVE) : 0; 1332 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1333 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1334 1335 switch (s->output_type) { 1336 case DRM_MODE_CONNECTOR_LVDS: 1337 VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1338 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1339 VOP_REG_SET(vop, output, rgb_en, 1); 1340 break; 1341 case DRM_MODE_CONNECTOR_eDP: 1342 VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1343 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1344 VOP_REG_SET(vop, output, edp_en, 1); 1345 break; 1346 case DRM_MODE_CONNECTOR_HDMIA: 1347 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1348 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1349 VOP_REG_SET(vop, output, hdmi_en, 1); 1350 break; 1351 case DRM_MODE_CONNECTOR_DSI: 1352 VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1353 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1354 VOP_REG_SET(vop, output, mipi_en, 1); 1355 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1356 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1357 break; 1358 case DRM_MODE_CONNECTOR_DisplayPort: 1359 VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1360 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1361 VOP_REG_SET(vop, output, dp_en, 1); 1362 break; 1363 default: 1364 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1365 s->output_type); 1366 } 1367 1368 /* 1369 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1370 */ 1371 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1372 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1373 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1374 1375 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1376 VOP_REG_SET(vop, common, pre_dither_down, 1); 1377 else 1378 VOP_REG_SET(vop, common, pre_dither_down, 0); 1379 1380 if (dither_bpc == 6) { 1381 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1382 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1383 VOP_REG_SET(vop, common, dither_down_en, 1); 1384 } else { 1385 VOP_REG_SET(vop, common, dither_down_en, 0); 1386 } 1387 1388 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1389 1390 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1391 val = hact_st << 16; 1392 val |= hact_end; 1393 VOP_REG_SET(vop, modeset, hact_st_end, val); 1394 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1395 1396 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1397 val = vact_st << 16; 1398 val |= vact_end; 1399 VOP_REG_SET(vop, modeset, vact_st_end, val); 1400 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1401 1402 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1403 1404 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1405 1406 VOP_REG_SET(vop, common, standby, 0); 1407 mutex_unlock(&vop->vop_lock); 1408 } 1409 1410 static bool vop_fs_irq_is_pending(struct vop *vop) 1411 { 1412 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1413 } 1414 1415 static void vop_wait_for_irq_handler(struct vop *vop) 1416 { 1417 bool pending; 1418 int ret; 1419 1420 /* 1421 * Spin until frame start interrupt status bit goes low, which means 1422 * that interrupt handler was invoked and cleared it. The timeout of 1423 * 10 msecs is really too long, but it is just a safety measure if 1424 * something goes really wrong. The wait will only happen in the very 1425 * unlikely case of a vblank happening exactly at the same time and 1426 * shouldn't exceed microseconds range. 1427 */ 1428 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1429 !pending, 0, 10 * 1000); 1430 if (ret) 1431 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1432 1433 synchronize_irq(vop->irq); 1434 } 1435 1436 static int vop_crtc_atomic_check(struct drm_crtc *crtc, 1437 struct drm_atomic_state *state) 1438 { 1439 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1440 crtc); 1441 struct vop *vop = to_vop(crtc); 1442 struct drm_plane *plane; 1443 struct drm_plane_state *plane_state; 1444 struct rockchip_crtc_state *s; 1445 int afbc_planes = 0; 1446 1447 if (vop->lut_regs && crtc_state->color_mgmt_changed && 1448 crtc_state->gamma_lut) { 1449 unsigned int len; 1450 1451 len = drm_color_lut_size(crtc_state->gamma_lut); 1452 if (len != crtc->gamma_size) { 1453 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1454 len, crtc->gamma_size); 1455 return -EINVAL; 1456 } 1457 } 1458 1459 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { 1460 plane_state = 1461 drm_atomic_get_plane_state(crtc_state->state, plane); 1462 if (IS_ERR(plane_state)) { 1463 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n", 1464 plane->name); 1465 return PTR_ERR(plane_state); 1466 } 1467 1468 if (drm_is_afbc(plane_state->fb->modifier)) 1469 ++afbc_planes; 1470 } 1471 1472 if (afbc_planes > 1) { 1473 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes); 1474 return -EINVAL; 1475 } 1476 1477 s = to_rockchip_crtc_state(crtc_state); 1478 s->enable_afbc = afbc_planes > 0; 1479 1480 return 0; 1481 } 1482 1483 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1484 struct drm_atomic_state *state) 1485 { 1486 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1487 crtc); 1488 struct drm_atomic_state *old_state = old_crtc_state->state; 1489 struct drm_plane_state *old_plane_state, *new_plane_state; 1490 struct vop *vop = to_vop(crtc); 1491 struct drm_plane *plane; 1492 struct rockchip_crtc_state *s; 1493 int i; 1494 1495 if (WARN_ON(!vop->is_enabled)) 1496 return; 1497 1498 spin_lock(&vop->reg_lock); 1499 1500 /* Enable AFBC if there is some AFBC window, disable otherwise. */ 1501 s = to_rockchip_crtc_state(crtc->state); 1502 VOP_AFBC_SET(vop, enable, s->enable_afbc); 1503 vop_cfg_done(vop); 1504 1505 spin_unlock(&vop->reg_lock); 1506 1507 /* 1508 * There is a (rather unlikely) possiblity that a vblank interrupt 1509 * fired before we set the cfg_done bit. To avoid spuriously 1510 * signalling flip completion we need to wait for it to finish. 1511 */ 1512 vop_wait_for_irq_handler(vop); 1513 1514 spin_lock_irq(&crtc->dev->event_lock); 1515 if (crtc->state->event) { 1516 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1517 WARN_ON(vop->event); 1518 1519 vop->event = crtc->state->event; 1520 crtc->state->event = NULL; 1521 } 1522 spin_unlock_irq(&crtc->dev->event_lock); 1523 1524 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1525 new_plane_state, i) { 1526 if (!old_plane_state->fb) 1527 continue; 1528 1529 if (old_plane_state->fb == new_plane_state->fb) 1530 continue; 1531 1532 drm_framebuffer_get(old_plane_state->fb); 1533 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1534 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1535 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1536 } 1537 } 1538 1539 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1540 .mode_fixup = vop_crtc_mode_fixup, 1541 .atomic_check = vop_crtc_atomic_check, 1542 .atomic_begin = vop_crtc_atomic_begin, 1543 .atomic_flush = vop_crtc_atomic_flush, 1544 .atomic_enable = vop_crtc_atomic_enable, 1545 .atomic_disable = vop_crtc_atomic_disable, 1546 }; 1547 1548 static void vop_crtc_destroy(struct drm_crtc *crtc) 1549 { 1550 drm_crtc_cleanup(crtc); 1551 } 1552 1553 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1554 { 1555 struct rockchip_crtc_state *rockchip_state; 1556 1557 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1558 if (!rockchip_state) 1559 return NULL; 1560 1561 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1562 return &rockchip_state->base; 1563 } 1564 1565 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1566 struct drm_crtc_state *state) 1567 { 1568 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1569 1570 __drm_atomic_helper_crtc_destroy_state(&s->base); 1571 kfree(s); 1572 } 1573 1574 static void vop_crtc_reset(struct drm_crtc *crtc) 1575 { 1576 struct rockchip_crtc_state *crtc_state = 1577 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1578 1579 if (crtc->state) 1580 vop_crtc_destroy_state(crtc, crtc->state); 1581 1582 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1583 } 1584 1585 #ifdef CONFIG_DRM_ANALOGIX_DP 1586 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1587 { 1588 struct drm_connector *connector; 1589 struct drm_connector_list_iter conn_iter; 1590 1591 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1592 drm_for_each_connector_iter(connector, &conn_iter) { 1593 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1594 drm_connector_list_iter_end(&conn_iter); 1595 return connector; 1596 } 1597 } 1598 drm_connector_list_iter_end(&conn_iter); 1599 1600 return NULL; 1601 } 1602 1603 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1604 const char *source_name) 1605 { 1606 struct vop *vop = to_vop(crtc); 1607 struct drm_connector *connector; 1608 int ret; 1609 1610 connector = vop_get_edp_connector(vop); 1611 if (!connector) 1612 return -EINVAL; 1613 1614 if (source_name && strcmp(source_name, "auto") == 0) 1615 ret = analogix_dp_start_crc(connector); 1616 else if (!source_name) 1617 ret = analogix_dp_stop_crc(connector); 1618 else 1619 ret = -EINVAL; 1620 1621 return ret; 1622 } 1623 1624 static int 1625 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1626 size_t *values_cnt) 1627 { 1628 if (source_name && strcmp(source_name, "auto") != 0) 1629 return -EINVAL; 1630 1631 *values_cnt = 3; 1632 return 0; 1633 } 1634 1635 #else 1636 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1637 const char *source_name) 1638 { 1639 return -ENODEV; 1640 } 1641 1642 static int 1643 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1644 size_t *values_cnt) 1645 { 1646 return -ENODEV; 1647 } 1648 #endif 1649 1650 static const struct drm_crtc_funcs vop_crtc_funcs = { 1651 .set_config = drm_atomic_helper_set_config, 1652 .page_flip = drm_atomic_helper_page_flip, 1653 .destroy = vop_crtc_destroy, 1654 .reset = vop_crtc_reset, 1655 .atomic_duplicate_state = vop_crtc_duplicate_state, 1656 .atomic_destroy_state = vop_crtc_destroy_state, 1657 .enable_vblank = vop_crtc_enable_vblank, 1658 .disable_vblank = vop_crtc_disable_vblank, 1659 .set_crc_source = vop_crtc_set_crc_source, 1660 .verify_crc_source = vop_crtc_verify_crc_source, 1661 }; 1662 1663 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1664 { 1665 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1666 struct drm_framebuffer *fb = val; 1667 1668 drm_crtc_vblank_put(&vop->crtc); 1669 drm_framebuffer_put(fb); 1670 } 1671 1672 static void vop_handle_vblank(struct vop *vop) 1673 { 1674 struct drm_device *drm = vop->drm_dev; 1675 struct drm_crtc *crtc = &vop->crtc; 1676 1677 spin_lock(&drm->event_lock); 1678 if (vop->event) { 1679 drm_crtc_send_vblank_event(crtc, vop->event); 1680 drm_crtc_vblank_put(crtc); 1681 vop->event = NULL; 1682 } 1683 spin_unlock(&drm->event_lock); 1684 1685 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1686 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1687 } 1688 1689 static irqreturn_t vop_isr(int irq, void *data) 1690 { 1691 struct vop *vop = data; 1692 struct drm_crtc *crtc = &vop->crtc; 1693 uint32_t active_irqs; 1694 int ret = IRQ_NONE; 1695 1696 /* 1697 * The irq is shared with the iommu. If the runtime-pm state of the 1698 * vop-device is disabled the irq has to be targeted at the iommu. 1699 */ 1700 if (!pm_runtime_get_if_in_use(vop->dev)) 1701 return IRQ_NONE; 1702 1703 if (vop_core_clks_enable(vop)) { 1704 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1705 goto out; 1706 } 1707 1708 /* 1709 * interrupt register has interrupt status, enable and clear bits, we 1710 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1711 */ 1712 spin_lock(&vop->irq_lock); 1713 1714 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1715 /* Clear all active interrupt sources */ 1716 if (active_irqs) 1717 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1718 1719 spin_unlock(&vop->irq_lock); 1720 1721 /* This is expected for vop iommu irqs, since the irq is shared */ 1722 if (!active_irqs) 1723 goto out_disable; 1724 1725 if (active_irqs & DSP_HOLD_VALID_INTR) { 1726 complete(&vop->dsp_hold_completion); 1727 active_irqs &= ~DSP_HOLD_VALID_INTR; 1728 ret = IRQ_HANDLED; 1729 } 1730 1731 if (active_irqs & LINE_FLAG_INTR) { 1732 complete(&vop->line_flag_completion); 1733 active_irqs &= ~LINE_FLAG_INTR; 1734 ret = IRQ_HANDLED; 1735 } 1736 1737 if (active_irqs & FS_INTR) { 1738 drm_crtc_handle_vblank(crtc); 1739 vop_handle_vblank(vop); 1740 active_irqs &= ~FS_INTR; 1741 ret = IRQ_HANDLED; 1742 } 1743 1744 /* Unhandled irqs are spurious. */ 1745 if (active_irqs) 1746 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1747 active_irqs); 1748 1749 out_disable: 1750 vop_core_clks_disable(vop); 1751 out: 1752 pm_runtime_put(vop->dev); 1753 return ret; 1754 } 1755 1756 static void vop_plane_add_properties(struct drm_plane *plane, 1757 const struct vop_win_data *win_data) 1758 { 1759 unsigned int flags = 0; 1760 1761 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1762 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1763 if (flags) 1764 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1765 DRM_MODE_ROTATE_0 | flags); 1766 } 1767 1768 static int vop_create_crtc(struct vop *vop) 1769 { 1770 const struct vop_data *vop_data = vop->data; 1771 struct device *dev = vop->dev; 1772 struct drm_device *drm_dev = vop->drm_dev; 1773 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1774 struct drm_crtc *crtc = &vop->crtc; 1775 struct device_node *port; 1776 int ret; 1777 int i; 1778 1779 /* 1780 * Create drm_plane for primary and cursor planes first, since we need 1781 * to pass them to drm_crtc_init_with_planes, which sets the 1782 * "possible_crtcs" to the newly initialized crtc. 1783 */ 1784 for (i = 0; i < vop_data->win_size; i++) { 1785 struct vop_win *vop_win = &vop->win[i]; 1786 const struct vop_win_data *win_data = vop_win->data; 1787 1788 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1789 win_data->type != DRM_PLANE_TYPE_CURSOR) 1790 continue; 1791 1792 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1793 0, &vop_plane_funcs, 1794 win_data->phy->data_formats, 1795 win_data->phy->nformats, 1796 win_data->phy->format_modifiers, 1797 win_data->type, NULL); 1798 if (ret) { 1799 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1800 ret); 1801 goto err_cleanup_planes; 1802 } 1803 1804 plane = &vop_win->base; 1805 drm_plane_helper_add(plane, &plane_helper_funcs); 1806 vop_plane_add_properties(plane, win_data); 1807 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1808 primary = plane; 1809 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1810 cursor = plane; 1811 } 1812 1813 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1814 &vop_crtc_funcs, NULL); 1815 if (ret) 1816 goto err_cleanup_planes; 1817 1818 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1819 if (vop->lut_regs) { 1820 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size); 1821 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); 1822 } 1823 1824 /* 1825 * Create drm_planes for overlay windows with possible_crtcs restricted 1826 * to the newly created crtc. 1827 */ 1828 for (i = 0; i < vop_data->win_size; i++) { 1829 struct vop_win *vop_win = &vop->win[i]; 1830 const struct vop_win_data *win_data = vop_win->data; 1831 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1832 1833 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1834 continue; 1835 1836 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1837 possible_crtcs, 1838 &vop_plane_funcs, 1839 win_data->phy->data_formats, 1840 win_data->phy->nformats, 1841 win_data->phy->format_modifiers, 1842 win_data->type, NULL); 1843 if (ret) { 1844 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1845 ret); 1846 goto err_cleanup_crtc; 1847 } 1848 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1849 vop_plane_add_properties(&vop_win->base, win_data); 1850 } 1851 1852 port = of_get_child_by_name(dev->of_node, "port"); 1853 if (!port) { 1854 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1855 dev->of_node); 1856 ret = -ENOENT; 1857 goto err_cleanup_crtc; 1858 } 1859 1860 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1861 vop_fb_unref_worker); 1862 1863 init_completion(&vop->dsp_hold_completion); 1864 init_completion(&vop->line_flag_completion); 1865 crtc->port = port; 1866 1867 ret = drm_self_refresh_helper_init(crtc); 1868 if (ret) 1869 DRM_DEV_DEBUG_KMS(vop->dev, 1870 "Failed to init %s with SR helpers %d, ignoring\n", 1871 crtc->name, ret); 1872 1873 return 0; 1874 1875 err_cleanup_crtc: 1876 drm_crtc_cleanup(crtc); 1877 err_cleanup_planes: 1878 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1879 head) 1880 drm_plane_cleanup(plane); 1881 return ret; 1882 } 1883 1884 static void vop_destroy_crtc(struct vop *vop) 1885 { 1886 struct drm_crtc *crtc = &vop->crtc; 1887 struct drm_device *drm_dev = vop->drm_dev; 1888 struct drm_plane *plane, *tmp; 1889 1890 drm_self_refresh_helper_cleanup(crtc); 1891 1892 of_node_put(crtc->port); 1893 1894 /* 1895 * We need to cleanup the planes now. Why? 1896 * 1897 * The planes are "&vop->win[i].base". That means the memory is 1898 * all part of the big "struct vop" chunk of memory. That memory 1899 * was devm allocated and associated with this component. We need to 1900 * free it ourselves before vop_unbind() finishes. 1901 */ 1902 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1903 head) 1904 vop_plane_destroy(plane); 1905 1906 /* 1907 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1908 * references the CRTC. 1909 */ 1910 drm_crtc_cleanup(crtc); 1911 drm_flip_work_cleanup(&vop->fb_unref_work); 1912 } 1913 1914 static int vop_initial(struct vop *vop) 1915 { 1916 struct reset_control *ahb_rst; 1917 int i, ret; 1918 1919 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1920 if (IS_ERR(vop->hclk)) { 1921 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1922 return PTR_ERR(vop->hclk); 1923 } 1924 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1925 if (IS_ERR(vop->aclk)) { 1926 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1927 return PTR_ERR(vop->aclk); 1928 } 1929 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1930 if (IS_ERR(vop->dclk)) { 1931 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1932 return PTR_ERR(vop->dclk); 1933 } 1934 1935 ret = pm_runtime_get_sync(vop->dev); 1936 if (ret < 0) { 1937 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1938 return ret; 1939 } 1940 1941 ret = clk_prepare(vop->dclk); 1942 if (ret < 0) { 1943 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1944 goto err_put_pm_runtime; 1945 } 1946 1947 /* Enable both the hclk and aclk to setup the vop */ 1948 ret = clk_prepare_enable(vop->hclk); 1949 if (ret < 0) { 1950 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1951 goto err_unprepare_dclk; 1952 } 1953 1954 ret = clk_prepare_enable(vop->aclk); 1955 if (ret < 0) { 1956 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1957 goto err_disable_hclk; 1958 } 1959 1960 /* 1961 * do hclk_reset, reset all vop registers. 1962 */ 1963 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1964 if (IS_ERR(ahb_rst)) { 1965 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1966 ret = PTR_ERR(ahb_rst); 1967 goto err_disable_aclk; 1968 } 1969 reset_control_assert(ahb_rst); 1970 usleep_range(10, 20); 1971 reset_control_deassert(ahb_rst); 1972 1973 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1974 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1975 1976 for (i = 0; i < vop->len; i += sizeof(u32)) 1977 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1978 1979 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1980 VOP_REG_SET(vop, common, dsp_blank, 0); 1981 1982 for (i = 0; i < vop->data->win_size; i++) { 1983 struct vop_win *vop_win = &vop->win[i]; 1984 const struct vop_win_data *win = vop_win->data; 1985 int channel = i * 2 + 1; 1986 1987 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1988 vop_win_disable(vop, vop_win); 1989 VOP_WIN_SET(vop, win, gate, 1); 1990 } 1991 1992 vop_cfg_done(vop); 1993 1994 /* 1995 * do dclk_reset, let all config take affect. 1996 */ 1997 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1998 if (IS_ERR(vop->dclk_rst)) { 1999 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 2000 ret = PTR_ERR(vop->dclk_rst); 2001 goto err_disable_aclk; 2002 } 2003 reset_control_assert(vop->dclk_rst); 2004 usleep_range(10, 20); 2005 reset_control_deassert(vop->dclk_rst); 2006 2007 clk_disable(vop->hclk); 2008 clk_disable(vop->aclk); 2009 2010 vop->is_enabled = false; 2011 2012 pm_runtime_put_sync(vop->dev); 2013 2014 return 0; 2015 2016 err_disable_aclk: 2017 clk_disable_unprepare(vop->aclk); 2018 err_disable_hclk: 2019 clk_disable_unprepare(vop->hclk); 2020 err_unprepare_dclk: 2021 clk_unprepare(vop->dclk); 2022 err_put_pm_runtime: 2023 pm_runtime_put_sync(vop->dev); 2024 return ret; 2025 } 2026 2027 /* 2028 * Initialize the vop->win array elements. 2029 */ 2030 static void vop_win_init(struct vop *vop) 2031 { 2032 const struct vop_data *vop_data = vop->data; 2033 unsigned int i; 2034 2035 for (i = 0; i < vop_data->win_size; i++) { 2036 struct vop_win *vop_win = &vop->win[i]; 2037 const struct vop_win_data *win_data = &vop_data->win[i]; 2038 2039 vop_win->data = win_data; 2040 vop_win->vop = vop; 2041 2042 if (vop_data->win_yuv2yuv) 2043 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 2044 } 2045 } 2046 2047 /** 2048 * rockchip_drm_wait_vact_end 2049 * @crtc: CRTC to enable line flag 2050 * @mstimeout: millisecond for timeout 2051 * 2052 * Wait for vact_end line flag irq or timeout. 2053 * 2054 * Returns: 2055 * Zero on success, negative errno on failure. 2056 */ 2057 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 2058 { 2059 struct vop *vop = to_vop(crtc); 2060 unsigned long jiffies_left; 2061 int ret = 0; 2062 2063 if (!crtc || !vop->is_enabled) 2064 return -ENODEV; 2065 2066 mutex_lock(&vop->vop_lock); 2067 if (mstimeout <= 0) { 2068 ret = -EINVAL; 2069 goto out; 2070 } 2071 2072 if (vop_line_flag_irq_is_enabled(vop)) { 2073 ret = -EBUSY; 2074 goto out; 2075 } 2076 2077 reinit_completion(&vop->line_flag_completion); 2078 vop_line_flag_irq_enable(vop); 2079 2080 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 2081 msecs_to_jiffies(mstimeout)); 2082 vop_line_flag_irq_disable(vop); 2083 2084 if (jiffies_left == 0) { 2085 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 2086 ret = -ETIMEDOUT; 2087 goto out; 2088 } 2089 2090 out: 2091 mutex_unlock(&vop->vop_lock); 2092 return ret; 2093 } 2094 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 2095 2096 static int vop_bind(struct device *dev, struct device *master, void *data) 2097 { 2098 struct platform_device *pdev = to_platform_device(dev); 2099 const struct vop_data *vop_data; 2100 struct drm_device *drm_dev = data; 2101 struct vop *vop; 2102 struct resource *res; 2103 int ret, irq; 2104 2105 vop_data = of_device_get_match_data(dev); 2106 if (!vop_data) 2107 return -ENODEV; 2108 2109 /* Allocate vop struct and its vop_win array */ 2110 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 2111 GFP_KERNEL); 2112 if (!vop) 2113 return -ENOMEM; 2114 2115 vop->dev = dev; 2116 vop->data = vop_data; 2117 vop->drm_dev = drm_dev; 2118 dev_set_drvdata(dev, vop); 2119 2120 vop_win_init(vop); 2121 2122 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2123 vop->len = resource_size(res); 2124 vop->regs = devm_ioremap_resource(dev, res); 2125 if (IS_ERR(vop->regs)) 2126 return PTR_ERR(vop->regs); 2127 2128 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2129 if (res) { 2130 if (!vop_data->lut_size) { 2131 DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); 2132 return -EINVAL; 2133 } 2134 vop->lut_regs = devm_ioremap_resource(dev, res); 2135 if (IS_ERR(vop->lut_regs)) 2136 return PTR_ERR(vop->lut_regs); 2137 } 2138 2139 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 2140 if (!vop->regsbak) 2141 return -ENOMEM; 2142 2143 irq = platform_get_irq(pdev, 0); 2144 if (irq < 0) { 2145 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 2146 return irq; 2147 } 2148 vop->irq = (unsigned int)irq; 2149 2150 spin_lock_init(&vop->reg_lock); 2151 spin_lock_init(&vop->irq_lock); 2152 mutex_init(&vop->vop_lock); 2153 2154 ret = vop_create_crtc(vop); 2155 if (ret) 2156 return ret; 2157 2158 pm_runtime_enable(&pdev->dev); 2159 2160 ret = vop_initial(vop); 2161 if (ret < 0) { 2162 DRM_DEV_ERROR(&pdev->dev, 2163 "cannot initial vop dev - err %d\n", ret); 2164 goto err_disable_pm_runtime; 2165 } 2166 2167 ret = devm_request_irq(dev, vop->irq, vop_isr, 2168 IRQF_SHARED, dev_name(dev), vop); 2169 if (ret) 2170 goto err_disable_pm_runtime; 2171 2172 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 2173 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 2174 if (IS_ERR(vop->rgb)) { 2175 ret = PTR_ERR(vop->rgb); 2176 goto err_disable_pm_runtime; 2177 } 2178 } 2179 2180 return 0; 2181 2182 err_disable_pm_runtime: 2183 pm_runtime_disable(&pdev->dev); 2184 vop_destroy_crtc(vop); 2185 return ret; 2186 } 2187 2188 static void vop_unbind(struct device *dev, struct device *master, void *data) 2189 { 2190 struct vop *vop = dev_get_drvdata(dev); 2191 2192 if (vop->rgb) 2193 rockchip_rgb_fini(vop->rgb); 2194 2195 pm_runtime_disable(dev); 2196 vop_destroy_crtc(vop); 2197 2198 clk_unprepare(vop->aclk); 2199 clk_unprepare(vop->hclk); 2200 clk_unprepare(vop->dclk); 2201 } 2202 2203 const struct component_ops vop_component_ops = { 2204 .bind = vop_bind, 2205 .unbind = vop_unbind, 2206 }; 2207 EXPORT_SYMBOL_GPL(vop_component_ops); 2208