1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author:Mark Yao <mark.yao@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/overflow.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_uapi.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_flip_work.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_gem_framebuffer_helper.h> 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_probe_helper.h> 29 #include <drm/drm_vblank.h> 30 31 #ifdef CONFIG_DRM_ANALOGIX_DP 32 #include <drm/bridge/analogix_dp.h> 33 #endif 34 35 #include "rockchip_drm_drv.h" 36 #include "rockchip_drm_gem.h" 37 #include "rockchip_drm_fb.h" 38 #include "rockchip_drm_psr.h" 39 #include "rockchip_drm_vop.h" 40 #include "rockchip_rgb.h" 41 42 #define VOP_WIN_SET(vop, win, name, v) \ 43 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) 44 #define VOP_SCL_SET(vop, win, name, v) \ 45 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) 46 #define VOP_SCL_SET_EXT(vop, win, name, v) \ 47 vop_reg_set(vop, &win->phy->scl->ext->name, \ 48 win->base, ~0, v, #name) 49 50 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \ 51 do { \ 52 if (win_yuv2yuv && win_yuv2yuv->name.mask) \ 53 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \ 54 } while (0) 55 56 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \ 57 do { \ 58 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ 59 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \ 60 } while (0) 61 62 #define VOP_INTR_SET_MASK(vop, name, mask, v) \ 63 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) 64 65 #define VOP_REG_SET(vop, group, name, v) \ 66 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) 67 68 #define VOP_INTR_SET_TYPE(vop, name, type, v) \ 69 do { \ 70 int i, reg = 0, mask = 0; \ 71 for (i = 0; i < vop->data->intr->nintrs; i++) { \ 72 if (vop->data->intr->intrs[i] & type) { \ 73 reg |= (v) << i; \ 74 mask |= 1 << i; \ 75 } \ 76 } \ 77 VOP_INTR_SET_MASK(vop, name, mask, reg); \ 78 } while (0) 79 #define VOP_INTR_GET_TYPE(vop, name, type) \ 80 vop_get_intr_type(vop, &vop->data->intr->name, type) 81 82 #define VOP_WIN_GET(vop, win, name) \ 83 vop_read_reg(vop, win->offset, win->phy->name) 84 85 #define VOP_WIN_HAS_REG(win, name) \ 86 (!!(win->phy->name.mask)) 87 88 #define VOP_WIN_GET_YRGBADDR(vop, win) \ 89 vop_readl(vop, win->base + win->phy->yrgb_mst.offset) 90 91 #define VOP_WIN_TO_INDEX(vop_win) \ 92 ((vop_win) - (vop_win)->vop->win) 93 94 #define to_vop(x) container_of(x, struct vop, crtc) 95 #define to_vop_win(x) container_of(x, struct vop_win, base) 96 97 /* 98 * The coefficients of the following matrix are all fixed points. 99 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets. 100 * They are all represented in two's complement. 101 */ 102 static const uint32_t bt601_yuv2rgb[] = { 103 0x4A8, 0x0, 0x662, 104 0x4A8, 0x1E6F, 0x1CBF, 105 0x4A8, 0x812, 0x0, 106 0x321168, 0x0877CF, 0x2EB127 107 }; 108 109 enum vop_pending { 110 VOP_PENDING_FB_UNREF, 111 }; 112 113 struct vop_win { 114 struct drm_plane base; 115 const struct vop_win_data *data; 116 const struct vop_win_yuv2yuv_data *yuv2yuv_data; 117 struct vop *vop; 118 }; 119 120 struct rockchip_rgb; 121 struct vop { 122 struct drm_crtc crtc; 123 struct device *dev; 124 struct drm_device *drm_dev; 125 bool is_enabled; 126 127 struct completion dsp_hold_completion; 128 129 /* protected by dev->event_lock */ 130 struct drm_pending_vblank_event *event; 131 132 struct drm_flip_work fb_unref_work; 133 unsigned long pending; 134 135 struct completion line_flag_completion; 136 137 const struct vop_data *data; 138 139 uint32_t *regsbak; 140 void __iomem *regs; 141 142 /* physical map length of vop register */ 143 uint32_t len; 144 145 /* one time only one process allowed to config the register */ 146 spinlock_t reg_lock; 147 /* lock vop irq reg */ 148 spinlock_t irq_lock; 149 /* protects crtc enable/disable */ 150 struct mutex vop_lock; 151 152 unsigned int irq; 153 154 /* vop AHP clk */ 155 struct clk *hclk; 156 /* vop dclk */ 157 struct clk *dclk; 158 /* vop share memory frequency */ 159 struct clk *aclk; 160 161 /* vop dclk reset */ 162 struct reset_control *dclk_rst; 163 164 /* optional internal rgb encoder */ 165 struct rockchip_rgb *rgb; 166 167 struct vop_win win[]; 168 }; 169 170 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 171 { 172 writel(v, vop->regs + offset); 173 vop->regsbak[offset >> 2] = v; 174 } 175 176 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 177 { 178 return readl(vop->regs + offset); 179 } 180 181 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 182 const struct vop_reg *reg) 183 { 184 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 185 } 186 187 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, 188 uint32_t _offset, uint32_t _mask, uint32_t v, 189 const char *reg_name) 190 { 191 int offset, mask, shift; 192 193 if (!reg || !reg->mask) { 194 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); 195 return; 196 } 197 198 offset = reg->offset + _offset; 199 mask = reg->mask & _mask; 200 shift = reg->shift; 201 202 if (reg->write_mask) { 203 v = ((v << shift) & 0xffff) | (mask << (shift + 16)); 204 } else { 205 uint32_t cached_val = vop->regsbak[offset >> 2]; 206 207 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 208 vop->regsbak[offset >> 2] = v; 209 } 210 211 if (reg->relaxed) 212 writel_relaxed(v, vop->regs + offset); 213 else 214 writel(v, vop->regs + offset); 215 } 216 217 static inline uint32_t vop_get_intr_type(struct vop *vop, 218 const struct vop_reg *reg, int type) 219 { 220 uint32_t i, ret = 0; 221 uint32_t regs = vop_read_reg(vop, 0, reg); 222 223 for (i = 0; i < vop->data->intr->nintrs; i++) { 224 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) 225 ret |= vop->data->intr->intrs[i]; 226 } 227 228 return ret; 229 } 230 231 static inline void vop_cfg_done(struct vop *vop) 232 { 233 VOP_REG_SET(vop, common, cfg_done, 1); 234 } 235 236 static bool has_rb_swapped(uint32_t format) 237 { 238 switch (format) { 239 case DRM_FORMAT_XBGR8888: 240 case DRM_FORMAT_ABGR8888: 241 case DRM_FORMAT_BGR888: 242 case DRM_FORMAT_BGR565: 243 return true; 244 default: 245 return false; 246 } 247 } 248 249 static enum vop_data_format vop_convert_format(uint32_t format) 250 { 251 switch (format) { 252 case DRM_FORMAT_XRGB8888: 253 case DRM_FORMAT_ARGB8888: 254 case DRM_FORMAT_XBGR8888: 255 case DRM_FORMAT_ABGR8888: 256 return VOP_FMT_ARGB8888; 257 case DRM_FORMAT_RGB888: 258 case DRM_FORMAT_BGR888: 259 return VOP_FMT_RGB888; 260 case DRM_FORMAT_RGB565: 261 case DRM_FORMAT_BGR565: 262 return VOP_FMT_RGB565; 263 case DRM_FORMAT_NV12: 264 return VOP_FMT_YUV420SP; 265 case DRM_FORMAT_NV16: 266 return VOP_FMT_YUV422SP; 267 case DRM_FORMAT_NV24: 268 return VOP_FMT_YUV444SP; 269 default: 270 DRM_ERROR("unsupported format[%08x]\n", format); 271 return -EINVAL; 272 } 273 } 274 275 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 276 uint32_t dst, bool is_horizontal, 277 int vsu_mode, int *vskiplines) 278 { 279 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 280 281 if (vskiplines) 282 *vskiplines = 0; 283 284 if (is_horizontal) { 285 if (mode == SCALE_UP) 286 val = GET_SCL_FT_BIC(src, dst); 287 else if (mode == SCALE_DOWN) 288 val = GET_SCL_FT_BILI_DN(src, dst); 289 } else { 290 if (mode == SCALE_UP) { 291 if (vsu_mode == SCALE_UP_BIL) 292 val = GET_SCL_FT_BILI_UP(src, dst); 293 else 294 val = GET_SCL_FT_BIC(src, dst); 295 } else if (mode == SCALE_DOWN) { 296 if (vskiplines) { 297 *vskiplines = scl_get_vskiplines(src, dst); 298 val = scl_get_bili_dn_vskip(src, dst, 299 *vskiplines); 300 } else { 301 val = GET_SCL_FT_BILI_DN(src, dst); 302 } 303 } 304 } 305 306 return val; 307 } 308 309 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, 310 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 311 uint32_t dst_h, const struct drm_format_info *info) 312 { 313 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 314 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 315 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 316 bool is_yuv = false; 317 uint16_t cbcr_src_w = src_w / info->hsub; 318 uint16_t cbcr_src_h = src_h / info->vsub; 319 uint16_t vsu_mode; 320 uint16_t lb_mode; 321 uint32_t val; 322 int vskiplines; 323 324 if (info->is_yuv) 325 is_yuv = true; 326 327 if (dst_w > 3840) { 328 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n"); 329 return; 330 } 331 332 if (!win->phy->scl->ext) { 333 VOP_SCL_SET(vop, win, scale_yrgb_x, 334 scl_cal_scale2(src_w, dst_w)); 335 VOP_SCL_SET(vop, win, scale_yrgb_y, 336 scl_cal_scale2(src_h, dst_h)); 337 if (is_yuv) { 338 VOP_SCL_SET(vop, win, scale_cbcr_x, 339 scl_cal_scale2(cbcr_src_w, dst_w)); 340 VOP_SCL_SET(vop, win, scale_cbcr_y, 341 scl_cal_scale2(cbcr_src_h, dst_h)); 342 } 343 return; 344 } 345 346 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 347 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 348 349 if (is_yuv) { 350 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 351 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 352 if (cbcr_hor_scl_mode == SCALE_DOWN) 353 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 354 else 355 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 356 } else { 357 if (yrgb_hor_scl_mode == SCALE_DOWN) 358 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 359 else 360 lb_mode = scl_vop_cal_lb_mode(src_w, false); 361 } 362 363 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); 364 if (lb_mode == LB_RGB_3840X2) { 365 if (yrgb_ver_scl_mode != SCALE_NONE) { 366 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n"); 367 return; 368 } 369 if (cbcr_ver_scl_mode != SCALE_NONE) { 370 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n"); 371 return; 372 } 373 vsu_mode = SCALE_UP_BIL; 374 } else if (lb_mode == LB_RGB_2560X4) { 375 vsu_mode = SCALE_UP_BIL; 376 } else { 377 vsu_mode = SCALE_UP_BIC; 378 } 379 380 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 381 true, 0, NULL); 382 VOP_SCL_SET(vop, win, scale_yrgb_x, val); 383 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 384 false, vsu_mode, &vskiplines); 385 VOP_SCL_SET(vop, win, scale_yrgb_y, val); 386 387 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); 388 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); 389 390 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 391 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 392 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); 393 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); 394 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); 395 if (is_yuv) { 396 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 397 dst_w, true, 0, NULL); 398 VOP_SCL_SET(vop, win, scale_cbcr_x, val); 399 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 400 dst_h, false, vsu_mode, &vskiplines); 401 VOP_SCL_SET(vop, win, scale_cbcr_y, val); 402 403 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); 404 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); 405 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 406 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 407 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); 408 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); 409 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); 410 } 411 } 412 413 static void vop_dsp_hold_valid_irq_enable(struct vop *vop) 414 { 415 unsigned long flags; 416 417 if (WARN_ON(!vop->is_enabled)) 418 return; 419 420 spin_lock_irqsave(&vop->irq_lock, flags); 421 422 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1); 423 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); 424 425 spin_unlock_irqrestore(&vop->irq_lock, flags); 426 } 427 428 static void vop_dsp_hold_valid_irq_disable(struct vop *vop) 429 { 430 unsigned long flags; 431 432 if (WARN_ON(!vop->is_enabled)) 433 return; 434 435 spin_lock_irqsave(&vop->irq_lock, flags); 436 437 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); 438 439 spin_unlock_irqrestore(&vop->irq_lock, flags); 440 } 441 442 /* 443 * (1) each frame starts at the start of the Vsync pulse which is signaled by 444 * the "FRAME_SYNC" interrupt. 445 * (2) the active data region of each frame ends at dsp_vact_end 446 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num, 447 * to get "LINE_FLAG" interrupt at the end of the active on screen data. 448 * 449 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end 450 * Interrupts 451 * LINE_FLAG -------------------------------+ 452 * FRAME_SYNC ----+ | 453 * | | 454 * v v 455 * | Vsync | Vbp | Vactive | Vfp | 456 * ^ ^ ^ ^ 457 * | | | | 458 * | | | | 459 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END 460 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END 461 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END 462 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END 463 */ 464 static bool vop_line_flag_irq_is_enabled(struct vop *vop) 465 { 466 uint32_t line_flag_irq; 467 unsigned long flags; 468 469 spin_lock_irqsave(&vop->irq_lock, flags); 470 471 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR); 472 473 spin_unlock_irqrestore(&vop->irq_lock, flags); 474 475 return !!line_flag_irq; 476 } 477 478 static void vop_line_flag_irq_enable(struct vop *vop) 479 { 480 unsigned long flags; 481 482 if (WARN_ON(!vop->is_enabled)) 483 return; 484 485 spin_lock_irqsave(&vop->irq_lock, flags); 486 487 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1); 488 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1); 489 490 spin_unlock_irqrestore(&vop->irq_lock, flags); 491 } 492 493 static void vop_line_flag_irq_disable(struct vop *vop) 494 { 495 unsigned long flags; 496 497 if (WARN_ON(!vop->is_enabled)) 498 return; 499 500 spin_lock_irqsave(&vop->irq_lock, flags); 501 502 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0); 503 504 spin_unlock_irqrestore(&vop->irq_lock, flags); 505 } 506 507 static int vop_core_clks_enable(struct vop *vop) 508 { 509 int ret; 510 511 ret = clk_enable(vop->hclk); 512 if (ret < 0) 513 return ret; 514 515 ret = clk_enable(vop->aclk); 516 if (ret < 0) 517 goto err_disable_hclk; 518 519 return 0; 520 521 err_disable_hclk: 522 clk_disable(vop->hclk); 523 return ret; 524 } 525 526 static void vop_core_clks_disable(struct vop *vop) 527 { 528 clk_disable(vop->aclk); 529 clk_disable(vop->hclk); 530 } 531 532 static void vop_win_disable(struct vop *vop, const struct vop_win_data *win) 533 { 534 if (win->phy->scl && win->phy->scl->ext) { 535 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE); 536 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE); 537 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE); 538 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE); 539 } 540 541 VOP_WIN_SET(vop, win, enable, 0); 542 } 543 544 static int vop_enable(struct drm_crtc *crtc) 545 { 546 struct vop *vop = to_vop(crtc); 547 int ret, i; 548 549 ret = pm_runtime_get_sync(vop->dev); 550 if (ret < 0) { 551 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 552 return ret; 553 } 554 555 ret = vop_core_clks_enable(vop); 556 if (WARN_ON(ret < 0)) 557 goto err_put_pm_runtime; 558 559 ret = clk_enable(vop->dclk); 560 if (WARN_ON(ret < 0)) 561 goto err_disable_core; 562 563 /* 564 * Slave iommu shares power, irq and clock with vop. It was associated 565 * automatically with this master device via common driver code. 566 * Now that we have enabled the clock we attach it to the shared drm 567 * mapping. 568 */ 569 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev); 570 if (ret) { 571 DRM_DEV_ERROR(vop->dev, 572 "failed to attach dma mapping, %d\n", ret); 573 goto err_disable_dclk; 574 } 575 576 spin_lock(&vop->reg_lock); 577 for (i = 0; i < vop->len; i += 4) 578 writel_relaxed(vop->regsbak[i / 4], vop->regs + i); 579 580 /* 581 * We need to make sure that all windows are disabled before we 582 * enable the crtc. Otherwise we might try to scan from a destroyed 583 * buffer later. 584 */ 585 for (i = 0; i < vop->data->win_size; i++) { 586 struct vop_win *vop_win = &vop->win[i]; 587 const struct vop_win_data *win = vop_win->data; 588 589 vop_win_disable(vop, win); 590 } 591 spin_unlock(&vop->reg_lock); 592 593 vop_cfg_done(vop); 594 595 /* 596 * At here, vop clock & iommu is enable, R/W vop regs would be safe. 597 */ 598 vop->is_enabled = true; 599 600 spin_lock(&vop->reg_lock); 601 602 VOP_REG_SET(vop, common, standby, 1); 603 604 spin_unlock(&vop->reg_lock); 605 606 drm_crtc_vblank_on(crtc); 607 608 return 0; 609 610 err_disable_dclk: 611 clk_disable(vop->dclk); 612 err_disable_core: 613 vop_core_clks_disable(vop); 614 err_put_pm_runtime: 615 pm_runtime_put_sync(vop->dev); 616 return ret; 617 } 618 619 static void vop_crtc_atomic_disable(struct drm_crtc *crtc, 620 struct drm_crtc_state *old_state) 621 { 622 struct vop *vop = to_vop(crtc); 623 624 WARN_ON(vop->event); 625 626 mutex_lock(&vop->vop_lock); 627 drm_crtc_vblank_off(crtc); 628 629 /* 630 * Vop standby will take effect at end of current frame, 631 * if dsp hold valid irq happen, it means standby complete. 632 * 633 * we must wait standby complete when we want to disable aclk, 634 * if not, memory bus maybe dead. 635 */ 636 reinit_completion(&vop->dsp_hold_completion); 637 vop_dsp_hold_valid_irq_enable(vop); 638 639 spin_lock(&vop->reg_lock); 640 641 VOP_REG_SET(vop, common, standby, 1); 642 643 spin_unlock(&vop->reg_lock); 644 645 wait_for_completion(&vop->dsp_hold_completion); 646 647 vop_dsp_hold_valid_irq_disable(vop); 648 649 vop->is_enabled = false; 650 651 /* 652 * vop standby complete, so iommu detach is safe. 653 */ 654 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); 655 656 clk_disable(vop->dclk); 657 vop_core_clks_disable(vop); 658 pm_runtime_put(vop->dev); 659 mutex_unlock(&vop->vop_lock); 660 661 if (crtc->state->event && !crtc->state->active) { 662 spin_lock_irq(&crtc->dev->event_lock); 663 drm_crtc_send_vblank_event(crtc, crtc->state->event); 664 spin_unlock_irq(&crtc->dev->event_lock); 665 666 crtc->state->event = NULL; 667 } 668 } 669 670 static void vop_plane_destroy(struct drm_plane *plane) 671 { 672 drm_plane_cleanup(plane); 673 } 674 675 static int vop_plane_atomic_check(struct drm_plane *plane, 676 struct drm_plane_state *state) 677 { 678 struct drm_crtc *crtc = state->crtc; 679 struct drm_crtc_state *crtc_state; 680 struct drm_framebuffer *fb = state->fb; 681 struct vop_win *vop_win = to_vop_win(plane); 682 const struct vop_win_data *win = vop_win->data; 683 int ret; 684 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 685 DRM_PLANE_HELPER_NO_SCALING; 686 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 687 DRM_PLANE_HELPER_NO_SCALING; 688 689 if (!crtc || !fb) 690 return 0; 691 692 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 693 if (WARN_ON(!crtc_state)) 694 return -EINVAL; 695 696 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 697 min_scale, max_scale, 698 true, true); 699 if (ret) 700 return ret; 701 702 if (!state->visible) 703 return 0; 704 705 ret = vop_convert_format(fb->format->format); 706 if (ret < 0) 707 return ret; 708 709 /* 710 * Src.x1 can be odd when do clip, but yuv plane start point 711 * need align with 2 pixel. 712 */ 713 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) { 714 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n"); 715 return -EINVAL; 716 } 717 718 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) { 719 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n"); 720 return -EINVAL; 721 } 722 723 return 0; 724 } 725 726 static void vop_plane_atomic_disable(struct drm_plane *plane, 727 struct drm_plane_state *old_state) 728 { 729 struct vop_win *vop_win = to_vop_win(plane); 730 const struct vop_win_data *win = vop_win->data; 731 struct vop *vop = to_vop(old_state->crtc); 732 733 if (!old_state->crtc) 734 return; 735 736 spin_lock(&vop->reg_lock); 737 738 vop_win_disable(vop, win); 739 740 spin_unlock(&vop->reg_lock); 741 } 742 743 static void vop_plane_atomic_update(struct drm_plane *plane, 744 struct drm_plane_state *old_state) 745 { 746 struct drm_plane_state *state = plane->state; 747 struct drm_crtc *crtc = state->crtc; 748 struct vop_win *vop_win = to_vop_win(plane); 749 const struct vop_win_data *win = vop_win->data; 750 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data; 751 struct vop *vop = to_vop(state->crtc); 752 struct drm_framebuffer *fb = state->fb; 753 unsigned int actual_w, actual_h; 754 unsigned int dsp_stx, dsp_sty; 755 uint32_t act_info, dsp_info, dsp_st; 756 struct drm_rect *src = &state->src; 757 struct drm_rect *dest = &state->dst; 758 struct drm_gem_object *obj, *uv_obj; 759 struct rockchip_gem_object *rk_obj, *rk_uv_obj; 760 unsigned long offset; 761 dma_addr_t dma_addr; 762 uint32_t val; 763 bool rb_swap; 764 int win_index = VOP_WIN_TO_INDEX(vop_win); 765 int format; 766 int is_yuv = fb->format->is_yuv; 767 int i; 768 769 /* 770 * can't update plane when vop is disabled. 771 */ 772 if (WARN_ON(!crtc)) 773 return; 774 775 if (WARN_ON(!vop->is_enabled)) 776 return; 777 778 if (!state->visible) { 779 vop_plane_atomic_disable(plane, old_state); 780 return; 781 } 782 783 obj = fb->obj[0]; 784 rk_obj = to_rockchip_obj(obj); 785 786 actual_w = drm_rect_width(src) >> 16; 787 actual_h = drm_rect_height(src) >> 16; 788 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); 789 790 dsp_info = (drm_rect_height(dest) - 1) << 16; 791 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff; 792 793 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start; 794 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; 795 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 796 797 offset = (src->x1 >> 16) * fb->format->cpp[0]; 798 offset += (src->y1 >> 16) * fb->pitches[0]; 799 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; 800 801 /* 802 * For y-mirroring we need to move address 803 * to the beginning of the last line. 804 */ 805 if (state->rotation & DRM_MODE_REFLECT_Y) 806 dma_addr += (actual_h - 1) * fb->pitches[0]; 807 808 format = vop_convert_format(fb->format->format); 809 810 spin_lock(&vop->reg_lock); 811 812 VOP_WIN_SET(vop, win, format, format); 813 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); 814 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); 815 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); 816 VOP_WIN_SET(vop, win, y_mir_en, 817 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0); 818 VOP_WIN_SET(vop, win, x_mir_en, 819 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0); 820 821 if (is_yuv) { 822 int hsub = fb->format->hsub; 823 int vsub = fb->format->vsub; 824 int bpp = fb->format->cpp[1]; 825 826 uv_obj = fb->obj[1]; 827 rk_uv_obj = to_rockchip_obj(uv_obj); 828 829 offset = (src->x1 >> 16) * bpp / hsub; 830 offset += (src->y1 >> 16) * fb->pitches[1] / vsub; 831 832 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; 833 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); 834 VOP_WIN_SET(vop, win, uv_mst, dma_addr); 835 836 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { 837 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, 838 win_yuv2yuv, 839 y2r_coefficients[i], 840 bt601_yuv2rgb[i]); 841 } 842 } 843 844 if (win->phy->scl) 845 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h, 846 drm_rect_width(dest), drm_rect_height(dest), 847 fb->format); 848 849 VOP_WIN_SET(vop, win, act_info, act_info); 850 VOP_WIN_SET(vop, win, dsp_info, dsp_info); 851 VOP_WIN_SET(vop, win, dsp_st, dsp_st); 852 853 rb_swap = has_rb_swapped(fb->format->format); 854 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 855 856 /* 857 * Blending win0 with the background color doesn't seem to work 858 * correctly. We only get the background color, no matter the contents 859 * of the win0 framebuffer. However, blending pre-multiplied color 860 * with the default opaque black default background color is a no-op, 861 * so we can just disable blending to get the correct result. 862 */ 863 if (fb->format->has_alpha && win_index > 0) { 864 VOP_WIN_SET(vop, win, dst_alpha_ctl, 865 DST_FACTOR_M0(ALPHA_SRC_INVERSE)); 866 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) | 867 SRC_ALPHA_M0(ALPHA_STRAIGHT) | 868 SRC_BLEND_M0(ALPHA_PER_PIX) | 869 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) | 870 SRC_FACTOR_M0(ALPHA_ONE); 871 VOP_WIN_SET(vop, win, src_alpha_ctl, val); 872 } else { 873 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0)); 874 } 875 876 VOP_WIN_SET(vop, win, enable, 1); 877 spin_unlock(&vop->reg_lock); 878 } 879 880 static int vop_plane_atomic_async_check(struct drm_plane *plane, 881 struct drm_plane_state *state) 882 { 883 struct vop_win *vop_win = to_vop_win(plane); 884 const struct vop_win_data *win = vop_win->data; 885 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) : 886 DRM_PLANE_HELPER_NO_SCALING; 887 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : 888 DRM_PLANE_HELPER_NO_SCALING; 889 struct drm_crtc_state *crtc_state; 890 891 if (plane != state->crtc->cursor) 892 return -EINVAL; 893 894 if (!plane->state) 895 return -EINVAL; 896 897 if (!plane->state->fb) 898 return -EINVAL; 899 900 if (state->state) 901 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 902 state->crtc); 903 else /* Special case for asynchronous cursor updates. */ 904 crtc_state = plane->crtc->state; 905 906 return drm_atomic_helper_check_plane_state(plane->state, crtc_state, 907 min_scale, max_scale, 908 true, true); 909 } 910 911 static void vop_plane_atomic_async_update(struct drm_plane *plane, 912 struct drm_plane_state *new_state) 913 { 914 struct vop *vop = to_vop(plane->state->crtc); 915 struct drm_framebuffer *old_fb = plane->state->fb; 916 917 plane->state->crtc_x = new_state->crtc_x; 918 plane->state->crtc_y = new_state->crtc_y; 919 plane->state->crtc_h = new_state->crtc_h; 920 plane->state->crtc_w = new_state->crtc_w; 921 plane->state->src_x = new_state->src_x; 922 plane->state->src_y = new_state->src_y; 923 plane->state->src_h = new_state->src_h; 924 plane->state->src_w = new_state->src_w; 925 swap(plane->state->fb, new_state->fb); 926 927 if (vop->is_enabled) { 928 rockchip_drm_psr_inhibit_get_state(new_state->state); 929 vop_plane_atomic_update(plane, plane->state); 930 spin_lock(&vop->reg_lock); 931 vop_cfg_done(vop); 932 spin_unlock(&vop->reg_lock); 933 rockchip_drm_psr_inhibit_put_state(new_state->state); 934 935 /* 936 * A scanout can still be occurring, so we can't drop the 937 * reference to the old framebuffer. To solve this we get a 938 * reference to old_fb and set a worker to release it later. 939 * FIXME: if we perform 500 async_update calls before the 940 * vblank, then we can have 500 different framebuffers waiting 941 * to be released. 942 */ 943 if (old_fb && plane->state->fb != old_fb) { 944 drm_framebuffer_get(old_fb); 945 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0); 946 drm_flip_work_queue(&vop->fb_unref_work, old_fb); 947 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 948 } 949 } 950 } 951 952 static const struct drm_plane_helper_funcs plane_helper_funcs = { 953 .atomic_check = vop_plane_atomic_check, 954 .atomic_update = vop_plane_atomic_update, 955 .atomic_disable = vop_plane_atomic_disable, 956 .atomic_async_check = vop_plane_atomic_async_check, 957 .atomic_async_update = vop_plane_atomic_async_update, 958 .prepare_fb = drm_gem_fb_prepare_fb, 959 }; 960 961 static const struct drm_plane_funcs vop_plane_funcs = { 962 .update_plane = drm_atomic_helper_update_plane, 963 .disable_plane = drm_atomic_helper_disable_plane, 964 .destroy = vop_plane_destroy, 965 .reset = drm_atomic_helper_plane_reset, 966 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 967 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 968 }; 969 970 static int vop_crtc_enable_vblank(struct drm_crtc *crtc) 971 { 972 struct vop *vop = to_vop(crtc); 973 unsigned long flags; 974 975 if (WARN_ON(!vop->is_enabled)) 976 return -EPERM; 977 978 spin_lock_irqsave(&vop->irq_lock, flags); 979 980 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1); 981 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); 982 983 spin_unlock_irqrestore(&vop->irq_lock, flags); 984 985 return 0; 986 } 987 988 static void vop_crtc_disable_vblank(struct drm_crtc *crtc) 989 { 990 struct vop *vop = to_vop(crtc); 991 unsigned long flags; 992 993 if (WARN_ON(!vop->is_enabled)) 994 return; 995 996 spin_lock_irqsave(&vop->irq_lock, flags); 997 998 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); 999 1000 spin_unlock_irqrestore(&vop->irq_lock, flags); 1001 } 1002 1003 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, 1004 const struct drm_display_mode *mode, 1005 struct drm_display_mode *adjusted_mode) 1006 { 1007 struct vop *vop = to_vop(crtc); 1008 1009 adjusted_mode->clock = 1010 DIV_ROUND_UP(clk_round_rate(vop->dclk, 1011 adjusted_mode->clock * 1000), 1000); 1012 1013 return true; 1014 } 1015 1016 static void vop_crtc_atomic_enable(struct drm_crtc *crtc, 1017 struct drm_crtc_state *old_state) 1018 { 1019 struct vop *vop = to_vop(crtc); 1020 const struct vop_data *vop_data = vop->data; 1021 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state); 1022 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1023 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start; 1024 u16 hdisplay = adjusted_mode->hdisplay; 1025 u16 htotal = adjusted_mode->htotal; 1026 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start; 1027 u16 hact_end = hact_st + hdisplay; 1028 u16 vdisplay = adjusted_mode->vdisplay; 1029 u16 vtotal = adjusted_mode->vtotal; 1030 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start; 1031 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start; 1032 u16 vact_end = vact_st + vdisplay; 1033 uint32_t pin_pol, val; 1034 int dither_bpc = s->output_bpc ? s->output_bpc : 10; 1035 int ret; 1036 1037 mutex_lock(&vop->vop_lock); 1038 1039 WARN_ON(vop->event); 1040 1041 ret = vop_enable(crtc); 1042 if (ret) { 1043 mutex_unlock(&vop->vop_lock); 1044 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1045 return; 1046 } 1047 1048 pin_pol = BIT(DCLK_INVERT); 1049 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1050 BIT(HSYNC_POSITIVE) : 0; 1051 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1052 BIT(VSYNC_POSITIVE) : 0; 1053 VOP_REG_SET(vop, output, pin_pol, pin_pol); 1054 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0); 1055 1056 switch (s->output_type) { 1057 case DRM_MODE_CONNECTOR_LVDS: 1058 VOP_REG_SET(vop, output, rgb_en, 1); 1059 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1060 break; 1061 case DRM_MODE_CONNECTOR_eDP: 1062 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1063 VOP_REG_SET(vop, output, edp_en, 1); 1064 break; 1065 case DRM_MODE_CONNECTOR_HDMIA: 1066 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1067 VOP_REG_SET(vop, output, hdmi_en, 1); 1068 break; 1069 case DRM_MODE_CONNECTOR_DSI: 1070 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1071 VOP_REG_SET(vop, output, mipi_en, 1); 1072 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1073 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1074 break; 1075 case DRM_MODE_CONNECTOR_DisplayPort: 1076 pin_pol &= ~BIT(DCLK_INVERT); 1077 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1078 VOP_REG_SET(vop, output, dp_en, 1); 1079 break; 1080 default: 1081 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", 1082 s->output_type); 1083 } 1084 1085 /* 1086 * if vop is not support RGB10 output, need force RGB10 to RGB888. 1087 */ 1088 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1089 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) 1090 s->output_mode = ROCKCHIP_OUT_MODE_P888; 1091 1092 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) 1093 VOP_REG_SET(vop, common, pre_dither_down, 1); 1094 else 1095 VOP_REG_SET(vop, common, pre_dither_down, 0); 1096 1097 if (dither_bpc == 6) { 1098 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO); 1099 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666); 1100 VOP_REG_SET(vop, common, dither_down_en, 1); 1101 } else { 1102 VOP_REG_SET(vop, common, dither_down_en, 0); 1103 } 1104 1105 VOP_REG_SET(vop, common, out_mode, s->output_mode); 1106 1107 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); 1108 val = hact_st << 16; 1109 val |= hact_end; 1110 VOP_REG_SET(vop, modeset, hact_st_end, val); 1111 VOP_REG_SET(vop, modeset, hpost_st_end, val); 1112 1113 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); 1114 val = vact_st << 16; 1115 val |= vact_end; 1116 VOP_REG_SET(vop, modeset, vact_st_end, val); 1117 VOP_REG_SET(vop, modeset, vpost_st_end, val); 1118 1119 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end); 1120 1121 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); 1122 1123 VOP_REG_SET(vop, common, standby, 0); 1124 mutex_unlock(&vop->vop_lock); 1125 } 1126 1127 static bool vop_fs_irq_is_pending(struct vop *vop) 1128 { 1129 return VOP_INTR_GET_TYPE(vop, status, FS_INTR); 1130 } 1131 1132 static void vop_wait_for_irq_handler(struct vop *vop) 1133 { 1134 bool pending; 1135 int ret; 1136 1137 /* 1138 * Spin until frame start interrupt status bit goes low, which means 1139 * that interrupt handler was invoked and cleared it. The timeout of 1140 * 10 msecs is really too long, but it is just a safety measure if 1141 * something goes really wrong. The wait will only happen in the very 1142 * unlikely case of a vblank happening exactly at the same time and 1143 * shouldn't exceed microseconds range. 1144 */ 1145 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending, 1146 !pending, 0, 10 * 1000); 1147 if (ret) 1148 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n"); 1149 1150 synchronize_irq(vop->irq); 1151 } 1152 1153 static void vop_crtc_atomic_flush(struct drm_crtc *crtc, 1154 struct drm_crtc_state *old_crtc_state) 1155 { 1156 struct drm_atomic_state *old_state = old_crtc_state->state; 1157 struct drm_plane_state *old_plane_state, *new_plane_state; 1158 struct vop *vop = to_vop(crtc); 1159 struct drm_plane *plane; 1160 int i; 1161 1162 if (WARN_ON(!vop->is_enabled)) 1163 return; 1164 1165 spin_lock(&vop->reg_lock); 1166 1167 vop_cfg_done(vop); 1168 1169 spin_unlock(&vop->reg_lock); 1170 1171 /* 1172 * There is a (rather unlikely) possiblity that a vblank interrupt 1173 * fired before we set the cfg_done bit. To avoid spuriously 1174 * signalling flip completion we need to wait for it to finish. 1175 */ 1176 vop_wait_for_irq_handler(vop); 1177 1178 spin_lock_irq(&crtc->dev->event_lock); 1179 if (crtc->state->event) { 1180 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1181 WARN_ON(vop->event); 1182 1183 vop->event = crtc->state->event; 1184 crtc->state->event = NULL; 1185 } 1186 spin_unlock_irq(&crtc->dev->event_lock); 1187 1188 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, 1189 new_plane_state, i) { 1190 if (!old_plane_state->fb) 1191 continue; 1192 1193 if (old_plane_state->fb == new_plane_state->fb) 1194 continue; 1195 1196 drm_framebuffer_get(old_plane_state->fb); 1197 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1198 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); 1199 set_bit(VOP_PENDING_FB_UNREF, &vop->pending); 1200 } 1201 } 1202 1203 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { 1204 .mode_fixup = vop_crtc_mode_fixup, 1205 .atomic_flush = vop_crtc_atomic_flush, 1206 .atomic_enable = vop_crtc_atomic_enable, 1207 .atomic_disable = vop_crtc_atomic_disable, 1208 }; 1209 1210 static void vop_crtc_destroy(struct drm_crtc *crtc) 1211 { 1212 drm_crtc_cleanup(crtc); 1213 } 1214 1215 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) 1216 { 1217 struct rockchip_crtc_state *rockchip_state; 1218 1219 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); 1220 if (!rockchip_state) 1221 return NULL; 1222 1223 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base); 1224 return &rockchip_state->base; 1225 } 1226 1227 static void vop_crtc_destroy_state(struct drm_crtc *crtc, 1228 struct drm_crtc_state *state) 1229 { 1230 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state); 1231 1232 __drm_atomic_helper_crtc_destroy_state(&s->base); 1233 kfree(s); 1234 } 1235 1236 static void vop_crtc_reset(struct drm_crtc *crtc) 1237 { 1238 struct rockchip_crtc_state *crtc_state = 1239 kzalloc(sizeof(*crtc_state), GFP_KERNEL); 1240 1241 if (crtc->state) 1242 vop_crtc_destroy_state(crtc, crtc->state); 1243 1244 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); 1245 } 1246 1247 #ifdef CONFIG_DRM_ANALOGIX_DP 1248 static struct drm_connector *vop_get_edp_connector(struct vop *vop) 1249 { 1250 struct drm_connector *connector; 1251 struct drm_connector_list_iter conn_iter; 1252 1253 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter); 1254 drm_for_each_connector_iter(connector, &conn_iter) { 1255 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1256 drm_connector_list_iter_end(&conn_iter); 1257 return connector; 1258 } 1259 } 1260 drm_connector_list_iter_end(&conn_iter); 1261 1262 return NULL; 1263 } 1264 1265 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1266 const char *source_name) 1267 { 1268 struct vop *vop = to_vop(crtc); 1269 struct drm_connector *connector; 1270 int ret; 1271 1272 connector = vop_get_edp_connector(vop); 1273 if (!connector) 1274 return -EINVAL; 1275 1276 if (source_name && strcmp(source_name, "auto") == 0) 1277 ret = analogix_dp_start_crc(connector); 1278 else if (!source_name) 1279 ret = analogix_dp_stop_crc(connector); 1280 else 1281 ret = -EINVAL; 1282 1283 return ret; 1284 } 1285 1286 static int 1287 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1288 size_t *values_cnt) 1289 { 1290 if (source_name && strcmp(source_name, "auto") != 0) 1291 return -EINVAL; 1292 1293 *values_cnt = 3; 1294 return 0; 1295 } 1296 1297 #else 1298 static int vop_crtc_set_crc_source(struct drm_crtc *crtc, 1299 const char *source_name) 1300 { 1301 return -ENODEV; 1302 } 1303 1304 static int 1305 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, 1306 size_t *values_cnt) 1307 { 1308 return -ENODEV; 1309 } 1310 #endif 1311 1312 static const struct drm_crtc_funcs vop_crtc_funcs = { 1313 .set_config = drm_atomic_helper_set_config, 1314 .page_flip = drm_atomic_helper_page_flip, 1315 .destroy = vop_crtc_destroy, 1316 .reset = vop_crtc_reset, 1317 .atomic_duplicate_state = vop_crtc_duplicate_state, 1318 .atomic_destroy_state = vop_crtc_destroy_state, 1319 .enable_vblank = vop_crtc_enable_vblank, 1320 .disable_vblank = vop_crtc_disable_vblank, 1321 .set_crc_source = vop_crtc_set_crc_source, 1322 .verify_crc_source = vop_crtc_verify_crc_source, 1323 }; 1324 1325 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) 1326 { 1327 struct vop *vop = container_of(work, struct vop, fb_unref_work); 1328 struct drm_framebuffer *fb = val; 1329 1330 drm_crtc_vblank_put(&vop->crtc); 1331 drm_framebuffer_put(fb); 1332 } 1333 1334 static void vop_handle_vblank(struct vop *vop) 1335 { 1336 struct drm_device *drm = vop->drm_dev; 1337 struct drm_crtc *crtc = &vop->crtc; 1338 1339 spin_lock(&drm->event_lock); 1340 if (vop->event) { 1341 drm_crtc_send_vblank_event(crtc, vop->event); 1342 drm_crtc_vblank_put(crtc); 1343 vop->event = NULL; 1344 } 1345 spin_unlock(&drm->event_lock); 1346 1347 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending)) 1348 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq); 1349 } 1350 1351 static irqreturn_t vop_isr(int irq, void *data) 1352 { 1353 struct vop *vop = data; 1354 struct drm_crtc *crtc = &vop->crtc; 1355 uint32_t active_irqs; 1356 int ret = IRQ_NONE; 1357 1358 /* 1359 * The irq is shared with the iommu. If the runtime-pm state of the 1360 * vop-device is disabled the irq has to be targeted at the iommu. 1361 */ 1362 if (!pm_runtime_get_if_in_use(vop->dev)) 1363 return IRQ_NONE; 1364 1365 if (vop_core_clks_enable(vop)) { 1366 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); 1367 goto out; 1368 } 1369 1370 /* 1371 * interrupt register has interrupt status, enable and clear bits, we 1372 * must hold irq_lock to avoid a race with enable/disable_vblank(). 1373 */ 1374 spin_lock(&vop->irq_lock); 1375 1376 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); 1377 /* Clear all active interrupt sources */ 1378 if (active_irqs) 1379 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); 1380 1381 spin_unlock(&vop->irq_lock); 1382 1383 /* This is expected for vop iommu irqs, since the irq is shared */ 1384 if (!active_irqs) 1385 goto out_disable; 1386 1387 if (active_irqs & DSP_HOLD_VALID_INTR) { 1388 complete(&vop->dsp_hold_completion); 1389 active_irqs &= ~DSP_HOLD_VALID_INTR; 1390 ret = IRQ_HANDLED; 1391 } 1392 1393 if (active_irqs & LINE_FLAG_INTR) { 1394 complete(&vop->line_flag_completion); 1395 active_irqs &= ~LINE_FLAG_INTR; 1396 ret = IRQ_HANDLED; 1397 } 1398 1399 if (active_irqs & FS_INTR) { 1400 drm_crtc_handle_vblank(crtc); 1401 vop_handle_vblank(vop); 1402 active_irqs &= ~FS_INTR; 1403 ret = IRQ_HANDLED; 1404 } 1405 1406 /* Unhandled irqs are spurious. */ 1407 if (active_irqs) 1408 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", 1409 active_irqs); 1410 1411 out_disable: 1412 vop_core_clks_disable(vop); 1413 out: 1414 pm_runtime_put(vop->dev); 1415 return ret; 1416 } 1417 1418 static void vop_plane_add_properties(struct drm_plane *plane, 1419 const struct vop_win_data *win_data) 1420 { 1421 unsigned int flags = 0; 1422 1423 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0; 1424 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0; 1425 if (flags) 1426 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1427 DRM_MODE_ROTATE_0 | flags); 1428 } 1429 1430 static int vop_create_crtc(struct vop *vop) 1431 { 1432 const struct vop_data *vop_data = vop->data; 1433 struct device *dev = vop->dev; 1434 struct drm_device *drm_dev = vop->drm_dev; 1435 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp; 1436 struct drm_crtc *crtc = &vop->crtc; 1437 struct device_node *port; 1438 int ret; 1439 int i; 1440 1441 /* 1442 * Create drm_plane for primary and cursor planes first, since we need 1443 * to pass them to drm_crtc_init_with_planes, which sets the 1444 * "possible_crtcs" to the newly initialized crtc. 1445 */ 1446 for (i = 0; i < vop_data->win_size; i++) { 1447 struct vop_win *vop_win = &vop->win[i]; 1448 const struct vop_win_data *win_data = vop_win->data; 1449 1450 if (win_data->type != DRM_PLANE_TYPE_PRIMARY && 1451 win_data->type != DRM_PLANE_TYPE_CURSOR) 1452 continue; 1453 1454 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1455 0, &vop_plane_funcs, 1456 win_data->phy->data_formats, 1457 win_data->phy->nformats, 1458 NULL, win_data->type, NULL); 1459 if (ret) { 1460 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n", 1461 ret); 1462 goto err_cleanup_planes; 1463 } 1464 1465 plane = &vop_win->base; 1466 drm_plane_helper_add(plane, &plane_helper_funcs); 1467 vop_plane_add_properties(plane, win_data); 1468 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 1469 primary = plane; 1470 else if (plane->type == DRM_PLANE_TYPE_CURSOR) 1471 cursor = plane; 1472 } 1473 1474 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, 1475 &vop_crtc_funcs, NULL); 1476 if (ret) 1477 goto err_cleanup_planes; 1478 1479 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs); 1480 1481 /* 1482 * Create drm_planes for overlay windows with possible_crtcs restricted 1483 * to the newly created crtc. 1484 */ 1485 for (i = 0; i < vop_data->win_size; i++) { 1486 struct vop_win *vop_win = &vop->win[i]; 1487 const struct vop_win_data *win_data = vop_win->data; 1488 unsigned long possible_crtcs = drm_crtc_mask(crtc); 1489 1490 if (win_data->type != DRM_PLANE_TYPE_OVERLAY) 1491 continue; 1492 1493 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 1494 possible_crtcs, 1495 &vop_plane_funcs, 1496 win_data->phy->data_formats, 1497 win_data->phy->nformats, 1498 NULL, win_data->type, NULL); 1499 if (ret) { 1500 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", 1501 ret); 1502 goto err_cleanup_crtc; 1503 } 1504 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); 1505 vop_plane_add_properties(&vop_win->base, win_data); 1506 } 1507 1508 port = of_get_child_by_name(dev->of_node, "port"); 1509 if (!port) { 1510 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n", 1511 dev->of_node); 1512 ret = -ENOENT; 1513 goto err_cleanup_crtc; 1514 } 1515 1516 drm_flip_work_init(&vop->fb_unref_work, "fb_unref", 1517 vop_fb_unref_worker); 1518 1519 init_completion(&vop->dsp_hold_completion); 1520 init_completion(&vop->line_flag_completion); 1521 crtc->port = port; 1522 1523 return 0; 1524 1525 err_cleanup_crtc: 1526 drm_crtc_cleanup(crtc); 1527 err_cleanup_planes: 1528 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1529 head) 1530 drm_plane_cleanup(plane); 1531 return ret; 1532 } 1533 1534 static void vop_destroy_crtc(struct vop *vop) 1535 { 1536 struct drm_crtc *crtc = &vop->crtc; 1537 struct drm_device *drm_dev = vop->drm_dev; 1538 struct drm_plane *plane, *tmp; 1539 1540 of_node_put(crtc->port); 1541 1542 /* 1543 * We need to cleanup the planes now. Why? 1544 * 1545 * The planes are "&vop->win[i].base". That means the memory is 1546 * all part of the big "struct vop" chunk of memory. That memory 1547 * was devm allocated and associated with this component. We need to 1548 * free it ourselves before vop_unbind() finishes. 1549 */ 1550 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list, 1551 head) 1552 vop_plane_destroy(plane); 1553 1554 /* 1555 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane() 1556 * references the CRTC. 1557 */ 1558 drm_crtc_cleanup(crtc); 1559 drm_flip_work_cleanup(&vop->fb_unref_work); 1560 } 1561 1562 static int vop_initial(struct vop *vop) 1563 { 1564 const struct vop_data *vop_data = vop->data; 1565 struct reset_control *ahb_rst; 1566 int i, ret; 1567 1568 vop->hclk = devm_clk_get(vop->dev, "hclk_vop"); 1569 if (IS_ERR(vop->hclk)) { 1570 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n"); 1571 return PTR_ERR(vop->hclk); 1572 } 1573 vop->aclk = devm_clk_get(vop->dev, "aclk_vop"); 1574 if (IS_ERR(vop->aclk)) { 1575 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n"); 1576 return PTR_ERR(vop->aclk); 1577 } 1578 vop->dclk = devm_clk_get(vop->dev, "dclk_vop"); 1579 if (IS_ERR(vop->dclk)) { 1580 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n"); 1581 return PTR_ERR(vop->dclk); 1582 } 1583 1584 ret = pm_runtime_get_sync(vop->dev); 1585 if (ret < 0) { 1586 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); 1587 return ret; 1588 } 1589 1590 ret = clk_prepare(vop->dclk); 1591 if (ret < 0) { 1592 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n"); 1593 goto err_put_pm_runtime; 1594 } 1595 1596 /* Enable both the hclk and aclk to setup the vop */ 1597 ret = clk_prepare_enable(vop->hclk); 1598 if (ret < 0) { 1599 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n"); 1600 goto err_unprepare_dclk; 1601 } 1602 1603 ret = clk_prepare_enable(vop->aclk); 1604 if (ret < 0) { 1605 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n"); 1606 goto err_disable_hclk; 1607 } 1608 1609 /* 1610 * do hclk_reset, reset all vop registers. 1611 */ 1612 ahb_rst = devm_reset_control_get(vop->dev, "ahb"); 1613 if (IS_ERR(ahb_rst)) { 1614 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n"); 1615 ret = PTR_ERR(ahb_rst); 1616 goto err_disable_aclk; 1617 } 1618 reset_control_assert(ahb_rst); 1619 usleep_range(10, 20); 1620 reset_control_deassert(ahb_rst); 1621 1622 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1); 1623 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0); 1624 1625 for (i = 0; i < vop->len; i += sizeof(u32)) 1626 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i); 1627 1628 VOP_REG_SET(vop, misc, global_regdone_en, 1); 1629 VOP_REG_SET(vop, common, dsp_blank, 0); 1630 1631 for (i = 0; i < vop_data->win_size; i++) { 1632 const struct vop_win_data *win = &vop_data->win[i]; 1633 int channel = i * 2 + 1; 1634 1635 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); 1636 vop_win_disable(vop, win); 1637 VOP_WIN_SET(vop, win, gate, 1); 1638 } 1639 1640 vop_cfg_done(vop); 1641 1642 /* 1643 * do dclk_reset, let all config take affect. 1644 */ 1645 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk"); 1646 if (IS_ERR(vop->dclk_rst)) { 1647 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n"); 1648 ret = PTR_ERR(vop->dclk_rst); 1649 goto err_disable_aclk; 1650 } 1651 reset_control_assert(vop->dclk_rst); 1652 usleep_range(10, 20); 1653 reset_control_deassert(vop->dclk_rst); 1654 1655 clk_disable(vop->hclk); 1656 clk_disable(vop->aclk); 1657 1658 vop->is_enabled = false; 1659 1660 pm_runtime_put_sync(vop->dev); 1661 1662 return 0; 1663 1664 err_disable_aclk: 1665 clk_disable_unprepare(vop->aclk); 1666 err_disable_hclk: 1667 clk_disable_unprepare(vop->hclk); 1668 err_unprepare_dclk: 1669 clk_unprepare(vop->dclk); 1670 err_put_pm_runtime: 1671 pm_runtime_put_sync(vop->dev); 1672 return ret; 1673 } 1674 1675 /* 1676 * Initialize the vop->win array elements. 1677 */ 1678 static void vop_win_init(struct vop *vop) 1679 { 1680 const struct vop_data *vop_data = vop->data; 1681 unsigned int i; 1682 1683 for (i = 0; i < vop_data->win_size; i++) { 1684 struct vop_win *vop_win = &vop->win[i]; 1685 const struct vop_win_data *win_data = &vop_data->win[i]; 1686 1687 vop_win->data = win_data; 1688 vop_win->vop = vop; 1689 1690 if (vop_data->win_yuv2yuv) 1691 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i]; 1692 } 1693 } 1694 1695 /** 1696 * rockchip_drm_wait_vact_end 1697 * @crtc: CRTC to enable line flag 1698 * @mstimeout: millisecond for timeout 1699 * 1700 * Wait for vact_end line flag irq or timeout. 1701 * 1702 * Returns: 1703 * Zero on success, negative errno on failure. 1704 */ 1705 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout) 1706 { 1707 struct vop *vop = to_vop(crtc); 1708 unsigned long jiffies_left; 1709 int ret = 0; 1710 1711 if (!crtc || !vop->is_enabled) 1712 return -ENODEV; 1713 1714 mutex_lock(&vop->vop_lock); 1715 if (mstimeout <= 0) { 1716 ret = -EINVAL; 1717 goto out; 1718 } 1719 1720 if (vop_line_flag_irq_is_enabled(vop)) { 1721 ret = -EBUSY; 1722 goto out; 1723 } 1724 1725 reinit_completion(&vop->line_flag_completion); 1726 vop_line_flag_irq_enable(vop); 1727 1728 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion, 1729 msecs_to_jiffies(mstimeout)); 1730 vop_line_flag_irq_disable(vop); 1731 1732 if (jiffies_left == 0) { 1733 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n"); 1734 ret = -ETIMEDOUT; 1735 goto out; 1736 } 1737 1738 out: 1739 mutex_unlock(&vop->vop_lock); 1740 return ret; 1741 } 1742 EXPORT_SYMBOL(rockchip_drm_wait_vact_end); 1743 1744 static int vop_bind(struct device *dev, struct device *master, void *data) 1745 { 1746 struct platform_device *pdev = to_platform_device(dev); 1747 const struct vop_data *vop_data; 1748 struct drm_device *drm_dev = data; 1749 struct vop *vop; 1750 struct resource *res; 1751 int ret, irq; 1752 1753 vop_data = of_device_get_match_data(dev); 1754 if (!vop_data) 1755 return -ENODEV; 1756 1757 /* Allocate vop struct and its vop_win array */ 1758 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size), 1759 GFP_KERNEL); 1760 if (!vop) 1761 return -ENOMEM; 1762 1763 vop->dev = dev; 1764 vop->data = vop_data; 1765 vop->drm_dev = drm_dev; 1766 dev_set_drvdata(dev, vop); 1767 1768 vop_win_init(vop); 1769 1770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1771 vop->len = resource_size(res); 1772 vop->regs = devm_ioremap_resource(dev, res); 1773 if (IS_ERR(vop->regs)) 1774 return PTR_ERR(vop->regs); 1775 1776 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL); 1777 if (!vop->regsbak) 1778 return -ENOMEM; 1779 1780 irq = platform_get_irq(pdev, 0); 1781 if (irq < 0) { 1782 DRM_DEV_ERROR(dev, "cannot find irq for vop\n"); 1783 return irq; 1784 } 1785 vop->irq = (unsigned int)irq; 1786 1787 spin_lock_init(&vop->reg_lock); 1788 spin_lock_init(&vop->irq_lock); 1789 mutex_init(&vop->vop_lock); 1790 1791 ret = vop_create_crtc(vop); 1792 if (ret) 1793 return ret; 1794 1795 pm_runtime_enable(&pdev->dev); 1796 1797 ret = vop_initial(vop); 1798 if (ret < 0) { 1799 DRM_DEV_ERROR(&pdev->dev, 1800 "cannot initial vop dev - err %d\n", ret); 1801 goto err_disable_pm_runtime; 1802 } 1803 1804 ret = devm_request_irq(dev, vop->irq, vop_isr, 1805 IRQF_SHARED, dev_name(dev), vop); 1806 if (ret) 1807 goto err_disable_pm_runtime; 1808 1809 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) { 1810 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev); 1811 if (IS_ERR(vop->rgb)) { 1812 ret = PTR_ERR(vop->rgb); 1813 goto err_disable_pm_runtime; 1814 } 1815 } 1816 1817 return 0; 1818 1819 err_disable_pm_runtime: 1820 pm_runtime_disable(&pdev->dev); 1821 vop_destroy_crtc(vop); 1822 return ret; 1823 } 1824 1825 static void vop_unbind(struct device *dev, struct device *master, void *data) 1826 { 1827 struct vop *vop = dev_get_drvdata(dev); 1828 1829 if (vop->rgb) 1830 rockchip_rgb_fini(vop->rgb); 1831 1832 pm_runtime_disable(dev); 1833 vop_destroy_crtc(vop); 1834 1835 clk_unprepare(vop->aclk); 1836 clk_unprepare(vop->hclk); 1837 clk_unprepare(vop->dclk); 1838 } 1839 1840 const struct component_ops vop_component_ops = { 1841 .bind = vop_bind, 1842 .unbind = vop_unbind, 1843 }; 1844 EXPORT_SYMBOL_GPL(vop_component_ops); 1845